2 * Support PCI/PCIe on PowerNV platforms
4 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/pci.h>
16 #include <linux/crash_dump.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/memblock.h>
21 #include <linux/irq.h>
23 #include <linux/msi.h>
24 #include <linux/iommu.h>
25 #include <linux/rculist.h>
26 #include <linux/sizes.h>
28 #include <asm/sections.h>
31 #include <asm/pci-bridge.h>
32 #include <asm/machdep.h>
33 #include <asm/msi_bitmap.h>
34 #include <asm/ppc-pci.h>
36 #include <asm/iommu.h>
39 #include <asm/debugfs.h>
40 #include <asm/firmware.h>
41 #include <asm/pnv-pci.h>
42 #include <asm/mmzone.h>
44 #include <misc/cxl-base.h>
48 #include "../../../../drivers/pci/pci.h"
50 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */
51 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */
52 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
54 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_NVLINK",
57 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
69 if (pe->flags & PNV_IODA_PE_DEV)
70 strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
71 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
72 sprintf(pfix, "%04x:%02x ",
73 pci_domain_nr(pe->pbus), pe->pbus->number);
75 else if (pe->flags & PNV_IODA_PE_VF)
76 sprintf(pfix, "%04x:%02x:%2x.%d",
77 pci_domain_nr(pe->parent_dev->bus),
78 (pe->rid & 0xff00) >> 8,
79 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
80 #endif /* CONFIG_PCI_IOV*/
82 printk("%spci %s: [PE# %.2x] %pV",
83 level, pfix, pe->pe_number, &vaf);
88 static bool pnv_iommu_bypass_disabled __read_mostly;
89 static bool pci_reset_phbs __read_mostly;
91 static int __init iommu_setup(char *str)
97 if (!strncmp(str, "nobypass", 8)) {
98 pnv_iommu_bypass_disabled = true;
99 pr_info("PowerNV: IOMMU bypass window disabled.\n");
102 str += strcspn(str, ",");
109 early_param("iommu", iommu_setup);
111 static int __init pci_reset_phbs_setup(char *str)
113 pci_reset_phbs = true;
117 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup);
119 static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r)
122 * WARNING: We cannot rely on the resource flags. The Linux PCI
123 * allocation code sometimes decides to put a 64-bit prefetchable
124 * BAR in the 32-bit window, so we have to compare the addresses.
126 * For simplicity we only test resource start.
128 return (r->start >= phb->ioda.m64_base &&
129 r->start < (phb->ioda.m64_base + phb->ioda.m64_size));
132 static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags)
134 unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
136 return (resource_flags & flags) == flags;
139 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
143 phb->ioda.pe_array[pe_no].phb = phb;
144 phb->ioda.pe_array[pe_no].pe_number = pe_no;
147 * Clear the PE frozen state as it might be put into frozen state
148 * in the last PCI remove path. It's not harmful to do so when the
149 * PE is already in unfrozen state.
151 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
152 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
153 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
154 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
155 __func__, rc, phb->hose->global_number, pe_no);
157 return &phb->ioda.pe_array[pe_no];
160 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
162 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
163 pr_warn("%s: Invalid PE %x on PHB#%x\n",
164 __func__, pe_no, phb->hose->global_number);
168 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
169 pr_debug("%s: PE %x was reserved on PHB#%x\n",
170 __func__, pe_no, phb->hose->global_number);
172 pnv_ioda_init_pe(phb, pe_no);
175 static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb)
179 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
180 if (!test_and_set_bit(pe, phb->ioda.pe_alloc))
181 return pnv_ioda_init_pe(phb, pe);
187 static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
189 struct pnv_phb *phb = pe->phb;
190 unsigned int pe_num = pe->pe_number;
194 memset(pe, 0, sizeof(struct pnv_ioda_pe));
195 clear_bit(pe_num, phb->ioda.pe_alloc);
198 /* The default M64 BAR is shared by all PEs */
199 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
205 /* Configure the default M64 BAR */
206 rc = opal_pci_set_phb_mem_window(phb->opal_id,
207 OPAL_M64_WINDOW_TYPE,
208 phb->ioda.m64_bar_idx,
212 if (rc != OPAL_SUCCESS) {
213 desc = "configuring";
217 /* Enable the default M64 BAR */
218 rc = opal_pci_phb_mmio_enable(phb->opal_id,
219 OPAL_M64_WINDOW_TYPE,
220 phb->ioda.m64_bar_idx,
221 OPAL_ENABLE_M64_SPLIT);
222 if (rc != OPAL_SUCCESS) {
228 * Exclude the segments for reserved and root bus PE, which
229 * are first or last two PEs.
231 r = &phb->hose->mem_resources[1];
232 if (phb->ioda.reserved_pe_idx == 0)
233 r->start += (2 * phb->ioda.m64_segsize);
234 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
235 r->end -= (2 * phb->ioda.m64_segsize);
237 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n",
238 phb->ioda.reserved_pe_idx);
243 pr_warn(" Failure %lld %s M64 BAR#%d\n",
244 rc, desc, phb->ioda.m64_bar_idx);
245 opal_pci_phb_mmio_enable(phb->opal_id,
246 OPAL_M64_WINDOW_TYPE,
247 phb->ioda.m64_bar_idx,
252 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
253 unsigned long *pe_bitmap)
255 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
256 struct pnv_phb *phb = hose->private_data;
258 resource_size_t base, sgsz, start, end;
261 base = phb->ioda.m64_base;
262 sgsz = phb->ioda.m64_segsize;
263 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
264 r = &pdev->resource[i];
265 if (!r->parent || !pnv_pci_is_m64(phb, r))
268 start = _ALIGN_DOWN(r->start - base, sgsz);
269 end = _ALIGN_UP(r->end - base, sgsz);
270 for (segno = start / sgsz; segno < end / sgsz; segno++) {
272 set_bit(segno, pe_bitmap);
274 pnv_ioda_reserve_pe(phb, segno);
279 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
285 * There are 16 M64 BARs, each of which has 8 segments. So
286 * there are as many M64 segments as the maximum number of
289 for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
290 unsigned long base, segsz = phb->ioda.m64_segsize;
293 base = phb->ioda.m64_base +
294 index * PNV_IODA1_M64_SEGS * segsz;
295 rc = opal_pci_set_phb_mem_window(phb->opal_id,
296 OPAL_M64_WINDOW_TYPE, index, base, 0,
297 PNV_IODA1_M64_SEGS * segsz);
298 if (rc != OPAL_SUCCESS) {
299 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n",
300 rc, phb->hose->global_number, index);
304 rc = opal_pci_phb_mmio_enable(phb->opal_id,
305 OPAL_M64_WINDOW_TYPE, index,
306 OPAL_ENABLE_M64_SPLIT);
307 if (rc != OPAL_SUCCESS) {
308 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n",
309 rc, phb->hose->global_number, index);
315 * Exclude the segments for reserved and root bus PE, which
316 * are first or last two PEs.
318 r = &phb->hose->mem_resources[1];
319 if (phb->ioda.reserved_pe_idx == 0)
320 r->start += (2 * phb->ioda.m64_segsize);
321 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
322 r->end -= (2 * phb->ioda.m64_segsize);
324 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
325 phb->ioda.reserved_pe_idx, phb->hose->global_number);
330 for ( ; index >= 0; index--)
331 opal_pci_phb_mmio_enable(phb->opal_id,
332 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
337 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
338 unsigned long *pe_bitmap,
341 struct pci_dev *pdev;
343 list_for_each_entry(pdev, &bus->devices, bus_list) {
344 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
346 if (all && pdev->subordinate)
347 pnv_ioda_reserve_m64_pe(pdev->subordinate,
352 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
354 struct pci_controller *hose = pci_bus_to_host(bus);
355 struct pnv_phb *phb = hose->private_data;
356 struct pnv_ioda_pe *master_pe, *pe;
357 unsigned long size, *pe_alloc;
360 /* Root bus shouldn't use M64 */
361 if (pci_is_root_bus(bus))
364 /* Allocate bitmap */
365 size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
366 pe_alloc = kzalloc(size, GFP_KERNEL);
368 pr_warn("%s: Out of memory !\n",
373 /* Figure out reserved PE numbers by the PE */
374 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
377 * the current bus might not own M64 window and that's all
378 * contributed by its child buses. For the case, we needn't
379 * pick M64 dependent PE#.
381 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
387 * Figure out the master PE and put all slave PEs to master
388 * PE's list to form compound PE.
392 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
393 phb->ioda.total_pe_num) {
394 pe = &phb->ioda.pe_array[i];
396 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
398 pe->flags |= PNV_IODA_PE_MASTER;
399 INIT_LIST_HEAD(&pe->slaves);
402 pe->flags |= PNV_IODA_PE_SLAVE;
403 pe->master = master_pe;
404 list_add_tail(&pe->list, &master_pe->slaves);
408 * P7IOC supports M64DT, which helps mapping M64 segment
409 * to one particular PE#. However, PHB3 has fixed mapping
410 * between M64 segment and PE#. In order to have same logic
411 * for P7IOC and PHB3, we enforce fixed mapping between M64
412 * segment and PE# on P7IOC.
414 if (phb->type == PNV_PHB_IODA1) {
417 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
418 pe->pe_number, OPAL_M64_WINDOW_TYPE,
419 pe->pe_number / PNV_IODA1_M64_SEGS,
420 pe->pe_number % PNV_IODA1_M64_SEGS);
421 if (rc != OPAL_SUCCESS)
422 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
423 __func__, rc, phb->hose->global_number,
432 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
434 struct pci_controller *hose = phb->hose;
435 struct device_node *dn = hose->dn;
436 struct resource *res;
441 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
442 pr_info(" Not support M64 window\n");
446 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
447 pr_info(" Firmware too old to support M64 window\n");
451 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
453 pr_info(" No <ibm,opal-m64-window> on %pOF\n",
459 * Find the available M64 BAR range and pickup the last one for
460 * covering the whole 64-bits space. We support only one range.
462 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
464 /* In absence of the property, assume 0..15 */
468 /* We only support 64 bits in our allocator */
469 if (m64_range[1] > 63) {
470 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
471 __func__, m64_range[1], phb->hose->global_number);
474 /* Empty range, no m64 */
475 if (m64_range[1] <= m64_range[0]) {
476 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
477 __func__, phb->hose->global_number);
481 /* Configure M64 informations */
482 res = &hose->mem_resources[1];
483 res->name = dn->full_name;
484 res->start = of_translate_address(dn, r + 2);
485 res->end = res->start + of_read_number(r + 4, 2) - 1;
486 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
487 pci_addr = of_read_number(r, 2);
488 hose->mem_offset[1] = res->start - pci_addr;
490 phb->ioda.m64_size = resource_size(res);
491 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
492 phb->ioda.m64_base = pci_addr;
494 /* This lines up nicely with the display from processing OF ranges */
495 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
496 res->start, res->end, pci_addr, m64_range[0],
497 m64_range[0] + m64_range[1] - 1);
499 /* Mark all M64 used up by default */
500 phb->ioda.m64_bar_alloc = (unsigned long)-1;
502 /* Use last M64 BAR to cover M64 window */
504 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
506 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
508 /* Mark remaining ones free */
509 for (i = m64_range[0]; i < m64_range[1]; i++)
510 clear_bit(i, &phb->ioda.m64_bar_alloc);
513 * Setup init functions for M64 based on IODA version, IODA3 uses
516 if (phb->type == PNV_PHB_IODA1)
517 phb->init_m64 = pnv_ioda1_init_m64;
519 phb->init_m64 = pnv_ioda2_init_m64;
520 phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe;
521 phb->pick_m64_pe = pnv_ioda_pick_m64_pe;
524 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
526 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
527 struct pnv_ioda_pe *slave;
530 /* Fetch master PE */
531 if (pe->flags & PNV_IODA_PE_SLAVE) {
533 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
536 pe_no = pe->pe_number;
539 /* Freeze master PE */
540 rc = opal_pci_eeh_freeze_set(phb->opal_id,
542 OPAL_EEH_ACTION_SET_FREEZE_ALL);
543 if (rc != OPAL_SUCCESS) {
544 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
545 __func__, rc, phb->hose->global_number, pe_no);
549 /* Freeze slave PEs */
550 if (!(pe->flags & PNV_IODA_PE_MASTER))
553 list_for_each_entry(slave, &pe->slaves, list) {
554 rc = opal_pci_eeh_freeze_set(phb->opal_id,
556 OPAL_EEH_ACTION_SET_FREEZE_ALL);
557 if (rc != OPAL_SUCCESS)
558 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
559 __func__, rc, phb->hose->global_number,
564 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
566 struct pnv_ioda_pe *pe, *slave;
570 pe = &phb->ioda.pe_array[pe_no];
571 if (pe->flags & PNV_IODA_PE_SLAVE) {
573 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
574 pe_no = pe->pe_number;
577 /* Clear frozen state for master PE */
578 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
579 if (rc != OPAL_SUCCESS) {
580 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
581 __func__, rc, opt, phb->hose->global_number, pe_no);
585 if (!(pe->flags & PNV_IODA_PE_MASTER))
588 /* Clear frozen state for slave PEs */
589 list_for_each_entry(slave, &pe->slaves, list) {
590 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
593 if (rc != OPAL_SUCCESS) {
594 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
595 __func__, rc, opt, phb->hose->global_number,
604 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
606 struct pnv_ioda_pe *slave, *pe;
611 /* Sanity check on PE number */
612 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
613 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
616 * Fetch the master PE and the PE instance might be
617 * not initialized yet.
619 pe = &phb->ioda.pe_array[pe_no];
620 if (pe->flags & PNV_IODA_PE_SLAVE) {
622 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
623 pe_no = pe->pe_number;
626 /* Check the master PE */
627 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
628 &state, &pcierr, NULL);
629 if (rc != OPAL_SUCCESS) {
630 pr_warn("%s: Failure %lld getting "
631 "PHB#%x-PE#%x state\n",
633 phb->hose->global_number, pe_no);
634 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
637 /* Check the slave PE */
638 if (!(pe->flags & PNV_IODA_PE_MASTER))
641 list_for_each_entry(slave, &pe->slaves, list) {
642 rc = opal_pci_eeh_freeze_status(phb->opal_id,
647 if (rc != OPAL_SUCCESS) {
648 pr_warn("%s: Failure %lld getting "
649 "PHB#%x-PE#%x state\n",
651 phb->hose->global_number, slave->pe_number);
652 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
656 * Override the result based on the ascending
666 /* Currently those 2 are only used when MSIs are enabled, this will change
667 * but in the meantime, we need to protect them to avoid warnings
669 #ifdef CONFIG_PCI_MSI
670 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
672 struct pci_controller *hose = pci_bus_to_host(dev->bus);
673 struct pnv_phb *phb = hose->private_data;
674 struct pci_dn *pdn = pci_get_pdn(dev);
678 if (pdn->pe_number == IODA_INVALID_PE)
680 return &phb->ioda.pe_array[pdn->pe_number];
682 #endif /* CONFIG_PCI_MSI */
684 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
685 struct pnv_ioda_pe *parent,
686 struct pnv_ioda_pe *child,
689 const char *desc = is_add ? "adding" : "removing";
690 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
691 OPAL_REMOVE_PE_FROM_DOMAIN;
692 struct pnv_ioda_pe *slave;
695 /* Parent PE affects child PE */
696 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
697 child->pe_number, op);
698 if (rc != OPAL_SUCCESS) {
699 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
704 if (!(child->flags & PNV_IODA_PE_MASTER))
707 /* Compound case: parent PE affects slave PEs */
708 list_for_each_entry(slave, &child->slaves, list) {
709 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
710 slave->pe_number, op);
711 if (rc != OPAL_SUCCESS) {
712 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
721 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
722 struct pnv_ioda_pe *pe,
725 struct pnv_ioda_pe *slave;
726 struct pci_dev *pdev = NULL;
730 * Clear PE frozen state. If it's master PE, we need
731 * clear slave PE frozen state as well.
734 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
735 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
736 if (pe->flags & PNV_IODA_PE_MASTER) {
737 list_for_each_entry(slave, &pe->slaves, list)
738 opal_pci_eeh_freeze_clear(phb->opal_id,
740 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
745 * Associate PE in PELT. We need add the PE into the
746 * corresponding PELT-V as well. Otherwise, the error
747 * originated from the PE might contribute to other
750 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
754 /* For compound PEs, any one affects all of them */
755 if (pe->flags & PNV_IODA_PE_MASTER) {
756 list_for_each_entry(slave, &pe->slaves, list) {
757 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
763 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
764 pdev = pe->pbus->self;
765 else if (pe->flags & PNV_IODA_PE_DEV)
766 pdev = pe->pdev->bus->self;
767 #ifdef CONFIG_PCI_IOV
768 else if (pe->flags & PNV_IODA_PE_VF)
769 pdev = pe->parent_dev;
770 #endif /* CONFIG_PCI_IOV */
772 struct pci_dn *pdn = pci_get_pdn(pdev);
773 struct pnv_ioda_pe *parent;
775 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
776 parent = &phb->ioda.pe_array[pdn->pe_number];
777 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
782 pdev = pdev->bus->self;
788 static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
790 struct pci_dev *parent;
791 uint8_t bcomp, dcomp, fcomp;
795 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
799 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
800 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
801 parent = pe->pbus->self;
802 if (pe->flags & PNV_IODA_PE_BUS_ALL)
803 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
808 case 1: bcomp = OpalPciBusAll; break;
809 case 2: bcomp = OpalPciBus7Bits; break;
810 case 4: bcomp = OpalPciBus6Bits; break;
811 case 8: bcomp = OpalPciBus5Bits; break;
812 case 16: bcomp = OpalPciBus4Bits; break;
813 case 32: bcomp = OpalPciBus3Bits; break;
815 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
817 /* Do an exact match only */
818 bcomp = OpalPciBusAll;
820 rid_end = pe->rid + (count << 8);
822 #ifdef CONFIG_PCI_IOV
823 if (pe->flags & PNV_IODA_PE_VF)
824 parent = pe->parent_dev;
827 parent = pe->pdev->bus->self;
828 bcomp = OpalPciBusAll;
829 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
830 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
831 rid_end = pe->rid + 1;
834 /* Clear the reverse map */
835 for (rid = pe->rid; rid < rid_end; rid++)
836 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
838 /* Release from all parents PELT-V */
840 struct pci_dn *pdn = pci_get_pdn(parent);
841 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
842 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
843 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
844 /* XXX What to do in case of error ? */
846 parent = parent->bus->self;
849 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
850 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
852 /* Disassociate PE in PELT */
853 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
854 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
856 pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc);
857 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
858 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
860 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
864 #ifdef CONFIG_PCI_IOV
865 pe->parent_dev = NULL;
871 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
873 struct pci_dev *parent;
874 uint8_t bcomp, dcomp, fcomp;
875 long rc, rid_end, rid;
877 /* Bus validation ? */
881 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
882 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
883 parent = pe->pbus->self;
884 if (pe->flags & PNV_IODA_PE_BUS_ALL)
885 count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
890 case 1: bcomp = OpalPciBusAll; break;
891 case 2: bcomp = OpalPciBus7Bits; break;
892 case 4: bcomp = OpalPciBus6Bits; break;
893 case 8: bcomp = OpalPciBus5Bits; break;
894 case 16: bcomp = OpalPciBus4Bits; break;
895 case 32: bcomp = OpalPciBus3Bits; break;
897 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
899 /* Do an exact match only */
900 bcomp = OpalPciBusAll;
902 rid_end = pe->rid + (count << 8);
904 #ifdef CONFIG_PCI_IOV
905 if (pe->flags & PNV_IODA_PE_VF)
906 parent = pe->parent_dev;
908 #endif /* CONFIG_PCI_IOV */
909 parent = pe->pdev->bus->self;
910 bcomp = OpalPciBusAll;
911 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
912 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
913 rid_end = pe->rid + 1;
917 * Associate PE in PELT. We need add the PE into the
918 * corresponding PELT-V as well. Otherwise, the error
919 * originated from the PE might contribute to other
922 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
923 bcomp, dcomp, fcomp, OPAL_MAP_PE);
925 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
930 * Configure PELTV. NPUs don't have a PELTV table so skip
931 * configuration on them.
933 if (phb->type != PNV_PHB_NPU_NVLINK && phb->type != PNV_PHB_NPU_OCAPI)
934 pnv_ioda_set_peltv(phb, pe, true);
936 /* Setup reverse map */
937 for (rid = pe->rid; rid < rid_end; rid++)
938 phb->ioda.pe_rmap[rid] = pe->pe_number;
940 /* Setup one MVTs on IODA1 */
941 if (phb->type != PNV_PHB_IODA1) {
946 pe->mve_number = pe->pe_number;
947 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
948 if (rc != OPAL_SUCCESS) {
949 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
953 rc = opal_pci_set_mve_enable(phb->opal_id,
954 pe->mve_number, OPAL_ENABLE_MVE);
956 pe_err(pe, "OPAL error %ld enabling MVE %x\n",
966 #ifdef CONFIG_PCI_IOV
967 static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset)
969 struct pci_dn *pdn = pci_get_pdn(dev);
971 struct resource *res, res2;
972 resource_size_t size;
979 * "offset" is in VFs. The M64 windows are sized so that when they
980 * are segmented, each segment is the same size as the IOV BAR.
981 * Each segment is in a separate PE, and the high order bits of the
982 * address are the PE number. Therefore, each VF's BAR is in a
983 * separate PE, and changing the IOV BAR start address changes the
984 * range of PEs the VFs are in.
986 num_vfs = pdn->num_vfs;
987 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
988 res = &dev->resource[i + PCI_IOV_RESOURCES];
989 if (!res->flags || !res->parent)
993 * The actual IOV BAR range is determined by the start address
994 * and the actual size for num_vfs VFs BAR. This check is to
995 * make sure that after shifting, the range will not overlap
996 * with another device.
998 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
999 res2.flags = res->flags;
1000 res2.start = res->start + (size * offset);
1001 res2.end = res2.start + (size * num_vfs) - 1;
1003 if (res2.end > res->end) {
1004 dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n",
1005 i, &res2, res, num_vfs, offset);
1011 * Since M64 BAR shares segments among all possible 256 PEs,
1012 * we have to shift the beginning of PF IOV BAR to make it start from
1013 * the segment which belongs to the PE number assigned to the first VF.
1014 * This creates a "hole" in the /proc/iomem which could be used for
1015 * allocating other resources so we reserve this area below and
1016 * release when IOV is released.
1018 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1019 res = &dev->resource[i + PCI_IOV_RESOURCES];
1020 if (!res->flags || !res->parent)
1023 size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES);
1025 res->start += size * offset;
1027 dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n",
1028 i, &res2, res, (offset > 0) ? "En" : "Dis",
1032 devm_release_resource(&dev->dev, &pdn->holes[i]);
1033 memset(&pdn->holes[i], 0, sizeof(pdn->holes[i]));
1036 pci_update_resource(dev, i + PCI_IOV_RESOURCES);
1039 pdn->holes[i].start = res2.start;
1040 pdn->holes[i].end = res2.start + size * offset - 1;
1041 pdn->holes[i].flags = IORESOURCE_BUS;
1042 pdn->holes[i].name = "pnv_iov_reserved";
1043 devm_request_resource(&dev->dev, res->parent,
1049 #endif /* CONFIG_PCI_IOV */
1051 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
1053 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1054 struct pnv_phb *phb = hose->private_data;
1055 struct pci_dn *pdn = pci_get_pdn(dev);
1056 struct pnv_ioda_pe *pe;
1059 pr_err("%s: Device tree node not associated properly\n",
1063 if (pdn->pe_number != IODA_INVALID_PE)
1066 pe = pnv_ioda_alloc_pe(phb);
1068 pr_warn("%s: Not enough PE# available, disabling device\n",
1073 /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
1074 * pointer in the PE data structure, both should be destroyed at the
1075 * same time. However, this needs to be looked at more closely again
1076 * once we actually start removing things (Hotplug, SR-IOV, ...)
1078 * At some point we want to remove the PDN completely anyways
1081 pdn->pe_number = pe->pe_number;
1082 pe->flags = PNV_IODA_PE_DEV;
1085 pe->mve_number = -1;
1086 pe->rid = dev->bus->number << 8 | pdn->devfn;
1088 pe_info(pe, "Associated device to PE\n");
1090 if (pnv_ioda_configure_pe(phb, pe)) {
1091 /* XXX What do we do here ? */
1092 pnv_ioda_free_pe(pe);
1093 pdn->pe_number = IODA_INVALID_PE;
1099 /* Put PE to the list */
1100 list_add_tail(&pe->list, &phb->ioda.pe_list);
1105 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
1107 struct pci_dev *dev;
1109 list_for_each_entry(dev, &bus->devices, bus_list) {
1110 struct pci_dn *pdn = pci_get_pdn(dev);
1113 pr_warn("%s: No device node associated with device !\n",
1119 * In partial hotplug case, the PCI device might be still
1120 * associated with the PE and needn't attach it to the PE
1123 if (pdn->pe_number != IODA_INVALID_PE)
1127 pdn->pe_number = pe->pe_number;
1128 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1129 pnv_ioda_setup_same_PE(dev->subordinate, pe);
1134 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1135 * single PCI bus. Another one that contains the primary PCI bus and its
1136 * subordinate PCI devices and buses. The second type of PE is normally
1137 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1139 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1141 struct pci_controller *hose = pci_bus_to_host(bus);
1142 struct pnv_phb *phb = hose->private_data;
1143 struct pnv_ioda_pe *pe = NULL;
1144 unsigned int pe_num;
1147 * In partial hotplug case, the PE instance might be still alive.
1148 * We should reuse it instead of allocating a new one.
1150 pe_num = phb->ioda.pe_rmap[bus->number << 8];
1151 if (pe_num != IODA_INVALID_PE) {
1152 pe = &phb->ioda.pe_array[pe_num];
1153 pnv_ioda_setup_same_PE(bus, pe);
1157 /* PE number for root bus should have been reserved */
1158 if (pci_is_root_bus(bus) &&
1159 phb->ioda.root_pe_idx != IODA_INVALID_PE)
1160 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1162 /* Check if PE is determined by M64 */
1163 if (!pe && phb->pick_m64_pe)
1164 pe = phb->pick_m64_pe(bus, all);
1166 /* The PE number isn't pinned by M64 */
1168 pe = pnv_ioda_alloc_pe(phb);
1171 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1172 __func__, pci_domain_nr(bus), bus->number);
1176 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1179 pe->mve_number = -1;
1180 pe->rid = bus->busn_res.start << 8;
1183 pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n",
1184 bus->busn_res.start, bus->busn_res.end, pe->pe_number);
1186 pe_info(pe, "Secondary bus %d associated with PE#%x\n",
1187 bus->busn_res.start, pe->pe_number);
1189 if (pnv_ioda_configure_pe(phb, pe)) {
1190 /* XXX What do we do here ? */
1191 pnv_ioda_free_pe(pe);
1196 /* Associate it with all child devices */
1197 pnv_ioda_setup_same_PE(bus, pe);
1199 /* Put PE to the list */
1200 list_add_tail(&pe->list, &phb->ioda.pe_list);
1205 static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev)
1207 int pe_num, found_pe = false, rc;
1209 struct pnv_ioda_pe *pe;
1210 struct pci_dev *gpu_pdev;
1211 struct pci_dn *npu_pdn;
1212 struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus);
1213 struct pnv_phb *phb = hose->private_data;
1216 * Due to a hardware errata PE#0 on the NPU is reserved for
1217 * error handling. This means we only have three PEs remaining
1218 * which need to be assigned to four links, implying some
1219 * links must share PEs.
1221 * To achieve this we assign PEs such that NPUs linking the
1222 * same GPU get assigned the same PE.
1224 gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev);
1225 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
1226 pe = &phb->ioda.pe_array[pe_num];
1230 if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) {
1232 * This device has the same peer GPU so should
1233 * be assigned the same PE as the existing
1236 dev_info(&npu_pdev->dev,
1237 "Associating to existing PE %x\n", pe_num);
1238 pci_dev_get(npu_pdev);
1239 npu_pdn = pci_get_pdn(npu_pdev);
1240 rid = npu_pdev->bus->number << 8 | npu_pdn->devfn;
1241 npu_pdn->pe_number = pe_num;
1242 phb->ioda.pe_rmap[rid] = pe->pe_number;
1244 /* Map the PE to this link */
1245 rc = opal_pci_set_pe(phb->opal_id, pe_num, rid,
1247 OPAL_COMPARE_RID_DEVICE_NUMBER,
1248 OPAL_COMPARE_RID_FUNCTION_NUMBER,
1250 WARN_ON(rc != OPAL_SUCCESS);
1258 * Could not find an existing PE so allocate a new
1261 return pnv_ioda_setup_dev_PE(npu_pdev);
1266 static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus)
1268 struct pci_dev *pdev;
1270 list_for_each_entry(pdev, &bus->devices, bus_list)
1271 pnv_ioda_setup_npu_PE(pdev);
1274 static void pnv_pci_ioda_setup_PEs(void)
1276 struct pci_controller *hose, *tmp;
1277 struct pnv_phb *phb;
1278 struct pci_bus *bus;
1279 struct pci_dev *pdev;
1281 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1282 phb = hose->private_data;
1283 if (phb->type == PNV_PHB_NPU_NVLINK) {
1284 /* PE#0 is needed for error reporting */
1285 pnv_ioda_reserve_pe(phb, 0);
1286 pnv_ioda_setup_npu_PEs(hose->bus);
1287 if (phb->model == PNV_PHB_MODEL_NPU2)
1290 if (phb->type == PNV_PHB_NPU_OCAPI) {
1292 list_for_each_entry(pdev, &bus->devices, bus_list)
1293 pnv_ioda_setup_dev_PE(pdev);
1298 #ifdef CONFIG_PCI_IOV
1299 static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs)
1301 struct pci_bus *bus;
1302 struct pci_controller *hose;
1303 struct pnv_phb *phb;
1309 hose = pci_bus_to_host(bus);
1310 phb = hose->private_data;
1311 pdn = pci_get_pdn(pdev);
1313 if (pdn->m64_single_mode)
1318 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++)
1319 for (j = 0; j < m64_bars; j++) {
1320 if (pdn->m64_map[j][i] == IODA_INVALID_M64)
1322 opal_pci_phb_mmio_enable(phb->opal_id,
1323 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0);
1324 clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc);
1325 pdn->m64_map[j][i] = IODA_INVALID_M64;
1328 kfree(pdn->m64_map);
1332 static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs)
1334 struct pci_bus *bus;
1335 struct pci_controller *hose;
1336 struct pnv_phb *phb;
1339 struct resource *res;
1343 resource_size_t size, start;
1348 hose = pci_bus_to_host(bus);
1349 phb = hose->private_data;
1350 pdn = pci_get_pdn(pdev);
1351 total_vfs = pci_sriov_get_totalvfs(pdev);
1353 if (pdn->m64_single_mode)
1358 pdn->m64_map = kmalloc_array(m64_bars,
1359 sizeof(*pdn->m64_map),
1363 /* Initialize the m64_map to IODA_INVALID_M64 */
1364 for (i = 0; i < m64_bars ; i++)
1365 for (j = 0; j < PCI_SRIOV_NUM_BARS; j++)
1366 pdn->m64_map[i][j] = IODA_INVALID_M64;
1369 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1370 res = &pdev->resource[i + PCI_IOV_RESOURCES];
1371 if (!res->flags || !res->parent)
1374 for (j = 0; j < m64_bars; j++) {
1376 win = find_next_zero_bit(&phb->ioda.m64_bar_alloc,
1377 phb->ioda.m64_bar_idx + 1, 0);
1379 if (win >= phb->ioda.m64_bar_idx + 1)
1381 } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc));
1383 pdn->m64_map[j][i] = win;
1385 if (pdn->m64_single_mode) {
1386 size = pci_iov_resource_size(pdev,
1387 PCI_IOV_RESOURCES + i);
1388 start = res->start + size * j;
1390 size = resource_size(res);
1394 /* Map the M64 here */
1395 if (pdn->m64_single_mode) {
1396 pe_num = pdn->pe_num_map[j];
1397 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
1398 pe_num, OPAL_M64_WINDOW_TYPE,
1399 pdn->m64_map[j][i], 0);
1402 rc = opal_pci_set_phb_mem_window(phb->opal_id,
1403 OPAL_M64_WINDOW_TYPE,
1410 if (rc != OPAL_SUCCESS) {
1411 dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n",
1416 if (pdn->m64_single_mode)
1417 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1418 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2);
1420 rc = opal_pci_phb_mmio_enable(phb->opal_id,
1421 OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1);
1423 if (rc != OPAL_SUCCESS) {
1424 dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n",
1433 pnv_pci_vf_release_m64(pdev, num_vfs);
1437 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1440 static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe)
1442 struct iommu_table *tbl;
1445 tbl = pe->table_group.tables[0];
1446 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1448 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
1450 pnv_pci_ioda2_set_bypass(pe, false);
1451 if (pe->table_group.group) {
1452 iommu_group_put(pe->table_group.group);
1453 BUG_ON(pe->table_group.group);
1455 iommu_tce_table_put(tbl);
1458 static void pnv_ioda_release_vf_PE(struct pci_dev *pdev)
1460 struct pci_bus *bus;
1461 struct pci_controller *hose;
1462 struct pnv_phb *phb;
1463 struct pnv_ioda_pe *pe, *pe_n;
1467 hose = pci_bus_to_host(bus);
1468 phb = hose->private_data;
1469 pdn = pci_get_pdn(pdev);
1471 if (!pdev->is_physfn)
1474 list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) {
1475 if (pe->parent_dev != pdev)
1478 pnv_pci_ioda2_release_dma_pe(pdev, pe);
1480 /* Remove from list */
1481 mutex_lock(&phb->ioda.pe_list_mutex);
1482 list_del(&pe->list);
1483 mutex_unlock(&phb->ioda.pe_list_mutex);
1485 pnv_ioda_deconfigure_pe(phb, pe);
1487 pnv_ioda_free_pe(pe);
1491 void pnv_pci_sriov_disable(struct pci_dev *pdev)
1493 struct pci_bus *bus;
1494 struct pci_controller *hose;
1495 struct pnv_phb *phb;
1496 struct pnv_ioda_pe *pe;
1501 hose = pci_bus_to_host(bus);
1502 phb = hose->private_data;
1503 pdn = pci_get_pdn(pdev);
1504 num_vfs = pdn->num_vfs;
1506 /* Release VF PEs */
1507 pnv_ioda_release_vf_PE(pdev);
1509 if (phb->type == PNV_PHB_IODA2) {
1510 if (!pdn->m64_single_mode)
1511 pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map);
1513 /* Release M64 windows */
1514 pnv_pci_vf_release_m64(pdev, num_vfs);
1516 /* Release PE numbers */
1517 if (pdn->m64_single_mode) {
1518 for (i = 0; i < num_vfs; i++) {
1519 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1522 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1523 pnv_ioda_free_pe(pe);
1526 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1527 /* Releasing pe_num_map */
1528 kfree(pdn->pe_num_map);
1532 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1533 struct pnv_ioda_pe *pe);
1534 static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs)
1536 struct pci_bus *bus;
1537 struct pci_controller *hose;
1538 struct pnv_phb *phb;
1539 struct pnv_ioda_pe *pe;
1545 hose = pci_bus_to_host(bus);
1546 phb = hose->private_data;
1547 pdn = pci_get_pdn(pdev);
1549 if (!pdev->is_physfn)
1552 /* Reserve PE for each VF */
1553 for (vf_index = 0; vf_index < num_vfs; vf_index++) {
1554 if (pdn->m64_single_mode)
1555 pe_num = pdn->pe_num_map[vf_index];
1557 pe_num = *pdn->pe_num_map + vf_index;
1559 pe = &phb->ioda.pe_array[pe_num];
1560 pe->pe_number = pe_num;
1562 pe->flags = PNV_IODA_PE_VF;
1564 pe->parent_dev = pdev;
1565 pe->mve_number = -1;
1566 pe->rid = (pci_iov_virtfn_bus(pdev, vf_index) << 8) |
1567 pci_iov_virtfn_devfn(pdev, vf_index);
1569 pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n",
1570 hose->global_number, pdev->bus->number,
1571 PCI_SLOT(pci_iov_virtfn_devfn(pdev, vf_index)),
1572 PCI_FUNC(pci_iov_virtfn_devfn(pdev, vf_index)), pe_num);
1574 if (pnv_ioda_configure_pe(phb, pe)) {
1575 /* XXX What do we do here ? */
1576 pnv_ioda_free_pe(pe);
1581 /* Put PE to the list */
1582 mutex_lock(&phb->ioda.pe_list_mutex);
1583 list_add_tail(&pe->list, &phb->ioda.pe_list);
1584 mutex_unlock(&phb->ioda.pe_list_mutex);
1586 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1590 int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1592 struct pci_bus *bus;
1593 struct pci_controller *hose;
1594 struct pnv_phb *phb;
1595 struct pnv_ioda_pe *pe;
1601 hose = pci_bus_to_host(bus);
1602 phb = hose->private_data;
1603 pdn = pci_get_pdn(pdev);
1605 if (phb->type == PNV_PHB_IODA2) {
1606 if (!pdn->vfs_expanded) {
1607 dev_info(&pdev->dev, "don't support this SRIOV device"
1608 " with non 64bit-prefetchable IOV BAR\n");
1613 * When M64 BARs functions in Single PE mode, the number of VFs
1614 * could be enabled must be less than the number of M64 BARs.
1616 if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) {
1617 dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n");
1621 /* Allocating pe_num_map */
1622 if (pdn->m64_single_mode)
1623 pdn->pe_num_map = kmalloc_array(num_vfs,
1624 sizeof(*pdn->pe_num_map),
1627 pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL);
1629 if (!pdn->pe_num_map)
1632 if (pdn->m64_single_mode)
1633 for (i = 0; i < num_vfs; i++)
1634 pdn->pe_num_map[i] = IODA_INVALID_PE;
1636 /* Calculate available PE for required VFs */
1637 if (pdn->m64_single_mode) {
1638 for (i = 0; i < num_vfs; i++) {
1639 pe = pnv_ioda_alloc_pe(phb);
1645 pdn->pe_num_map[i] = pe->pe_number;
1648 mutex_lock(&phb->ioda.pe_alloc_mutex);
1649 *pdn->pe_num_map = bitmap_find_next_zero_area(
1650 phb->ioda.pe_alloc, phb->ioda.total_pe_num,
1652 if (*pdn->pe_num_map >= phb->ioda.total_pe_num) {
1653 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1654 dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs);
1655 kfree(pdn->pe_num_map);
1658 bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1659 mutex_unlock(&phb->ioda.pe_alloc_mutex);
1661 pdn->num_vfs = num_vfs;
1663 /* Assign M64 window accordingly */
1664 ret = pnv_pci_vf_assign_m64(pdev, num_vfs);
1666 dev_info(&pdev->dev, "Not enough M64 window resources\n");
1671 * When using one M64 BAR to map one IOV BAR, we need to shift
1672 * the IOV BAR according to the PE# allocated to the VFs.
1673 * Otherwise, the PE# for the VF will conflict with others.
1675 if (!pdn->m64_single_mode) {
1676 ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map);
1683 pnv_ioda_setup_vf_PE(pdev, num_vfs);
1688 if (pdn->m64_single_mode) {
1689 for (i = 0; i < num_vfs; i++) {
1690 if (pdn->pe_num_map[i] == IODA_INVALID_PE)
1693 pe = &phb->ioda.pe_array[pdn->pe_num_map[i]];
1694 pnv_ioda_free_pe(pe);
1697 bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs);
1699 /* Releasing pe_num_map */
1700 kfree(pdn->pe_num_map);
1705 int pnv_pcibios_sriov_disable(struct pci_dev *pdev)
1707 pnv_pci_sriov_disable(pdev);
1709 /* Release PCI data */
1710 remove_dev_pci_data(pdev);
1714 int pnv_pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
1716 /* Allocate PCI data */
1717 add_dev_pci_data(pdev);
1719 return pnv_pci_sriov_enable(pdev, num_vfs);
1721 #endif /* CONFIG_PCI_IOV */
1723 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
1725 struct pci_dn *pdn = pci_get_pdn(pdev);
1726 struct pnv_ioda_pe *pe;
1729 * The function can be called while the PE#
1730 * hasn't been assigned. Do nothing for the
1733 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1736 pe = &phb->ioda.pe_array[pdn->pe_number];
1737 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1738 set_dma_offset(&pdev->dev, pe->tce_bypass_base);
1739 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1741 * Note: iommu_add_device() will fail here as
1742 * for physical PE: the device is already added by now;
1743 * for virtual PE: sysfs entries are not ready yet and
1744 * tce_iommu_bus_notifier will add the device to a group later.
1748 static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe)
1750 unsigned short vendor = 0;
1751 struct pci_dev *pdev;
1753 if (pe->device_count == 1)
1756 /* pe->pdev should be set if it's a single device, pe->pbus if not */
1760 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
1762 vendor = pdev->vendor;
1766 if (pdev->vendor != vendor)
1774 * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1776 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1777 * Devices can only access more than that if bit 59 of the PCI address is set
1778 * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1779 * Many PCI devices are not capable of addressing that many bits, and as a
1780 * result are limited to the 4GB of virtual memory made available to 32-bit
1783 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1784 * devices by configuring the virtual memory past the first 4GB inaccessible
1785 * by 64-bit DMAs. This should only be used by devices that want more than
1786 * 4GB, and only on PEs that have no 32-bit devices.
1788 * Currently this will only work on PHB3 (POWER8).
1790 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1792 u64 window_size, table_size, tce_count, addr;
1793 struct page *table_pages;
1794 u64 tce_order = 28; /* 256MB TCEs */
1799 * Window size needs to be a power of two, but needs to account for
1800 * shifting memory by the 4GB offset required to skip 32bit space.
1802 window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1803 tce_count = window_size >> tce_order;
1804 table_size = tce_count << 3;
1806 if (table_size < PAGE_SIZE)
1807 table_size = PAGE_SIZE;
1809 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1810 get_order(table_size));
1814 tces = page_address(table_pages);
1818 memset(tces, 0, table_size);
1820 for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1821 tces[(addr + (1ULL << 32)) >> tce_order] =
1822 cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1825 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1827 /* reconfigure window 0 */
1828 (pe->pe_number << 1) + 0,
1833 if (rc == OPAL_SUCCESS) {
1834 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1838 pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1842 static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask)
1844 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1845 struct pnv_phb *phb = hose->private_data;
1846 struct pci_dn *pdn = pci_get_pdn(pdev);
1847 struct pnv_ioda_pe *pe;
1849 bool bypass = false;
1852 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1855 pe = &phb->ioda.pe_array[pdn->pe_number];
1856 if (pe->tce_bypass_enabled) {
1857 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1858 bypass = (dma_mask >= top);
1862 dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n");
1863 set_dma_ops(&pdev->dev, &dma_nommu_ops);
1866 * If the device can't set the TCE bypass bit but still wants
1867 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1868 * bypass the 32-bit region and be usable for 64-bit DMAs.
1869 * The device needs to be able to address all of this space.
1871 if (dma_mask >> 32 &&
1872 dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1873 pnv_pci_ioda_pe_single_vendor(pe) &&
1874 phb->model == PNV_PHB_MODEL_PHB3) {
1875 /* Configure the bypass mode */
1876 rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1879 /* 4GB offset bypasses 32-bit space */
1880 set_dma_offset(&pdev->dev, (1ULL << 32));
1881 set_dma_ops(&pdev->dev, &dma_nommu_ops);
1882 } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) {
1884 * Fail the request if a DMA mask between 32 and 64 bits
1885 * was requested but couldn't be fulfilled. Ideally we
1886 * would do this for 64-bits but historically we have
1887 * always fallen back to 32-bits.
1891 dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n");
1892 set_dma_ops(&pdev->dev, &dma_iommu_ops);
1895 *pdev->dev.dma_mask = dma_mask;
1897 /* Update peer npu devices */
1898 pnv_npu_try_dma_set_bypass(pdev, bypass);
1903 static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev)
1905 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
1906 struct pnv_phb *phb = hose->private_data;
1907 struct pci_dn *pdn = pci_get_pdn(pdev);
1908 struct pnv_ioda_pe *pe;
1911 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1914 pe = &phb->ioda.pe_array[pdn->pe_number];
1915 if (!pe->tce_bypass_enabled)
1916 return __dma_get_required_mask(&pdev->dev);
1919 end = pe->tce_bypass_base + memblock_end_of_DRAM();
1920 mask = 1ULL << (fls64(end) - 1);
1926 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe,
1927 struct pci_bus *bus,
1930 struct pci_dev *dev;
1932 list_for_each_entry(dev, &bus->devices, bus_list) {
1933 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1934 set_dma_offset(&dev->dev, pe->tce_bypass_base);
1936 iommu_add_device(&dev->dev);
1938 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1939 pnv_ioda_setup_bus_dma(pe, dev->subordinate,
1944 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb,
1947 return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) :
1948 (phb->regs + 0x210);
1951 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1952 unsigned long index, unsigned long npages, bool rm)
1954 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1955 &tbl->it_group_list, struct iommu_table_group_link,
1957 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1958 struct pnv_ioda_pe, table_group);
1959 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
1960 unsigned long start, end, inc;
1962 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1963 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1966 /* p7ioc-style invalidation, 2 TCEs per write */
1967 start |= (1ull << 63);
1968 end |= (1ull << 63);
1970 end |= inc - 1; /* round up end to be different than start */
1972 mb(); /* Ensure above stores are visible */
1973 while (start <= end) {
1975 __raw_rm_writeq_be(start, invalidate);
1977 __raw_writeq_be(start, invalidate);
1983 * The iommu layer will do another mb() for us on build()
1984 * and we don't care on free()
1988 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1989 long npages, unsigned long uaddr,
1990 enum dma_data_direction direction,
1991 unsigned long attrs)
1993 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1997 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
2002 #ifdef CONFIG_IOMMU_API
2003 static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,
2004 unsigned long *hpa, enum dma_data_direction *direction)
2006 long ret = pnv_tce_xchg(tbl, index, hpa, direction, true);
2009 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false);
2014 static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index,
2015 unsigned long *hpa, enum dma_data_direction *direction)
2017 long ret = pnv_tce_xchg(tbl, index, hpa, direction, false);
2020 pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true);
2026 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
2029 pnv_tce_free(tbl, index, npages);
2031 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false);
2034 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
2035 .set = pnv_ioda1_tce_build,
2036 #ifdef CONFIG_IOMMU_API
2037 .exchange = pnv_ioda1_tce_xchg,
2038 .exchange_rm = pnv_ioda1_tce_xchg_rm,
2039 .useraddrptr = pnv_tce_useraddrptr,
2041 .clear = pnv_ioda1_tce_free,
2045 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
2046 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
2047 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
2049 static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2051 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm);
2052 const unsigned long val = PHB3_TCE_KILL_INVAL_ALL;
2054 mb(); /* Ensure previous TCE table stores are visible */
2056 __raw_rm_writeq_be(val, invalidate);
2058 __raw_writeq_be(val, invalidate);
2061 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2063 /* 01xb - invalidate TCEs that match the specified PE# */
2064 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false);
2065 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
2067 mb(); /* Ensure above stores are visible */
2068 __raw_writeq_be(val, invalidate);
2071 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm,
2072 unsigned shift, unsigned long index,
2073 unsigned long npages)
2075 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm);
2076 unsigned long start, end, inc;
2078 /* We'll invalidate DMA address in PE scope */
2079 start = PHB3_TCE_KILL_INVAL_ONE;
2080 start |= (pe->pe_number & 0xFF);
2083 /* Figure out the start, end and step */
2084 start |= (index << shift);
2085 end |= ((index + npages - 1) << shift);
2086 inc = (0x1ull << shift);
2089 while (start <= end) {
2091 __raw_rm_writeq_be(start, invalidate);
2093 __raw_writeq_be(start, invalidate);
2098 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
2100 struct pnv_phb *phb = pe->phb;
2102 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2103 pnv_pci_phb3_tce_invalidate_pe(pe);
2105 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
2106 pe->pe_number, 0, 0, 0);
2109 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
2110 unsigned long index, unsigned long npages, bool rm)
2112 struct iommu_table_group_link *tgl;
2114 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
2115 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
2116 struct pnv_ioda_pe, table_group);
2117 struct pnv_phb *phb = pe->phb;
2118 unsigned int shift = tbl->it_page_shift;
2121 * NVLink1 can use the TCE kill register directly as
2122 * it's the same as PHB3. NVLink2 is different and
2123 * should go via the OPAL call.
2125 if (phb->model == PNV_PHB_MODEL_NPU) {
2127 * The NVLink hardware does not support TCE kill
2128 * per TCE entry so we have to invalidate
2129 * the entire cache for it.
2131 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2134 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
2135 pnv_pci_phb3_tce_invalidate(pe, rm, shift,
2138 opal_pci_tce_kill(phb->opal_id,
2139 OPAL_PCI_TCE_KILL_PAGES,
2140 pe->pe_number, 1u << shift,
2141 index << shift, npages);
2145 void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm)
2147 if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3)
2148 pnv_pci_phb3_tce_invalidate_entire(phb, rm);
2150 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0);
2153 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
2154 long npages, unsigned long uaddr,
2155 enum dma_data_direction direction,
2156 unsigned long attrs)
2158 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
2162 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2167 #ifdef CONFIG_IOMMU_API
2168 static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,
2169 unsigned long *hpa, enum dma_data_direction *direction)
2171 long ret = pnv_tce_xchg(tbl, index, hpa, direction, true);
2174 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);
2179 static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index,
2180 unsigned long *hpa, enum dma_data_direction *direction)
2182 long ret = pnv_tce_xchg(tbl, index, hpa, direction, false);
2185 pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true);
2191 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
2194 pnv_tce_free(tbl, index, npages);
2196 pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false);
2199 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
2200 .set = pnv_ioda2_tce_build,
2201 #ifdef CONFIG_IOMMU_API
2202 .exchange = pnv_ioda2_tce_xchg,
2203 .exchange_rm = pnv_ioda2_tce_xchg_rm,
2204 .useraddrptr = pnv_tce_useraddrptr,
2206 .clear = pnv_ioda2_tce_free,
2208 .free = pnv_pci_ioda2_table_free_pages,
2211 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
2213 unsigned int *weight = (unsigned int *)data;
2215 /* This is quite simplistic. The "base" weight of a device
2216 * is 10. 0 means no DMA is to be accounted for it.
2218 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
2221 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
2222 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
2223 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
2225 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
2233 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
2235 unsigned int weight = 0;
2237 /* SRIOV VF has same DMA32 weight as its PF */
2238 #ifdef CONFIG_PCI_IOV
2239 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
2240 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
2245 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
2246 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
2247 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
2248 struct pci_dev *pdev;
2250 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
2251 pnv_pci_ioda_dev_dma_weight(pdev, &weight);
2252 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
2253 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
2259 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
2260 struct pnv_ioda_pe *pe)
2263 struct page *tce_mem = NULL;
2264 struct iommu_table *tbl;
2265 unsigned int weight, total_weight = 0;
2266 unsigned int tce32_segsz, base, segs, avail, i;
2270 /* XXX FIXME: Handle 64-bit only DMA devices */
2271 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
2272 /* XXX FIXME: Allocate multi-level tables on PHB3 */
2273 weight = pnv_pci_ioda_pe_dma_weight(pe);
2277 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
2279 segs = (weight * phb->ioda.dma32_count) / total_weight;
2284 * Allocate contiguous DMA32 segments. We begin with the expected
2285 * number of segments. With one more attempt, the number of DMA32
2286 * segments to be allocated is decreased by one until one segment
2287 * is allocated successfully.
2290 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
2291 for (avail = 0, i = base; i < base + segs; i++) {
2292 if (phb->ioda.dma32_segmap[i] ==
2303 pe_warn(pe, "No available DMA32 segments\n");
2308 tbl = pnv_pci_table_alloc(phb->hose->node);
2312 iommu_register_group(&pe->table_group, phb->hose->global_number,
2314 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
2316 /* Grab a 32-bit TCE table */
2317 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
2318 weight, total_weight, base, segs);
2319 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
2320 base * PNV_IODA1_DMA32_SEGSIZE,
2321 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
2323 /* XXX Currently, we allocate one big contiguous table for the
2324 * TCEs. We only really need one chunk per 256M of TCE space
2325 * (ie per segment) but that's an optimization for later, it
2326 * requires some added smarts with our get/put_tce implementation
2328 * Each TCE page is 4KB in size and each TCE entry occupies 8
2331 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
2332 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
2333 get_order(tce32_segsz * segs));
2335 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
2338 addr = page_address(tce_mem);
2339 memset(addr, 0, tce32_segsz * segs);
2342 for (i = 0; i < segs; i++) {
2343 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2346 __pa(addr) + tce32_segsz * i,
2347 tce32_segsz, IOMMU_PAGE_SIZE_4K);
2349 pe_err(pe, " Failed to configure 32-bit TCE table,"
2355 /* Setup DMA32 segment mapping */
2356 for (i = base; i < base + segs; i++)
2357 phb->ioda.dma32_segmap[i] = pe->pe_number;
2359 /* Setup linux iommu table */
2360 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
2361 base * PNV_IODA1_DMA32_SEGSIZE,
2362 IOMMU_PAGE_SHIFT_4K);
2364 tbl->it_ops = &pnv_ioda1_iommu_ops;
2365 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
2366 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
2367 iommu_init_table(tbl, phb->hose->node);
2369 if (pe->flags & PNV_IODA_PE_DEV) {
2371 * Setting table base here only for carrying iommu_group
2372 * further down to let iommu_add_device() do the job.
2373 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2375 set_iommu_table_base(&pe->pdev->dev, tbl);
2376 iommu_add_device(&pe->pdev->dev);
2377 } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2378 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2382 /* XXX Failure: Try to fallback to 64-bit only ? */
2384 __free_pages(tce_mem, get_order(tce32_segsz * segs));
2386 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
2387 iommu_tce_table_put(tbl);
2391 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
2392 int num, struct iommu_table *tbl)
2394 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2396 struct pnv_phb *phb = pe->phb;
2398 const unsigned long size = tbl->it_indirect_levels ?
2399 tbl->it_level_size : tbl->it_size;
2400 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
2401 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
2403 pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num,
2404 start_addr, start_addr + win_size - 1,
2405 IOMMU_PAGE_SIZE(tbl));
2408 * Map TCE table through TVT. The TVE index is the PE number
2409 * shifted by 1 bit for 32-bits DMA space.
2411 rc = opal_pci_map_pe_dma_window(phb->opal_id,
2413 (pe->pe_number << 1) + num,
2414 tbl->it_indirect_levels + 1,
2417 IOMMU_PAGE_SIZE(tbl));
2419 pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
2423 pnv_pci_link_table_and_group(phb->hose->node, num,
2424 tbl, &pe->table_group);
2425 pnv_pci_ioda2_tce_invalidate_pe(pe);
2430 void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
2432 uint16_t window_id = (pe->pe_number << 1 ) + 1;
2435 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
2437 phys_addr_t top = memblock_end_of_DRAM();
2439 top = roundup_pow_of_two(top);
2440 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2443 pe->tce_bypass_base,
2446 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
2449 pe->tce_bypass_base,
2453 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
2455 pe->tce_bypass_enabled = enable;
2458 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
2459 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2460 bool alloc_userspace_copy, struct iommu_table **ptbl)
2462 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2464 int nid = pe->phb->hose->node;
2465 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
2467 struct iommu_table *tbl;
2469 tbl = pnv_pci_table_alloc(nid);
2473 tbl->it_ops = &pnv_ioda2_iommu_ops;
2475 ret = pnv_pci_ioda2_table_alloc_pages(nid,
2476 bus_offset, page_shift, window_size,
2477 levels, alloc_userspace_copy, tbl);
2479 iommu_tce_table_put(tbl);
2488 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
2490 struct iommu_table *tbl = NULL;
2494 * crashkernel= specifies the kdump kernel's maximum memory at
2495 * some offset and there is no guaranteed the result is a power
2496 * of 2, which will cause errors later.
2498 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
2501 * In memory constrained environments, e.g. kdump kernel, the
2502 * DMA window can be larger than available memory, which will
2503 * cause errors later.
2505 const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory);
2507 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0,
2508 IOMMU_PAGE_SHIFT_4K,
2510 POWERNV_IOMMU_DEFAULT_LEVELS, false, &tbl);
2512 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
2517 iommu_init_table(tbl, pe->phb->hose->node);
2519 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
2521 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n",
2523 iommu_tce_table_put(tbl);
2527 if (!pnv_iommu_bypass_disabled)
2528 pnv_pci_ioda2_set_bypass(pe, true);
2531 * Setting table base here only for carrying iommu_group
2532 * further down to let iommu_add_device() do the job.
2533 * pnv_pci_ioda_dma_dev_setup will override it later anyway.
2535 if (pe->flags & PNV_IODA_PE_DEV)
2536 set_iommu_table_base(&pe->pdev->dev, tbl);
2541 #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV)
2542 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
2545 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2547 struct pnv_phb *phb = pe->phb;
2550 pe_info(pe, "Removing DMA window #%d\n", num);
2552 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2553 (pe->pe_number << 1) + num,
2554 0/* levels */, 0/* table address */,
2555 0/* table size */, 0/* page size */);
2557 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
2559 pnv_pci_ioda2_tce_invalidate_pe(pe);
2561 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2567 #ifdef CONFIG_IOMMU_API
2568 static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
2569 __u64 window_size, __u32 levels)
2571 unsigned long bytes = 0;
2572 const unsigned window_shift = ilog2(window_size);
2573 unsigned entries_shift = window_shift - page_shift;
2574 unsigned table_shift = entries_shift + 3;
2575 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
2576 unsigned long direct_table_size;
2578 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
2579 !is_power_of_2(window_size))
2582 /* Calculate a direct table size from window_size and levels */
2583 entries_shift = (entries_shift + levels - 1) / levels;
2584 table_shift = entries_shift + 3;
2585 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
2586 direct_table_size = 1UL << table_shift;
2588 for ( ; levels; --levels) {
2589 bytes += _ALIGN_UP(tce_table_size, direct_table_size);
2591 tce_table_size /= direct_table_size;
2592 tce_table_size <<= 3;
2593 tce_table_size = max_t(unsigned long,
2594 tce_table_size, direct_table_size);
2597 return bytes + bytes; /* one for HW table, one for userspace copy */
2600 static long pnv_pci_ioda2_create_table_userspace(
2601 struct iommu_table_group *table_group,
2602 int num, __u32 page_shift, __u64 window_size, __u32 levels,
2603 struct iommu_table **ptbl)
2605 return pnv_pci_ioda2_create_table(table_group,
2606 num, page_shift, window_size, levels, true, ptbl);
2609 static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
2611 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2613 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
2614 struct iommu_table *tbl = pe->table_group.tables[0];
2616 pnv_pci_ioda2_set_bypass(pe, false);
2617 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2619 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2620 iommu_tce_table_put(tbl);
2623 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
2625 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
2628 pnv_pci_ioda2_setup_default_config(pe);
2630 pnv_ioda_setup_bus_dma(pe, pe->pbus, false);
2633 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
2634 .get_table_size = pnv_pci_ioda2_get_table_size,
2635 .create_table = pnv_pci_ioda2_create_table_userspace,
2636 .set_window = pnv_pci_ioda2_set_window,
2637 .unset_window = pnv_pci_ioda2_unset_window,
2638 .take_ownership = pnv_ioda2_take_ownership,
2639 .release_ownership = pnv_ioda2_release_ownership,
2642 static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque)
2644 struct pci_controller *hose;
2645 struct pnv_phb *phb;
2646 struct pnv_ioda_pe **ptmppe = opaque;
2647 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
2648 struct pci_dn *pdn = pci_get_pdn(pdev);
2650 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2653 hose = pci_bus_to_host(pdev->bus);
2654 phb = hose->private_data;
2655 if (phb->type != PNV_PHB_NPU_NVLINK)
2658 *ptmppe = &phb->ioda.pe_array[pdn->pe_number];
2664 * This returns PE of associated NPU.
2665 * This assumes that NPU is in the same IOMMU group with GPU and there is
2668 static struct pnv_ioda_pe *gpe_table_group_to_npe(
2669 struct iommu_table_group *table_group)
2671 struct pnv_ioda_pe *npe = NULL;
2672 int ret = iommu_group_for_each_dev(table_group->group, &npe,
2673 gpe_table_group_to_npe_cb);
2675 BUG_ON(!ret || !npe);
2680 static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group,
2681 int num, struct iommu_table *tbl)
2683 struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group);
2684 int num2 = (num == 0) ? 1 : 0;
2685 long ret = pnv_pci_ioda2_set_window(table_group, num, tbl);
2690 if (table_group->tables[num2])
2691 pnv_npu_unset_window(npe, num2);
2693 ret = pnv_npu_set_window(npe, num, tbl);
2695 pnv_pci_ioda2_unset_window(table_group, num);
2696 if (table_group->tables[num2])
2697 pnv_npu_set_window(npe, num2,
2698 table_group->tables[num2]);
2704 static long pnv_pci_ioda2_npu_unset_window(
2705 struct iommu_table_group *table_group,
2708 struct pnv_ioda_pe *npe = gpe_table_group_to_npe(table_group);
2709 int num2 = (num == 0) ? 1 : 0;
2710 long ret = pnv_pci_ioda2_unset_window(table_group, num);
2715 if (!npe->table_group.tables[num])
2718 ret = pnv_npu_unset_window(npe, num);
2722 if (table_group->tables[num2])
2723 ret = pnv_npu_set_window(npe, num2, table_group->tables[num2]);
2728 static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group)
2731 * Detach NPU first as pnv_ioda2_take_ownership() will destroy
2732 * the iommu_table if 32bit DMA is enabled.
2734 pnv_npu_take_ownership(gpe_table_group_to_npe(table_group));
2735 pnv_ioda2_take_ownership(table_group);
2738 static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = {
2739 .get_table_size = pnv_pci_ioda2_get_table_size,
2740 .create_table = pnv_pci_ioda2_create_table_userspace,
2741 .set_window = pnv_pci_ioda2_npu_set_window,
2742 .unset_window = pnv_pci_ioda2_npu_unset_window,
2743 .take_ownership = pnv_ioda2_npu_take_ownership,
2744 .release_ownership = pnv_ioda2_release_ownership,
2747 static void pnv_pci_ioda_setup_iommu_api(void)
2749 struct pci_controller *hose, *tmp;
2750 struct pnv_phb *phb;
2751 struct pnv_ioda_pe *pe, *gpe;
2754 * Now we have all PHBs discovered, time to add NPU devices to
2755 * the corresponding IOMMU groups.
2757 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2758 phb = hose->private_data;
2760 if (phb->type != PNV_PHB_NPU_NVLINK)
2763 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2764 gpe = pnv_pci_npu_setup_iommu(pe);
2766 gpe->table_group.ops = &pnv_pci_ioda2_npu_ops;
2770 #else /* !CONFIG_IOMMU_API */
2771 static void pnv_pci_ioda_setup_iommu_api(void) { };
2774 static unsigned long pnv_ioda_parse_tce_sizes(struct pnv_phb *phb)
2776 struct pci_controller *hose = phb->hose;
2777 struct device_node *dn = hose->dn;
2778 unsigned long mask = 0;
2782 count = of_property_count_u32_elems(dn, "ibm,supported-tce-sizes");
2784 mask = SZ_4K | SZ_64K;
2785 /* Add 16M for POWER8 by default */
2786 if (cpu_has_feature(CPU_FTR_ARCH_207S) &&
2787 !cpu_has_feature(CPU_FTR_ARCH_300))
2788 mask |= SZ_16M | SZ_256M;
2792 for (i = 0; i < count; i++) {
2793 rc = of_property_read_u32_index(dn, "ibm,supported-tce-sizes",
2796 mask |= 1ULL << val;
2802 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
2803 struct pnv_ioda_pe *pe)
2807 if (!pnv_pci_ioda_pe_dma_weight(pe))
2810 /* TVE #1 is selected by PCI address bit 59 */
2811 pe->tce_bypass_base = 1ull << 59;
2813 iommu_register_group(&pe->table_group, phb->hose->global_number,
2816 /* The PE will reserve all possible 32-bits space */
2817 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
2818 phb->ioda.m32_pci_base);
2820 /* Setup linux iommu table */
2821 pe->table_group.tce32_start = 0;
2822 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
2823 pe->table_group.max_dynamic_windows_supported =
2824 IOMMU_TABLE_GROUP_MAX_TABLES;
2825 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
2826 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
2827 #ifdef CONFIG_IOMMU_API
2828 pe->table_group.ops = &pnv_pci_ioda2_ops;
2831 rc = pnv_pci_ioda2_setup_default_config(pe);
2835 if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
2836 pnv_ioda_setup_bus_dma(pe, pe->pbus, true);
2839 #ifdef CONFIG_PCI_MSI
2840 int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq)
2842 struct pnv_phb *phb = container_of(chip, struct pnv_phb,
2845 return opal_pci_msi_eoi(phb->opal_id, hw_irq);
2848 static void pnv_ioda2_msi_eoi(struct irq_data *d)
2851 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
2852 struct irq_chip *chip = irq_data_get_irq_chip(d);
2854 rc = pnv_opal_pci_msi_eoi(chip, hw_irq);
2861 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2863 struct irq_data *idata;
2864 struct irq_chip *ichip;
2866 /* The MSI EOI OPAL call is only needed on PHB3 */
2867 if (phb->model != PNV_PHB_MODEL_PHB3)
2870 if (!phb->ioda.irq_chip_init) {
2872 * First time we setup an MSI IRQ, we need to setup the
2873 * corresponding IRQ chip to route correctly.
2875 idata = irq_get_irq_data(virq);
2876 ichip = irq_data_get_irq_chip(idata);
2877 phb->ioda.irq_chip_init = 1;
2878 phb->ioda.irq_chip = *ichip;
2879 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2881 irq_set_chip(virq, &phb->ioda.irq_chip);
2885 * Returns true iff chip is something that we could call
2886 * pnv_opal_pci_msi_eoi for.
2888 bool is_pnv_opal_msi(struct irq_chip *chip)
2890 return chip->irq_eoi == pnv_ioda2_msi_eoi;
2892 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2894 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2895 unsigned int hwirq, unsigned int virq,
2896 unsigned int is_64, struct msi_msg *msg)
2898 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2899 unsigned int xive_num = hwirq - phb->msi_base;
2903 /* No PE assigned ? bail out ... no MSI for you ! */
2907 /* Check if we have an MVE */
2908 if (pe->mve_number < 0)
2911 /* Force 32-bit MSI on some broken devices */
2912 if (dev->no_64bit_msi)
2915 /* Assign XIVE to PE */
2916 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2918 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2919 pci_name(dev), rc, xive_num);
2926 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2929 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2933 msg->address_hi = be64_to_cpu(addr64) >> 32;
2934 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2938 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2941 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2945 msg->address_hi = 0;
2946 msg->address_lo = be32_to_cpu(addr32);
2948 msg->data = be32_to_cpu(data);
2950 pnv_set_msi_irq_chip(phb, virq);
2952 pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
2953 " address=%x_%08x data=%x PE# %x\n",
2954 pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
2955 msg->address_hi, msg->address_lo, data, pe->pe_number);
2960 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2963 const __be32 *prop = of_get_property(phb->hose->dn,
2964 "ibm,opal-msi-ranges", NULL);
2967 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2972 phb->msi_base = be32_to_cpup(prop);
2973 count = be32_to_cpup(prop + 1);
2974 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2975 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2976 phb->hose->global_number);
2980 phb->msi_setup = pnv_pci_ioda_msi_setup;
2981 phb->msi32_support = 1;
2982 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2983 count, phb->msi_base);
2986 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
2987 #endif /* CONFIG_PCI_MSI */
2989 #ifdef CONFIG_PCI_IOV
2990 static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev)
2992 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
2993 struct pnv_phb *phb = hose->private_data;
2994 const resource_size_t gate = phb->ioda.m64_segsize >> 2;
2995 struct resource *res;
2997 resource_size_t size, total_vf_bar_sz;
3001 if (!pdev->is_physfn || pci_dev_is_added(pdev))
3004 pdn = pci_get_pdn(pdev);
3005 pdn->vfs_expanded = 0;
3006 pdn->m64_single_mode = false;
3008 total_vfs = pci_sriov_get_totalvfs(pdev);
3009 mul = phb->ioda.total_pe_num;
3010 total_vf_bar_sz = 0;
3012 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3013 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3014 if (!res->flags || res->parent)
3016 if (!pnv_pci_is_m64_flags(res->flags)) {
3017 dev_warn(&pdev->dev, "Don't support SR-IOV with"
3018 " non M64 VF BAR%d: %pR. \n",
3023 total_vf_bar_sz += pci_iov_resource_size(pdev,
3024 i + PCI_IOV_RESOURCES);
3027 * If bigger than quarter of M64 segment size, just round up
3030 * Generally, one M64 BAR maps one IOV BAR. To avoid conflict
3031 * with other devices, IOV BAR size is expanded to be
3032 * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64
3033 * segment size , the expanded size would equal to half of the
3034 * whole M64 space size, which will exhaust the M64 Space and
3035 * limit the system flexibility. This is a design decision to
3036 * set the boundary to quarter of the M64 segment size.
3038 if (total_vf_bar_sz > gate) {
3039 mul = roundup_pow_of_two(total_vfs);
3040 dev_info(&pdev->dev,
3041 "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n",
3042 total_vf_bar_sz, gate, mul);
3043 pdn->m64_single_mode = true;
3048 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3049 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3050 if (!res->flags || res->parent)
3053 size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES);
3055 * On PHB3, the minimum size alignment of M64 BAR in single
3058 if (pdn->m64_single_mode && (size < SZ_32M))
3060 dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res);
3061 res->end = res->start + size * mul - 1;
3062 dev_dbg(&pdev->dev, " %pR\n", res);
3063 dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)",
3066 pdn->vfs_expanded = mul;
3071 /* To save MMIO space, IOV BAR is truncated. */
3072 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
3073 res = &pdev->resource[i + PCI_IOV_RESOURCES];
3075 res->end = res->start - 1;
3078 #endif /* CONFIG_PCI_IOV */
3080 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
3081 struct resource *res)
3083 struct pnv_phb *phb = pe->phb;
3084 struct pci_bus_region region;
3088 if (!res || !res->flags || res->start > res->end)
3091 if (res->flags & IORESOURCE_IO) {
3092 region.start = res->start - phb->ioda.io_pci_base;
3093 region.end = res->end - phb->ioda.io_pci_base;
3094 index = region.start / phb->ioda.io_segsize;
3096 while (index < phb->ioda.total_pe_num &&
3097 region.start <= region.end) {
3098 phb->ioda.io_segmap[index] = pe->pe_number;
3099 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3100 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
3101 if (rc != OPAL_SUCCESS) {
3102 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
3103 __func__, rc, index, pe->pe_number);
3107 region.start += phb->ioda.io_segsize;
3110 } else if ((res->flags & IORESOURCE_MEM) &&
3111 !pnv_pci_is_m64(phb, res)) {
3112 region.start = res->start -
3113 phb->hose->mem_offset[0] -
3114 phb->ioda.m32_pci_base;
3115 region.end = res->end -
3116 phb->hose->mem_offset[0] -
3117 phb->ioda.m32_pci_base;
3118 index = region.start / phb->ioda.m32_segsize;
3120 while (index < phb->ioda.total_pe_num &&
3121 region.start <= region.end) {
3122 phb->ioda.m32_segmap[index] = pe->pe_number;
3123 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3124 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
3125 if (rc != OPAL_SUCCESS) {
3126 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
3127 __func__, rc, index, pe->pe_number);
3131 region.start += phb->ioda.m32_segsize;
3138 * This function is supposed to be called on basis of PE from top
3139 * to bottom style. So the the I/O or MMIO segment assigned to
3140 * parent PE could be overridden by its child PEs if necessary.
3142 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
3144 struct pci_dev *pdev;
3148 * NOTE: We only care PCI bus based PE for now. For PCI
3149 * device based PE, for example SRIOV sensitive VF should
3150 * be figured out later.
3152 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
3154 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
3155 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
3156 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
3159 * If the PE contains all subordinate PCI buses, the
3160 * windows of the child bridges should be mapped to
3163 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
3165 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
3166 pnv_ioda_setup_pe_res(pe,
3167 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
3171 #ifdef CONFIG_DEBUG_FS
3172 static int pnv_pci_diag_data_set(void *data, u64 val)
3174 struct pci_controller *hose;
3175 struct pnv_phb *phb;
3181 hose = (struct pci_controller *)data;
3182 if (!hose || !hose->private_data)
3185 phb = hose->private_data;
3187 /* Retrieve the diag data from firmware */
3188 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
3189 phb->diag_data_size);
3190 if (ret != OPAL_SUCCESS)
3193 /* Print the diag data to the kernel log */
3194 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
3198 DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL,
3199 pnv_pci_diag_data_set, "%llu\n");
3201 #endif /* CONFIG_DEBUG_FS */
3203 static void pnv_pci_ioda_create_dbgfs(void)
3205 #ifdef CONFIG_DEBUG_FS
3206 struct pci_controller *hose, *tmp;
3207 struct pnv_phb *phb;
3210 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
3211 phb = hose->private_data;
3213 /* Notify initialization of PHB done */
3214 phb->initialized = 1;
3216 sprintf(name, "PCI%04x", hose->global_number);
3217 phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
3219 pr_warn("%s: Error on creating debugfs on PHB#%x\n",
3220 __func__, hose->global_number);
3224 debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose,
3225 &pnv_pci_diag_data_fops);
3227 #endif /* CONFIG_DEBUG_FS */
3230 static void pnv_pci_enable_bridge(struct pci_bus *bus)
3232 struct pci_dev *dev = bus->self;
3233 struct pci_bus *child;
3235 /* Empty bus ? bail */
3236 if (list_empty(&bus->devices))
3240 * If there's a bridge associated with that bus enable it. This works
3241 * around races in the generic code if the enabling is done during
3242 * parallel probing. This can be removed once those races have been
3246 int rc = pci_enable_device(dev);
3248 pci_err(dev, "Error enabling bridge (%d)\n", rc);
3249 pci_set_master(dev);
3252 /* Perform the same to child busses */
3253 list_for_each_entry(child, &bus->children, node)
3254 pnv_pci_enable_bridge(child);
3257 static void pnv_pci_enable_bridges(void)
3259 struct pci_controller *hose;
3261 list_for_each_entry(hose, &hose_list, list_node)
3262 pnv_pci_enable_bridge(hose->bus);
3265 static void pnv_pci_ioda_fixup(void)
3267 pnv_pci_ioda_setup_PEs();
3268 pnv_pci_ioda_setup_iommu_api();
3269 pnv_pci_ioda_create_dbgfs();
3271 pnv_pci_enable_bridges();
3274 pnv_eeh_post_init();
3279 * Returns the alignment for I/O or memory windows for P2P
3280 * bridges. That actually depends on how PEs are segmented.
3281 * For now, we return I/O or M32 segment size for PE sensitive
3282 * P2P bridges. Otherwise, the default values (4KiB for I/O,
3283 * 1MiB for memory) will be returned.
3285 * The current PCI bus might be put into one PE, which was
3286 * create against the parent PCI bridge. For that case, we
3287 * needn't enlarge the alignment so that we can save some
3290 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
3293 struct pci_dev *bridge;
3294 struct pci_controller *hose = pci_bus_to_host(bus);
3295 struct pnv_phb *phb = hose->private_data;
3296 int num_pci_bridges = 0;
3300 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
3302 if (num_pci_bridges >= 2)
3306 bridge = bridge->bus->self;
3310 * We fall back to M32 if M64 isn't supported. We enforce the M64
3311 * alignment for any 64-bit resource, PCIe doesn't care and
3312 * bridges only do 64-bit prefetchable anyway.
3314 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
3315 return phb->ioda.m64_segsize;
3316 if (type & IORESOURCE_MEM)
3317 return phb->ioda.m32_segsize;
3319 return phb->ioda.io_segsize;
3323 * We are updating root port or the upstream port of the
3324 * bridge behind the root port with PHB's windows in order
3325 * to accommodate the changes on required resources during
3326 * PCI (slot) hotplug, which is connected to either root
3327 * port or the downstream ports of PCIe switch behind the
3330 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
3333 struct pci_controller *hose = pci_bus_to_host(bus);
3334 struct pnv_phb *phb = hose->private_data;
3335 struct pci_dev *bridge = bus->self;
3336 struct resource *r, *w;
3337 bool msi_region = false;
3340 /* Check if we need apply fixup to the bridge's windows */
3341 if (!pci_is_root_bus(bridge->bus) &&
3342 !pci_is_root_bus(bridge->bus->self->bus))
3345 /* Fixup the resources */
3346 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
3347 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
3348 if (!r->flags || !r->parent)
3352 if (r->flags & type & IORESOURCE_IO)
3353 w = &hose->io_resource;
3354 else if (pnv_pci_is_m64(phb, r) &&
3355 (type & IORESOURCE_PREFETCH) &&
3356 phb->ioda.m64_segsize)
3357 w = &hose->mem_resources[1];
3358 else if (r->flags & type & IORESOURCE_MEM) {
3359 w = &hose->mem_resources[0];
3363 r->start = w->start;
3366 /* The 64KB 32-bits MSI region shouldn't be included in
3367 * the 32-bits bridge window. Otherwise, we can see strange
3368 * issues. One of them is EEH error observed on Garrison.
3370 * Exclude top 1MB region which is the minimal alignment of
3371 * 32-bits bridge window.
3380 static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type)
3382 struct pci_controller *hose = pci_bus_to_host(bus);
3383 struct pnv_phb *phb = hose->private_data;
3384 struct pci_dev *bridge = bus->self;
3385 struct pnv_ioda_pe *pe;
3386 bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
3388 /* Extend bridge's windows if necessary */
3389 pnv_pci_fixup_bridge_resources(bus, type);
3391 /* The PE for root bus should be realized before any one else */
3392 if (!phb->ioda.root_pe_populated) {
3393 pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false);
3395 phb->ioda.root_pe_idx = pe->pe_number;
3396 phb->ioda.root_pe_populated = true;
3400 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
3401 if (list_empty(&bus->devices))
3404 /* Reserve PEs according to used M64 resources */
3405 if (phb->reserve_m64_pe)
3406 phb->reserve_m64_pe(bus, NULL, all);
3409 * Assign PE. We might run here because of partial hotplug.
3410 * For the case, we just pick up the existing PE and should
3411 * not allocate resources again.
3413 pe = pnv_ioda_setup_bus_PE(bus, all);
3417 pnv_ioda_setup_pe_seg(pe);
3418 switch (phb->type) {
3420 pnv_pci_ioda1_setup_dma_pe(phb, pe);
3423 pnv_pci_ioda2_setup_dma_pe(phb, pe);
3426 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
3427 __func__, phb->hose->global_number, phb->type);
3431 static resource_size_t pnv_pci_default_alignment(void)
3436 #ifdef CONFIG_PCI_IOV
3437 static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev,
3440 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3441 struct pnv_phb *phb = hose->private_data;
3442 struct pci_dn *pdn = pci_get_pdn(pdev);
3443 resource_size_t align;
3446 * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the
3447 * SR-IOV. While from hardware perspective, the range mapped by M64
3448 * BAR should be size aligned.
3450 * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra
3451 * powernv-specific hardware restriction is gone. But if just use the
3452 * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with
3453 * in one segment of M64 #15, which introduces the PE conflict between
3454 * PF and VF. Based on this, the minimum alignment of an IOV BAR is
3457 * This function returns the total IOV BAR size if M64 BAR is in
3458 * Shared PE mode or just VF BAR size if not.
3459 * If the M64 BAR is in Single PE mode, return the VF BAR size or
3460 * M64 segment size if IOV BAR size is less.
3462 align = pci_iov_resource_size(pdev, resno);
3463 if (!pdn->vfs_expanded)
3465 if (pdn->m64_single_mode)
3466 return max(align, (resource_size_t)phb->ioda.m64_segsize);
3468 return pdn->vfs_expanded * align;
3470 #endif /* CONFIG_PCI_IOV */
3472 /* Prevent enabling devices for which we couldn't properly
3475 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
3477 struct pci_controller *hose = pci_bus_to_host(dev->bus);
3478 struct pnv_phb *phb = hose->private_data;
3481 /* The function is probably called while the PEs have
3482 * not be created yet. For example, resource reassignment
3483 * during PCI probe period. We just skip the check if
3486 if (!phb->initialized)
3489 pdn = pci_get_pdn(dev);
3490 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3496 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
3499 struct pnv_ioda_pe *pe = container_of(table_group,
3500 struct pnv_ioda_pe, table_group);
3501 struct pnv_phb *phb = pe->phb;
3505 pe_info(pe, "Removing DMA window #%d\n", num);
3506 for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
3507 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
3510 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
3511 idx, 0, 0ul, 0ul, 0ul);
3512 if (rc != OPAL_SUCCESS) {
3513 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
3518 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
3521 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
3522 return OPAL_SUCCESS;
3525 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
3527 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3528 struct iommu_table *tbl = pe->table_group.tables[0];
3534 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
3535 if (rc != OPAL_SUCCESS)
3538 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false);
3539 if (pe->table_group.group) {
3540 iommu_group_put(pe->table_group.group);
3541 WARN_ON(pe->table_group.group);
3544 free_pages(tbl->it_base, get_order(tbl->it_size << 3));
3545 iommu_tce_table_put(tbl);
3548 static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
3550 struct iommu_table *tbl = pe->table_group.tables[0];
3551 unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe);
3552 #ifdef CONFIG_IOMMU_API
3559 #ifdef CONFIG_IOMMU_API
3560 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
3562 pe_warn(pe, "OPAL error %ld release DMA window\n", rc);
3565 pnv_pci_ioda2_set_bypass(pe, false);
3566 if (pe->table_group.group) {
3567 iommu_group_put(pe->table_group.group);
3568 WARN_ON(pe->table_group.group);
3571 iommu_tce_table_put(tbl);
3574 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
3578 struct pnv_phb *phb = pe->phb;
3582 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
3583 if (map[idx] != pe->pe_number)
3586 if (win == OPAL_M64_WINDOW_TYPE)
3587 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3588 phb->ioda.reserved_pe_idx, win,
3589 idx / PNV_IODA1_M64_SEGS,
3590 idx % PNV_IODA1_M64_SEGS);
3592 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
3593 phb->ioda.reserved_pe_idx, win, 0, idx);
3595 if (rc != OPAL_SUCCESS)
3596 pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n",
3599 map[idx] = IODA_INVALID_PE;
3603 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
3605 struct pnv_phb *phb = pe->phb;
3607 if (phb->type == PNV_PHB_IODA1) {
3608 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
3609 phb->ioda.io_segmap);
3610 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3611 phb->ioda.m32_segmap);
3612 pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE,
3613 phb->ioda.m64_segmap);
3614 } else if (phb->type == PNV_PHB_IODA2) {
3615 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
3616 phb->ioda.m32_segmap);
3620 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
3622 struct pnv_phb *phb = pe->phb;
3623 struct pnv_ioda_pe *slave, *tmp;
3625 list_del(&pe->list);
3626 switch (phb->type) {
3628 pnv_pci_ioda1_release_pe_dma(pe);
3631 pnv_pci_ioda2_release_pe_dma(pe);
3637 pnv_ioda_release_pe_seg(pe);
3638 pnv_ioda_deconfigure_pe(pe->phb, pe);
3640 /* Release slave PEs in the compound PE */
3641 if (pe->flags & PNV_IODA_PE_MASTER) {
3642 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
3643 list_del(&slave->list);
3644 pnv_ioda_free_pe(slave);
3649 * The PE for root bus can be removed because of hotplug in EEH
3650 * recovery for fenced PHB error. We need to mark the PE dead so
3651 * that it can be populated again in PCI hot add path. The PE
3652 * shouldn't be destroyed as it's the global reserved resource.
3654 if (phb->ioda.root_pe_populated &&
3655 phb->ioda.root_pe_idx == pe->pe_number)
3656 phb->ioda.root_pe_populated = false;
3658 pnv_ioda_free_pe(pe);
3661 static void pnv_pci_release_device(struct pci_dev *pdev)
3663 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
3664 struct pnv_phb *phb = hose->private_data;
3665 struct pci_dn *pdn = pci_get_pdn(pdev);
3666 struct pnv_ioda_pe *pe;
3668 if (pdev->is_virtfn)
3671 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
3675 * PCI hotplug can happen as part of EEH error recovery. The @pdn
3676 * isn't removed and added afterwards in this scenario. We should
3677 * set the PE number in @pdn to an invalid one. Otherwise, the PE's
3678 * device count is decreased on removing devices while failing to
3679 * be increased on adding devices. It leads to unbalanced PE's device
3680 * count and eventually make normal PCI hotplug path broken.
3682 pe = &phb->ioda.pe_array[pdn->pe_number];
3683 pdn->pe_number = IODA_INVALID_PE;
3685 WARN_ON(--pe->device_count < 0);
3686 if (pe->device_count == 0)
3687 pnv_ioda_release_pe(pe);
3690 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
3692 struct pnv_phb *phb = hose->private_data;
3694 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
3698 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
3699 .dma_dev_setup = pnv_pci_dma_dev_setup,
3700 .dma_bus_setup = pnv_pci_dma_bus_setup,
3701 #ifdef CONFIG_PCI_MSI
3702 .setup_msi_irqs = pnv_setup_msi_irqs,
3703 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3705 .enable_device_hook = pnv_pci_enable_device_hook,
3706 .release_device = pnv_pci_release_device,
3707 .window_alignment = pnv_pci_window_alignment,
3708 .setup_bridge = pnv_pci_setup_bridge,
3709 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3710 .dma_set_mask = pnv_pci_ioda_dma_set_mask,
3711 .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask,
3712 .shutdown = pnv_pci_ioda_shutdown,
3715 static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask)
3717 dev_err_once(&npdev->dev,
3718 "%s operation unsupported for NVLink devices\n",
3723 static const struct pci_controller_ops pnv_npu_ioda_controller_ops = {
3724 .dma_dev_setup = pnv_pci_dma_dev_setup,
3725 #ifdef CONFIG_PCI_MSI
3726 .setup_msi_irqs = pnv_setup_msi_irqs,
3727 .teardown_msi_irqs = pnv_teardown_msi_irqs,
3729 .enable_device_hook = pnv_pci_enable_device_hook,
3730 .window_alignment = pnv_pci_window_alignment,
3731 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3732 .dma_set_mask = pnv_npu_dma_set_mask,
3733 .shutdown = pnv_pci_ioda_shutdown,
3736 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
3737 .enable_device_hook = pnv_pci_enable_device_hook,
3738 .window_alignment = pnv_pci_window_alignment,
3739 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
3740 .shutdown = pnv_pci_ioda_shutdown,
3743 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
3744 u64 hub_id, int ioda_type)
3746 struct pci_controller *hose;
3747 struct pnv_phb *phb;
3748 unsigned long size, m64map_off, m32map_off, pemap_off;
3749 unsigned long iomap_off = 0, dma32map_off = 0;
3751 const __be64 *prop64;
3752 const __be32 *prop32;
3759 if (!of_device_is_available(np))
3762 pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np);
3764 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3766 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3769 phb_id = be64_to_cpup(prop64);
3770 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3772 phb = memblock_alloc(sizeof(*phb), 0);
3774 /* Allocate PCI controller */
3775 phb->hose = hose = pcibios_alloc_controller(np);
3777 pr_err(" Can't allocate PCI controller for %pOF\n",
3779 memblock_free(__pa(phb), sizeof(struct pnv_phb));
3783 spin_lock_init(&phb->lock);
3784 prop32 = of_get_property(np, "bus-range", &len);
3785 if (prop32 && len == 8) {
3786 hose->first_busno = be32_to_cpu(prop32[0]);
3787 hose->last_busno = be32_to_cpu(prop32[1]);
3789 pr_warn(" Broken <bus-range> on %pOF\n", np);
3790 hose->first_busno = 0;
3791 hose->last_busno = 0xff;
3793 hose->private_data = phb;
3794 phb->hub_id = hub_id;
3795 phb->opal_id = phb_id;
3796 phb->type = ioda_type;
3797 mutex_init(&phb->ioda.pe_alloc_mutex);
3799 /* Detect specific models for error handling */
3800 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3801 phb->model = PNV_PHB_MODEL_P7IOC;
3802 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3803 phb->model = PNV_PHB_MODEL_PHB3;
3804 else if (of_device_is_compatible(np, "ibm,power8-npu-pciex"))
3805 phb->model = PNV_PHB_MODEL_NPU;
3806 else if (of_device_is_compatible(np, "ibm,power9-npu-pciex"))
3807 phb->model = PNV_PHB_MODEL_NPU2;
3809 phb->model = PNV_PHB_MODEL_UNKNOWN;
3811 /* Initialize diagnostic data buffer */
3812 prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
3814 phb->diag_data_size = be32_to_cpup(prop32);
3816 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
3818 phb->diag_data = memblock_alloc(phb->diag_data_size, 0);
3820 /* Parse 32-bit and IO ranges (if any) */
3821 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3824 if (!of_address_to_resource(np, 0, &r)) {
3825 phb->regs_phys = r.start;
3826 phb->regs = ioremap(r.start, resource_size(&r));
3827 if (phb->regs == NULL)
3828 pr_err(" Failed to map registers !\n");
3831 /* Initialize more IODA stuff */
3832 phb->ioda.total_pe_num = 1;
3833 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3835 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3836 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3838 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3840 /* Invalidate RID to PE# mapping */
3841 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3842 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3844 /* Parse 64-bit MMIO range */
3845 pnv_ioda_parse_m64_window(phb);
3847 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3848 /* FW Has already off top 64k of M32 space (MSI space) */
3849 phb->ioda.m32_size += 0x10000;
3851 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3852 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3853 phb->ioda.io_size = hose->pci_io_size;
3854 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3855 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3857 /* Calculate how many 32-bit TCE segments we have */
3858 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3859 PNV_IODA1_DMA32_SEGSIZE;
3861 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3862 size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3863 sizeof(unsigned long));
3865 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3867 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3868 if (phb->type == PNV_PHB_IODA1) {
3870 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3871 dma32map_off = size;
3872 size += phb->ioda.dma32_count *
3873 sizeof(phb->ioda.dma32_segmap[0]);
3876 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3877 aux = memblock_alloc(size, 0);
3878 phb->ioda.pe_alloc = aux;
3879 phb->ioda.m64_segmap = aux + m64map_off;
3880 phb->ioda.m32_segmap = aux + m32map_off;
3881 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3882 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3883 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3885 if (phb->type == PNV_PHB_IODA1) {
3886 phb->ioda.io_segmap = aux + iomap_off;
3887 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3888 phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3890 phb->ioda.dma32_segmap = aux + dma32map_off;
3891 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3892 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3894 phb->ioda.pe_array = aux + pemap_off;
3897 * Choose PE number for root bus, which shouldn't have
3898 * M64 resources consumed by its child devices. To pick
3899 * the PE number adjacent to the reserved one if possible.
3901 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3902 if (phb->ioda.reserved_pe_idx == 0) {
3903 phb->ioda.root_pe_idx = 1;
3904 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3905 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3906 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3907 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3909 phb->ioda.root_pe_idx = IODA_INVALID_PE;
3912 INIT_LIST_HEAD(&phb->ioda.pe_list);
3913 mutex_init(&phb->ioda.pe_list_mutex);
3915 /* Calculate how many 32-bit TCE segments we have */
3916 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3917 PNV_IODA1_DMA32_SEGSIZE;
3919 #if 0 /* We should really do that ... */
3920 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3923 starting_real_address,
3924 starting_pci_address,
3928 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3929 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3930 phb->ioda.m32_size, phb->ioda.m32_segsize);
3931 if (phb->ioda.m64_size)
3932 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3933 phb->ioda.m64_size, phb->ioda.m64_segsize);
3934 if (phb->ioda.io_size)
3935 pr_info(" IO: 0x%x [segment=0x%x]\n",
3936 phb->ioda.io_size, phb->ioda.io_segsize);
3939 phb->hose->ops = &pnv_pci_ops;
3940 phb->get_pe_state = pnv_ioda_get_pe_state;
3941 phb->freeze_pe = pnv_ioda_freeze_pe;
3942 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3944 /* Setup MSI support */
3945 pnv_pci_init_ioda_msis(phb);
3948 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3949 * to let the PCI core do resource assignment. It's supposed
3950 * that the PCI core will do correct I/O and MMIO alignment
3951 * for the P2P bridge bars so that each PCI bus (excluding
3952 * the child P2P bridges) can form individual PE.
3954 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3956 switch (phb->type) {
3957 case PNV_PHB_NPU_NVLINK:
3958 hose->controller_ops = pnv_npu_ioda_controller_ops;
3960 case PNV_PHB_NPU_OCAPI:
3961 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
3964 phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
3965 hose->controller_ops = pnv_pci_ioda_controller_ops;
3968 ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
3970 #ifdef CONFIG_PCI_IOV
3971 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources;
3972 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3973 ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable;
3974 ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable;
3977 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3979 /* Reset IODA tables to a clean state */
3980 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3982 pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc);
3985 * If we're running in kdump kernel, the previous kernel never
3986 * shutdown PCI devices correctly. We already got IODA table
3987 * cleaned out. So we have to issue PHB reset to stop all PCI
3988 * transactions from previous kernel. The ppc_pci_reset_phbs
3989 * kernel parameter will force this reset too.
3991 if (is_kdump_kernel() || pci_reset_phbs) {
3992 pr_info(" Issue PHB reset ...\n");
3993 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3994 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3997 /* Remove M64 resource if we can't configure it successfully */
3998 if (!phb->init_m64 || phb->init_m64(phb))
3999 hose->mem_resources[1].flags = 0;
4002 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
4004 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
4007 void __init pnv_pci_init_npu_phb(struct device_node *np)
4009 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_NVLINK);
4012 void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np)
4014 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI);
4017 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev)
4019 struct pci_controller *hose = pci_bus_to_host(dev->bus);
4020 struct pnv_phb *phb = hose->private_data;
4022 if (!machine_is(powernv))
4025 if (phb->type == PNV_PHB_NPU_OCAPI)
4026 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4028 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup);
4030 void __init pnv_pci_init_ioda_hub(struct device_node *np)
4032 struct device_node *phbn;
4033 const __be64 *prop64;
4036 pr_info("Probing IODA IO-Hub %pOF\n", np);
4038 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
4040 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
4043 hub_id = be64_to_cpup(prop64);
4044 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
4046 /* Count child PHBs */
4047 for_each_child_of_node(np, phbn) {
4048 /* Look for IODA1 PHBs */
4049 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
4050 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);