1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support PCI/PCIe on PowerNV platforms
5 * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
10 #include <linux/kernel.h>
11 #include <linux/pci.h>
12 #include <linux/crash_dump.h>
13 #include <linux/delay.h>
14 #include <linux/string.h>
15 #include <linux/init.h>
16 #include <linux/memblock.h>
17 #include <linux/irq.h>
19 #include <linux/msi.h>
20 #include <linux/iommu.h>
21 #include <linux/rculist.h>
22 #include <linux/sizes.h>
23 #include <linux/debugfs.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
27 #include <asm/sections.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/machdep.h>
31 #include <asm/msi_bitmap.h>
32 #include <asm/ppc-pci.h>
34 #include <asm/iommu.h>
37 #include <asm/firmware.h>
38 #include <asm/pnv-pci.h>
39 #include <asm/mmzone.h>
42 #include <misc/cxl-base.h>
46 #include "../../../../drivers/pci/pci.h"
48 #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */
49 #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */
50 #define PNV_IODA1_DMA32_SEGSIZE 0x10000000
52 static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU_OCAPI" };
54 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
55 static void pnv_pci_configure_bus(struct pci_bus *bus);
57 void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
69 if (pe->flags & PNV_IODA_PE_DEV)
70 strscpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix));
71 else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))
72 sprintf(pfix, "%04x:%02x ",
73 pci_domain_nr(pe->pbus), pe->pbus->number);
75 else if (pe->flags & PNV_IODA_PE_VF)
76 sprintf(pfix, "%04x:%02x:%2x.%d",
77 pci_domain_nr(pe->parent_dev->bus),
78 (pe->rid & 0xff00) >> 8,
79 PCI_SLOT(pe->rid), PCI_FUNC(pe->rid));
80 #endif /* CONFIG_PCI_IOV*/
82 printk("%spci %s: [PE# %.2x] %pV",
83 level, pfix, pe->pe_number, &vaf);
88 static bool pnv_iommu_bypass_disabled __read_mostly;
89 static bool pci_reset_phbs __read_mostly;
91 static int __init iommu_setup(char *str)
97 if (!strncmp(str, "nobypass", 8)) {
98 pnv_iommu_bypass_disabled = true;
99 pr_info("PowerNV: IOMMU bypass window disabled.\n");
102 str += strcspn(str, ",");
109 early_param("iommu", iommu_setup);
111 static int __init pci_reset_phbs_setup(char *str)
113 pci_reset_phbs = true;
117 early_param("ppc_pci_reset_phbs", pci_reset_phbs_setup);
119 static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no)
123 phb->ioda.pe_array[pe_no].phb = phb;
124 phb->ioda.pe_array[pe_no].pe_number = pe_no;
125 phb->ioda.pe_array[pe_no].dma_setup_done = false;
128 * Clear the PE frozen state as it might be put into frozen state
129 * in the last PCI remove path. It's not harmful to do so when the
130 * PE is already in unfrozen state.
132 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
133 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
134 if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED)
135 pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n",
136 __func__, rc, phb->hose->global_number, pe_no);
138 return &phb->ioda.pe_array[pe_no];
141 static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no)
143 if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) {
144 pr_warn("%s: Invalid PE %x on PHB#%x\n",
145 __func__, pe_no, phb->hose->global_number);
149 mutex_lock(&phb->ioda.pe_alloc_mutex);
150 if (test_and_set_bit(pe_no, phb->ioda.pe_alloc))
151 pr_debug("%s: PE %x was reserved on PHB#%x\n",
152 __func__, pe_no, phb->hose->global_number);
153 mutex_unlock(&phb->ioda.pe_alloc_mutex);
155 pnv_ioda_init_pe(phb, pe_no);
158 struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb, int count)
160 struct pnv_ioda_pe *ret = NULL;
163 mutex_lock(&phb->ioda.pe_alloc_mutex);
165 /* scan backwards for a run of @count cleared bits */
166 for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) {
167 if (test_bit(pe, phb->ioda.pe_alloc)) {
179 for (i = pe; i < pe + count; i++) {
180 set_bit(i, phb->ioda.pe_alloc);
181 pnv_ioda_init_pe(phb, i);
183 ret = &phb->ioda.pe_array[pe];
186 mutex_unlock(&phb->ioda.pe_alloc_mutex);
190 void pnv_ioda_free_pe(struct pnv_ioda_pe *pe)
192 struct pnv_phb *phb = pe->phb;
193 unsigned int pe_num = pe->pe_number;
196 memset(pe, 0, sizeof(struct pnv_ioda_pe));
198 mutex_lock(&phb->ioda.pe_alloc_mutex);
199 clear_bit(pe_num, phb->ioda.pe_alloc);
200 mutex_unlock(&phb->ioda.pe_alloc_mutex);
203 /* The default M64 BAR is shared by all PEs */
204 static int pnv_ioda2_init_m64(struct pnv_phb *phb)
210 /* Configure the default M64 BAR */
211 rc = opal_pci_set_phb_mem_window(phb->opal_id,
212 OPAL_M64_WINDOW_TYPE,
213 phb->ioda.m64_bar_idx,
217 if (rc != OPAL_SUCCESS) {
218 desc = "configuring";
222 /* Enable the default M64 BAR */
223 rc = opal_pci_phb_mmio_enable(phb->opal_id,
224 OPAL_M64_WINDOW_TYPE,
225 phb->ioda.m64_bar_idx,
226 OPAL_ENABLE_M64_SPLIT);
227 if (rc != OPAL_SUCCESS) {
233 * Exclude the segments for reserved and root bus PE, which
234 * are first or last two PEs.
236 r = &phb->hose->mem_resources[1];
237 if (phb->ioda.reserved_pe_idx == 0)
238 r->start += (2 * phb->ioda.m64_segsize);
239 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
240 r->end -= (2 * phb->ioda.m64_segsize);
242 pr_warn(" Cannot strip M64 segment for reserved PE#%x\n",
243 phb->ioda.reserved_pe_idx);
248 pr_warn(" Failure %lld %s M64 BAR#%d\n",
249 rc, desc, phb->ioda.m64_bar_idx);
250 opal_pci_phb_mmio_enable(phb->opal_id,
251 OPAL_M64_WINDOW_TYPE,
252 phb->ioda.m64_bar_idx,
257 static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev,
258 unsigned long *pe_bitmap)
260 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
262 resource_size_t base, sgsz, start, end;
265 base = phb->ioda.m64_base;
266 sgsz = phb->ioda.m64_segsize;
267 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
268 r = &pdev->resource[i];
269 if (!r->parent || !pnv_pci_is_m64(phb, r))
272 start = ALIGN_DOWN(r->start - base, sgsz);
273 end = ALIGN(r->end - base, sgsz);
274 for (segno = start / sgsz; segno < end / sgsz; segno++) {
276 set_bit(segno, pe_bitmap);
278 pnv_ioda_reserve_pe(phb, segno);
283 static int pnv_ioda1_init_m64(struct pnv_phb *phb)
289 * There are 16 M64 BARs, each of which has 8 segments. So
290 * there are as many M64 segments as the maximum number of
293 for (index = 0; index < PNV_IODA1_M64_NUM; index++) {
294 unsigned long base, segsz = phb->ioda.m64_segsize;
297 base = phb->ioda.m64_base +
298 index * PNV_IODA1_M64_SEGS * segsz;
299 rc = opal_pci_set_phb_mem_window(phb->opal_id,
300 OPAL_M64_WINDOW_TYPE, index, base, 0,
301 PNV_IODA1_M64_SEGS * segsz);
302 if (rc != OPAL_SUCCESS) {
303 pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n",
304 rc, phb->hose->global_number, index);
308 rc = opal_pci_phb_mmio_enable(phb->opal_id,
309 OPAL_M64_WINDOW_TYPE, index,
310 OPAL_ENABLE_M64_SPLIT);
311 if (rc != OPAL_SUCCESS) {
312 pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n",
313 rc, phb->hose->global_number, index);
318 for (index = 0; index < phb->ioda.total_pe_num; index++) {
322 * P7IOC supports M64DT, which helps mapping M64 segment
323 * to one particular PE#. However, PHB3 has fixed mapping
324 * between M64 segment and PE#. In order to have same logic
325 * for P7IOC and PHB3, we enforce fixed mapping between M64
326 * segment and PE# on P7IOC.
328 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
329 index, OPAL_M64_WINDOW_TYPE,
330 index / PNV_IODA1_M64_SEGS,
331 index % PNV_IODA1_M64_SEGS);
332 if (rc != OPAL_SUCCESS) {
333 pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n",
334 __func__, rc, phb->hose->global_number,
341 * Exclude the segments for reserved and root bus PE, which
342 * are first or last two PEs.
344 r = &phb->hose->mem_resources[1];
345 if (phb->ioda.reserved_pe_idx == 0)
346 r->start += (2 * phb->ioda.m64_segsize);
347 else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1))
348 r->end -= (2 * phb->ioda.m64_segsize);
350 WARN(1, "Wrong reserved PE#%x on PHB#%x\n",
351 phb->ioda.reserved_pe_idx, phb->hose->global_number);
356 for ( ; index >= 0; index--)
357 opal_pci_phb_mmio_enable(phb->opal_id,
358 OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64);
363 static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus,
364 unsigned long *pe_bitmap,
367 struct pci_dev *pdev;
369 list_for_each_entry(pdev, &bus->devices, bus_list) {
370 pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap);
372 if (all && pdev->subordinate)
373 pnv_ioda_reserve_m64_pe(pdev->subordinate,
378 static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all)
380 struct pnv_phb *phb = pci_bus_to_pnvhb(bus);
381 struct pnv_ioda_pe *master_pe, *pe;
382 unsigned long size, *pe_alloc;
385 /* Root bus shouldn't use M64 */
386 if (pci_is_root_bus(bus))
389 /* Allocate bitmap */
390 size = ALIGN(phb->ioda.total_pe_num / 8, sizeof(unsigned long));
391 pe_alloc = kzalloc(size, GFP_KERNEL);
393 pr_warn("%s: Out of memory !\n",
398 /* Figure out reserved PE numbers by the PE */
399 pnv_ioda_reserve_m64_pe(bus, pe_alloc, all);
402 * the current bus might not own M64 window and that's all
403 * contributed by its child buses. For the case, we needn't
404 * pick M64 dependent PE#.
406 if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) {
412 * Figure out the master PE and put all slave PEs to master
413 * PE's list to form compound PE.
417 while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) <
418 phb->ioda.total_pe_num) {
419 pe = &phb->ioda.pe_array[i];
421 phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number;
423 pe->flags |= PNV_IODA_PE_MASTER;
424 INIT_LIST_HEAD(&pe->slaves);
427 pe->flags |= PNV_IODA_PE_SLAVE;
428 pe->master = master_pe;
429 list_add_tail(&pe->list, &master_pe->slaves);
437 static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb)
439 struct pci_controller *hose = phb->hose;
440 struct device_node *dn = hose->dn;
441 struct resource *res;
446 if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) {
447 pr_info(" Not support M64 window\n");
451 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
452 pr_info(" Firmware too old to support M64 window\n");
456 r = of_get_property(dn, "ibm,opal-m64-window", NULL);
458 pr_info(" No <ibm,opal-m64-window> on %pOF\n",
464 * Find the available M64 BAR range and pickup the last one for
465 * covering the whole 64-bits space. We support only one range.
467 if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges",
469 /* In absence of the property, assume 0..15 */
473 /* We only support 64 bits in our allocator */
474 if (m64_range[1] > 63) {
475 pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n",
476 __func__, m64_range[1], phb->hose->global_number);
479 /* Empty range, no m64 */
480 if (m64_range[1] <= m64_range[0]) {
481 pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n",
482 __func__, phb->hose->global_number);
486 /* Configure M64 informations */
487 res = &hose->mem_resources[1];
488 res->name = dn->full_name;
489 res->start = of_translate_address(dn, r + 2);
490 res->end = res->start + of_read_number(r + 4, 2) - 1;
491 res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH);
492 pci_addr = of_read_number(r, 2);
493 hose->mem_offset[1] = res->start - pci_addr;
495 phb->ioda.m64_size = resource_size(res);
496 phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num;
497 phb->ioda.m64_base = pci_addr;
499 /* This lines up nicely with the display from processing OF ranges */
500 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n",
501 res->start, res->end, pci_addr, m64_range[0],
502 m64_range[0] + m64_range[1] - 1);
504 /* Mark all M64 used up by default */
505 phb->ioda.m64_bar_alloc = (unsigned long)-1;
507 /* Use last M64 BAR to cover M64 window */
509 phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1];
511 pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx);
513 /* Mark remaining ones free */
514 for (i = m64_range[0]; i < m64_range[1]; i++)
515 clear_bit(i, &phb->ioda.m64_bar_alloc);
518 * Setup init functions for M64 based on IODA version, IODA3 uses
521 if (phb->type == PNV_PHB_IODA1)
522 phb->init_m64 = pnv_ioda1_init_m64;
524 phb->init_m64 = pnv_ioda2_init_m64;
527 static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no)
529 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no];
530 struct pnv_ioda_pe *slave;
533 /* Fetch master PE */
534 if (pe->flags & PNV_IODA_PE_SLAVE) {
536 if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)))
539 pe_no = pe->pe_number;
542 /* Freeze master PE */
543 rc = opal_pci_eeh_freeze_set(phb->opal_id,
545 OPAL_EEH_ACTION_SET_FREEZE_ALL);
546 if (rc != OPAL_SUCCESS) {
547 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
548 __func__, rc, phb->hose->global_number, pe_no);
552 /* Freeze slave PEs */
553 if (!(pe->flags & PNV_IODA_PE_MASTER))
556 list_for_each_entry(slave, &pe->slaves, list) {
557 rc = opal_pci_eeh_freeze_set(phb->opal_id,
559 OPAL_EEH_ACTION_SET_FREEZE_ALL);
560 if (rc != OPAL_SUCCESS)
561 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
562 __func__, rc, phb->hose->global_number,
567 static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt)
569 struct pnv_ioda_pe *pe, *slave;
573 pe = &phb->ioda.pe_array[pe_no];
574 if (pe->flags & PNV_IODA_PE_SLAVE) {
576 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
577 pe_no = pe->pe_number;
580 /* Clear frozen state for master PE */
581 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt);
582 if (rc != OPAL_SUCCESS) {
583 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
584 __func__, rc, opt, phb->hose->global_number, pe_no);
588 if (!(pe->flags & PNV_IODA_PE_MASTER))
591 /* Clear frozen state for slave PEs */
592 list_for_each_entry(slave, &pe->slaves, list) {
593 rc = opal_pci_eeh_freeze_clear(phb->opal_id,
596 if (rc != OPAL_SUCCESS) {
597 pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n",
598 __func__, rc, opt, phb->hose->global_number,
607 static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
609 struct pnv_ioda_pe *slave, *pe;
610 u8 fstate = 0, state;
614 /* Sanity check on PE number */
615 if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num)
616 return OPAL_EEH_STOPPED_PERM_UNAVAIL;
619 * Fetch the master PE and the PE instance might be
620 * not initialized yet.
622 pe = &phb->ioda.pe_array[pe_no];
623 if (pe->flags & PNV_IODA_PE_SLAVE) {
625 WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER));
626 pe_no = pe->pe_number;
629 /* Check the master PE */
630 rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
631 &state, &pcierr, NULL);
632 if (rc != OPAL_SUCCESS) {
633 pr_warn("%s: Failure %lld getting "
634 "PHB#%x-PE#%x state\n",
636 phb->hose->global_number, pe_no);
637 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
640 /* Check the slave PE */
641 if (!(pe->flags & PNV_IODA_PE_MASTER))
644 list_for_each_entry(slave, &pe->slaves, list) {
645 rc = opal_pci_eeh_freeze_status(phb->opal_id,
650 if (rc != OPAL_SUCCESS) {
651 pr_warn("%s: Failure %lld getting "
652 "PHB#%x-PE#%x state\n",
654 phb->hose->global_number, slave->pe_number);
655 return OPAL_EEH_STOPPED_TEMP_UNAVAIL;
659 * Override the result based on the ascending
669 struct pnv_ioda_pe *pnv_pci_bdfn_to_pe(struct pnv_phb *phb, u16 bdfn)
671 int pe_number = phb->ioda.pe_rmap[bdfn];
673 if (pe_number == IODA_INVALID_PE)
676 return &phb->ioda.pe_array[pe_number];
679 struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
681 struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus);
682 struct pci_dn *pdn = pci_get_pdn(dev);
686 if (pdn->pe_number == IODA_INVALID_PE)
688 return &phb->ioda.pe_array[pdn->pe_number];
691 static int pnv_ioda_set_one_peltv(struct pnv_phb *phb,
692 struct pnv_ioda_pe *parent,
693 struct pnv_ioda_pe *child,
696 const char *desc = is_add ? "adding" : "removing";
697 uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN :
698 OPAL_REMOVE_PE_FROM_DOMAIN;
699 struct pnv_ioda_pe *slave;
702 /* Parent PE affects child PE */
703 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
704 child->pe_number, op);
705 if (rc != OPAL_SUCCESS) {
706 pe_warn(child, "OPAL error %ld %s to parent PELTV\n",
711 if (!(child->flags & PNV_IODA_PE_MASTER))
714 /* Compound case: parent PE affects slave PEs */
715 list_for_each_entry(slave, &child->slaves, list) {
716 rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number,
717 slave->pe_number, op);
718 if (rc != OPAL_SUCCESS) {
719 pe_warn(slave, "OPAL error %ld %s to parent PELTV\n",
728 static int pnv_ioda_set_peltv(struct pnv_phb *phb,
729 struct pnv_ioda_pe *pe,
732 struct pnv_ioda_pe *slave;
733 struct pci_dev *pdev = NULL;
737 * Clear PE frozen state. If it's master PE, we need
738 * clear slave PE frozen state as well.
741 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
742 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
743 if (pe->flags & PNV_IODA_PE_MASTER) {
744 list_for_each_entry(slave, &pe->slaves, list)
745 opal_pci_eeh_freeze_clear(phb->opal_id,
747 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
752 * Associate PE in PELT. We need add the PE into the
753 * corresponding PELT-V as well. Otherwise, the error
754 * originated from the PE might contribute to other
757 ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add);
761 /* For compound PEs, any one affects all of them */
762 if (pe->flags & PNV_IODA_PE_MASTER) {
763 list_for_each_entry(slave, &pe->slaves, list) {
764 ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add);
770 if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS))
771 pdev = pe->pbus->self;
772 else if (pe->flags & PNV_IODA_PE_DEV)
773 pdev = pe->pdev->bus->self;
774 #ifdef CONFIG_PCI_IOV
775 else if (pe->flags & PNV_IODA_PE_VF)
776 pdev = pe->parent_dev;
777 #endif /* CONFIG_PCI_IOV */
779 struct pci_dn *pdn = pci_get_pdn(pdev);
780 struct pnv_ioda_pe *parent;
782 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
783 parent = &phb->ioda.pe_array[pdn->pe_number];
784 ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add);
789 pdev = pdev->bus->self;
795 static void pnv_ioda_unset_peltv(struct pnv_phb *phb,
796 struct pnv_ioda_pe *pe,
797 struct pci_dev *parent)
802 struct pci_dn *pdn = pci_get_pdn(parent);
804 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
805 rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
807 OPAL_REMOVE_PE_FROM_DOMAIN);
808 /* XXX What to do in case of error ? */
810 parent = parent->bus->self;
813 opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
814 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
816 /* Disassociate PE in PELT */
817 rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
818 pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN);
820 pe_warn(pe, "OPAL error %lld remove self from PELTV\n", rc);
823 int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
825 struct pci_dev *parent;
826 uint8_t bcomp, dcomp, fcomp;
830 /* Currently, we just deconfigure VF PE. Bus PE will always there.*/
834 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
835 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
836 parent = pe->pbus->self;
837 if (pe->flags & PNV_IODA_PE_BUS_ALL)
838 count = resource_size(&pe->pbus->busn_res);
843 case 1: bcomp = OpalPciBusAll; break;
844 case 2: bcomp = OpalPciBus7Bits; break;
845 case 4: bcomp = OpalPciBus6Bits; break;
846 case 8: bcomp = OpalPciBus5Bits; break;
847 case 16: bcomp = OpalPciBus4Bits; break;
848 case 32: bcomp = OpalPciBus3Bits; break;
850 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
852 /* Do an exact match only */
853 bcomp = OpalPciBusAll;
855 rid_end = pe->rid + (count << 8);
857 #ifdef CONFIG_PCI_IOV
858 if (pe->flags & PNV_IODA_PE_VF)
859 parent = pe->parent_dev;
862 parent = pe->pdev->bus->self;
863 bcomp = OpalPciBusAll;
864 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
865 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
866 rid_end = pe->rid + 1;
869 /* Clear the reverse map */
870 for (rid = pe->rid; rid < rid_end; rid++)
871 phb->ioda.pe_rmap[rid] = IODA_INVALID_PE;
874 * Release from all parents PELT-V. NPUs don't have a PELTV
877 if (phb->type != PNV_PHB_NPU_OCAPI)
878 pnv_ioda_unset_peltv(phb, pe, parent);
880 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
881 bcomp, dcomp, fcomp, OPAL_UNMAP_PE);
883 pe_err(pe, "OPAL error %lld trying to setup PELT table\n", rc);
887 #ifdef CONFIG_PCI_IOV
888 pe->parent_dev = NULL;
894 int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
896 uint8_t bcomp, dcomp, fcomp;
897 long rc, rid_end, rid;
899 /* Bus validation ? */
903 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
904 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
905 if (pe->flags & PNV_IODA_PE_BUS_ALL)
906 count = resource_size(&pe->pbus->busn_res);
911 case 1: bcomp = OpalPciBusAll; break;
912 case 2: bcomp = OpalPciBus7Bits; break;
913 case 4: bcomp = OpalPciBus6Bits; break;
914 case 8: bcomp = OpalPciBus5Bits; break;
915 case 16: bcomp = OpalPciBus4Bits; break;
916 case 32: bcomp = OpalPciBus3Bits; break;
918 dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n",
920 /* Do an exact match only */
921 bcomp = OpalPciBusAll;
923 rid_end = pe->rid + (count << 8);
925 bcomp = OpalPciBusAll;
926 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
927 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
928 rid_end = pe->rid + 1;
932 * Associate PE in PELT. We need add the PE into the
933 * corresponding PELT-V as well. Otherwise, the error
934 * originated from the PE might contribute to other
937 rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
938 bcomp, dcomp, fcomp, OPAL_MAP_PE);
940 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
945 * Configure PELTV. NPUs don't have a PELTV table so skip
946 * configuration on them.
948 if (phb->type != PNV_PHB_NPU_OCAPI)
949 pnv_ioda_set_peltv(phb, pe, true);
951 /* Setup reverse map */
952 for (rid = pe->rid; rid < rid_end; rid++)
953 phb->ioda.pe_rmap[rid] = pe->pe_number;
955 /* Setup one MVTs on IODA1 */
956 if (phb->type != PNV_PHB_IODA1) {
961 pe->mve_number = pe->pe_number;
962 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number);
963 if (rc != OPAL_SUCCESS) {
964 pe_err(pe, "OPAL error %ld setting up MVE %x\n",
968 rc = opal_pci_set_mve_enable(phb->opal_id,
969 pe->mve_number, OPAL_ENABLE_MVE);
971 pe_err(pe, "OPAL error %ld enabling MVE %x\n",
981 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
983 struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus);
984 struct pci_dn *pdn = pci_get_pdn(dev);
985 struct pnv_ioda_pe *pe;
988 pr_err("%s: Device tree node not associated properly\n",
992 if (pdn->pe_number != IODA_INVALID_PE)
995 pe = pnv_ioda_alloc_pe(phb, 1);
997 pr_warn("%s: Not enough PE# available, disabling device\n",
1002 /* NOTE: We don't get a reference for the pointer in the PE
1003 * data structure, both the device and PE structures should be
1004 * destroyed at the same time.
1006 * At some point we want to remove the PDN completely anyways
1008 pdn->pe_number = pe->pe_number;
1009 pe->flags = PNV_IODA_PE_DEV;
1012 pe->mve_number = -1;
1013 pe->rid = dev->bus->number << 8 | pdn->devfn;
1016 pe_info(pe, "Associated device to PE\n");
1018 if (pnv_ioda_configure_pe(phb, pe)) {
1019 /* XXX What do we do here ? */
1020 pnv_ioda_free_pe(pe);
1021 pdn->pe_number = IODA_INVALID_PE;
1026 /* Put PE to the list */
1027 mutex_lock(&phb->ioda.pe_list_mutex);
1028 list_add_tail(&pe->list, &phb->ioda.pe_list);
1029 mutex_unlock(&phb->ioda.pe_list_mutex);
1034 * There're 2 types of PCI bus sensitive PEs: One that is compromised of
1035 * single PCI bus. Another one that contains the primary PCI bus and its
1036 * subordinate PCI devices and buses. The second type of PE is normally
1037 * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
1039 static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all)
1041 struct pnv_phb *phb = pci_bus_to_pnvhb(bus);
1042 struct pnv_ioda_pe *pe = NULL;
1043 unsigned int pe_num;
1046 * In partial hotplug case, the PE instance might be still alive.
1047 * We should reuse it instead of allocating a new one.
1049 pe_num = phb->ioda.pe_rmap[bus->number << 8];
1050 if (WARN_ON(pe_num != IODA_INVALID_PE)) {
1051 pe = &phb->ioda.pe_array[pe_num];
1055 /* PE number for root bus should have been reserved */
1056 if (pci_is_root_bus(bus))
1057 pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx];
1059 /* Check if PE is determined by M64 */
1061 pe = pnv_ioda_pick_m64_pe(bus, all);
1063 /* The PE number isn't pinned by M64 */
1065 pe = pnv_ioda_alloc_pe(phb, 1);
1068 pr_warn("%s: Not enough PE# available for PCI bus %04x:%02x\n",
1069 __func__, pci_domain_nr(bus), bus->number);
1073 pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
1076 pe->mve_number = -1;
1077 pe->rid = bus->busn_res.start << 8;
1080 pe_info(pe, "Secondary bus %pad..%pad associated with PE#%x\n",
1081 &bus->busn_res.start, &bus->busn_res.end,
1084 pe_info(pe, "Secondary bus %pad associated with PE#%x\n",
1085 &bus->busn_res.start, pe->pe_number);
1087 if (pnv_ioda_configure_pe(phb, pe)) {
1088 /* XXX What do we do here ? */
1089 pnv_ioda_free_pe(pe);
1094 /* Put PE to the list */
1095 list_add_tail(&pe->list, &phb->ioda.pe_list);
1100 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
1101 struct pnv_ioda_pe *pe);
1103 static void pnv_pci_ioda_dma_dev_setup(struct pci_dev *pdev)
1105 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
1106 struct pci_dn *pdn = pci_get_pdn(pdev);
1107 struct pnv_ioda_pe *pe;
1109 /* Check if the BDFN for this device is associated with a PE yet */
1110 pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8));
1112 /* VF PEs should be pre-configured in pnv_pci_sriov_enable() */
1113 if (WARN_ON(pdev->is_virtfn))
1116 pnv_pci_configure_bus(pdev->bus);
1117 pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8));
1118 pci_info(pdev, "Configured PE#%x\n", pe ? pe->pe_number : 0xfffff);
1122 * If we can't setup the IODA PE something has gone horribly
1123 * wrong and we can't enable DMA for the device.
1128 pci_info(pdev, "Added to existing PE#%x\n", pe->pe_number);
1132 * We assume that bridges *probably* don't need to do any DMA so we can
1133 * skip allocating a TCE table, etc unless we get a non-bridge device.
1135 if (!pe->dma_setup_done && !pci_is_bridge(pdev)) {
1136 switch (phb->type) {
1138 pnv_pci_ioda1_setup_dma_pe(phb, pe);
1141 pnv_pci_ioda2_setup_dma_pe(phb, pe);
1144 pr_warn("%s: No DMA for PHB#%x (type %d)\n",
1145 __func__, phb->hose->global_number, phb->type);
1150 pdn->pe_number = pe->pe_number;
1153 WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops);
1154 pdev->dev.archdata.dma_offset = pe->tce_bypass_base;
1155 set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]);
1157 /* PEs with a DMA weight of zero won't have a group */
1158 if (pe->table_group.group)
1159 iommu_add_device(&pe->table_group, &pdev->dev);
1163 * Reconfigure TVE#0 to be usable as 64-bit DMA space.
1165 * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses.
1166 * Devices can only access more than that if bit 59 of the PCI address is set
1167 * by hardware, which indicates TVE#1 should be used instead of TVE#0.
1168 * Many PCI devices are not capable of addressing that many bits, and as a
1169 * result are limited to the 4GB of virtual memory made available to 32-bit
1172 * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit
1173 * devices by configuring the virtual memory past the first 4GB inaccessible
1174 * by 64-bit DMAs. This should only be used by devices that want more than
1175 * 4GB, and only on PEs that have no 32-bit devices.
1177 * Currently this will only work on PHB3 (POWER8).
1179 static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe)
1181 u64 window_size, table_size, tce_count, addr;
1182 struct page *table_pages;
1183 u64 tce_order = 28; /* 256MB TCEs */
1188 * Window size needs to be a power of two, but needs to account for
1189 * shifting memory by the 4GB offset required to skip 32bit space.
1191 window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32));
1192 tce_count = window_size >> tce_order;
1193 table_size = tce_count << 3;
1195 if (table_size < PAGE_SIZE)
1196 table_size = PAGE_SIZE;
1198 table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL,
1199 get_order(table_size));
1203 tces = page_address(table_pages);
1207 memset(tces, 0, table_size);
1209 for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) {
1210 tces[(addr + (1ULL << 32)) >> tce_order] =
1211 cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE);
1214 rc = opal_pci_map_pe_dma_window(pe->phb->opal_id,
1216 /* reconfigure window 0 */
1217 (pe->pe_number << 1) + 0,
1222 if (rc == OPAL_SUCCESS) {
1223 pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n");
1227 pe_err(pe, "Error configuring 64-bit DMA bypass\n");
1231 static bool pnv_pci_ioda_iommu_bypass_supported(struct pci_dev *pdev,
1234 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
1235 struct pci_dn *pdn = pci_get_pdn(pdev);
1236 struct pnv_ioda_pe *pe;
1238 if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE))
1241 pe = &phb->ioda.pe_array[pdn->pe_number];
1242 if (pe->tce_bypass_enabled) {
1243 u64 top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1;
1244 if (dma_mask >= top)
1249 * If the device can't set the TCE bypass bit but still wants
1250 * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to
1251 * bypass the 32-bit region and be usable for 64-bit DMAs.
1252 * The device needs to be able to address all of this space.
1254 if (dma_mask >> 32 &&
1255 dma_mask > (memory_hotplug_max() + (1ULL << 32)) &&
1256 /* pe->pdev should be set if it's a single device, pe->pbus if not */
1257 (pe->device_count == 1 || !pe->pbus) &&
1258 phb->model == PNV_PHB_MODEL_PHB3) {
1259 /* Configure the bypass mode */
1260 s64 rc = pnv_pci_ioda_dma_64bit_bypass(pe);
1263 /* 4GB offset bypasses 32-bit space */
1264 pdev->dev.archdata.dma_offset = (1ULL << 32);
1271 static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb)
1273 return phb->regs + 0x210;
1276 static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl,
1277 unsigned long index, unsigned long npages)
1279 struct iommu_table_group_link *tgl = list_first_entry_or_null(
1280 &tbl->it_group_list, struct iommu_table_group_link,
1282 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1283 struct pnv_ioda_pe, table_group);
1284 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb);
1285 unsigned long start, end, inc;
1287 start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset);
1288 end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset +
1291 /* p7ioc-style invalidation, 2 TCEs per write */
1292 start |= (1ull << 63);
1293 end |= (1ull << 63);
1295 end |= inc - 1; /* round up end to be different than start */
1297 mb(); /* Ensure above stores are visible */
1298 while (start <= end) {
1299 __raw_writeq_be(start, invalidate);
1304 * The iommu layer will do another mb() for us on build()
1305 * and we don't care on free()
1309 static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index,
1310 long npages, unsigned long uaddr,
1311 enum dma_data_direction direction,
1312 unsigned long attrs)
1314 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1318 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages);
1323 #ifdef CONFIG_IOMMU_API
1324 /* Common for IODA1 and IODA2 */
1325 static int pnv_ioda_tce_xchg_no_kill(struct iommu_table *tbl, long index,
1326 unsigned long *hpa, enum dma_data_direction *direction)
1328 return pnv_tce_xchg(tbl, index, hpa, direction);
1332 static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,
1335 pnv_tce_free(tbl, index, npages);
1337 pnv_pci_p7ioc_tce_invalidate(tbl, index, npages);
1340 static struct iommu_table_ops pnv_ioda1_iommu_ops = {
1341 .set = pnv_ioda1_tce_build,
1342 #ifdef CONFIG_IOMMU_API
1343 .xchg_no_kill = pnv_ioda_tce_xchg_no_kill,
1344 .tce_kill = pnv_pci_p7ioc_tce_invalidate,
1345 .useraddrptr = pnv_tce_useraddrptr,
1347 .clear = pnv_ioda1_tce_free,
1351 #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0)
1352 #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1)
1353 #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2)
1355 static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1357 /* 01xb - invalidate TCEs that match the specified PE# */
1358 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb);
1359 unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF);
1361 mb(); /* Ensure above stores are visible */
1362 __raw_writeq_be(val, invalidate);
1365 static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe,
1366 unsigned shift, unsigned long index,
1367 unsigned long npages)
1369 __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb);
1370 unsigned long start, end, inc;
1372 /* We'll invalidate DMA address in PE scope */
1373 start = PHB3_TCE_KILL_INVAL_ONE;
1374 start |= (pe->pe_number & 0xFF);
1377 /* Figure out the start, end and step */
1378 start |= (index << shift);
1379 end |= ((index + npages - 1) << shift);
1380 inc = (0x1ull << shift);
1383 while (start <= end) {
1384 __raw_writeq_be(start, invalidate);
1389 static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe)
1391 struct pnv_phb *phb = pe->phb;
1393 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1394 pnv_pci_phb3_tce_invalidate_pe(pe);
1396 opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE,
1397 pe->pe_number, 0, 0, 0);
1400 static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl,
1401 unsigned long index, unsigned long npages)
1403 struct iommu_table_group_link *tgl;
1405 list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) {
1406 struct pnv_ioda_pe *pe = container_of(tgl->table_group,
1407 struct pnv_ioda_pe, table_group);
1408 struct pnv_phb *phb = pe->phb;
1409 unsigned int shift = tbl->it_page_shift;
1411 if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs)
1412 pnv_pci_phb3_tce_invalidate(pe, shift,
1415 opal_pci_tce_kill(phb->opal_id,
1416 OPAL_PCI_TCE_KILL_PAGES,
1417 pe->pe_number, 1u << shift,
1418 index << shift, npages);
1422 static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index,
1423 long npages, unsigned long uaddr,
1424 enum dma_data_direction direction,
1425 unsigned long attrs)
1427 int ret = pnv_tce_build(tbl, index, npages, uaddr, direction,
1431 pnv_pci_ioda2_tce_invalidate(tbl, index, npages);
1436 static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,
1439 pnv_tce_free(tbl, index, npages);
1441 pnv_pci_ioda2_tce_invalidate(tbl, index, npages);
1444 static struct iommu_table_ops pnv_ioda2_iommu_ops = {
1445 .set = pnv_ioda2_tce_build,
1446 #ifdef CONFIG_IOMMU_API
1447 .xchg_no_kill = pnv_ioda_tce_xchg_no_kill,
1448 .tce_kill = pnv_pci_ioda2_tce_invalidate,
1449 .useraddrptr = pnv_tce_useraddrptr,
1451 .clear = pnv_ioda2_tce_free,
1453 .free = pnv_pci_ioda2_table_free_pages,
1456 static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data)
1458 unsigned int *weight = (unsigned int *)data;
1460 /* This is quite simplistic. The "base" weight of a device
1461 * is 10. 0 means no DMA is to be accounted for it.
1463 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
1466 if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
1467 dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
1468 dev->class == PCI_CLASS_SERIAL_USB_EHCI)
1470 else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
1478 static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe)
1480 unsigned int weight = 0;
1482 /* SRIOV VF has same DMA32 weight as its PF */
1483 #ifdef CONFIG_PCI_IOV
1484 if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) {
1485 pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight);
1490 if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) {
1491 pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight);
1492 } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) {
1493 struct pci_dev *pdev;
1495 list_for_each_entry(pdev, &pe->pbus->devices, bus_list)
1496 pnv_pci_ioda_dev_dma_weight(pdev, &weight);
1497 } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) {
1498 pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight);
1504 static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb,
1505 struct pnv_ioda_pe *pe)
1508 struct page *tce_mem = NULL;
1509 struct iommu_table *tbl;
1510 unsigned int weight, total_weight = 0;
1511 unsigned int tce32_segsz, base, segs, avail, i;
1515 /* XXX FIXME: Handle 64-bit only DMA devices */
1516 /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
1517 /* XXX FIXME: Allocate multi-level tables on PHB3 */
1518 weight = pnv_pci_ioda_pe_dma_weight(pe);
1522 pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight,
1524 segs = (weight * phb->ioda.dma32_count) / total_weight;
1529 * Allocate contiguous DMA32 segments. We begin with the expected
1530 * number of segments. With one more attempt, the number of DMA32
1531 * segments to be allocated is decreased by one until one segment
1532 * is allocated successfully.
1535 for (base = 0; base <= phb->ioda.dma32_count - segs; base++) {
1536 for (avail = 0, i = base; i < base + segs; i++) {
1537 if (phb->ioda.dma32_segmap[i] ==
1548 pe_warn(pe, "No available DMA32 segments\n");
1553 tbl = pnv_pci_table_alloc(phb->hose->node);
1557 #ifdef CONFIG_IOMMU_API
1558 pe->table_group.ops = &spapr_tce_table_group_ops;
1559 pe->table_group.pgsizes = SZ_4K;
1561 iommu_register_group(&pe->table_group, phb->hose->global_number,
1563 pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
1565 /* Grab a 32-bit TCE table */
1566 pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n",
1567 weight, total_weight, base, segs);
1568 pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
1569 base * PNV_IODA1_DMA32_SEGSIZE,
1570 (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1);
1572 /* XXX Currently, we allocate one big contiguous table for the
1573 * TCEs. We only really need one chunk per 256M of TCE space
1574 * (ie per segment) but that's an optimization for later, it
1575 * requires some added smarts with our get/put_tce implementation
1577 * Each TCE page is 4KB in size and each TCE entry occupies 8
1580 tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3);
1581 tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
1582 get_order(tce32_segsz * segs));
1584 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
1587 addr = page_address(tce_mem);
1588 memset(addr, 0, tce32_segsz * segs);
1591 for (i = 0; i < segs; i++) {
1592 rc = opal_pci_map_pe_dma_window(phb->opal_id,
1595 __pa(addr) + tce32_segsz * i,
1596 tce32_segsz, IOMMU_PAGE_SIZE_4K);
1598 pe_err(pe, " Failed to configure 32-bit TCE table, err %lld\n",
1604 /* Setup DMA32 segment mapping */
1605 for (i = base; i < base + segs; i++)
1606 phb->ioda.dma32_segmap[i] = pe->pe_number;
1608 /* Setup linux iommu table */
1609 pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs,
1610 base * PNV_IODA1_DMA32_SEGSIZE,
1611 IOMMU_PAGE_SHIFT_4K);
1613 tbl->it_ops = &pnv_ioda1_iommu_ops;
1614 pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
1615 pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
1616 tbl->it_index = (phb->hose->global_number << 16) | pe->pe_number;
1617 if (!iommu_init_table(tbl, phb->hose->node, 0, 0))
1618 panic("Failed to initialize iommu table");
1620 pe->dma_setup_done = true;
1623 /* XXX Failure: Try to fallback to 64-bit only ? */
1625 __free_pages(tce_mem, get_order(tce32_segsz * segs));
1627 pnv_pci_unlink_table_and_group(tbl, &pe->table_group);
1628 iommu_tce_table_put(tbl);
1632 static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
1633 int num, struct iommu_table *tbl)
1635 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1637 struct pnv_phb *phb = pe->phb;
1639 const unsigned long size = tbl->it_indirect_levels ?
1640 tbl->it_level_size : tbl->it_size;
1641 const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
1642 const __u64 win_size = tbl->it_size << tbl->it_page_shift;
1644 pe_info(pe, "Setting up window#%d %llx..%llx pg=%lx\n",
1645 num, start_addr, start_addr + win_size - 1,
1646 IOMMU_PAGE_SIZE(tbl));
1649 * Map TCE table through TVT. The TVE index is the PE number
1650 * shifted by 1 bit for 32-bits DMA space.
1652 rc = opal_pci_map_pe_dma_window(phb->opal_id,
1654 (pe->pe_number << 1) + num,
1655 tbl->it_indirect_levels + 1,
1658 IOMMU_PAGE_SIZE(tbl));
1660 pe_err(pe, "Failed to configure TCE table, err %lld\n", rc);
1664 pnv_pci_link_table_and_group(phb->hose->node, num,
1665 tbl, &pe->table_group);
1666 pnv_pci_ioda2_tce_invalidate_pe(pe);
1671 static void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable)
1673 uint16_t window_id = (pe->pe_number << 1 ) + 1;
1676 pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis");
1678 phys_addr_t top = memblock_end_of_DRAM();
1680 top = roundup_pow_of_two(top);
1681 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1684 pe->tce_bypass_base,
1687 rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id,
1690 pe->tce_bypass_base,
1694 pe_err(pe, "OPAL error %lld configuring bypass window\n", rc);
1696 pe->tce_bypass_enabled = enable;
1699 static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
1700 int num, __u32 page_shift, __u64 window_size, __u32 levels,
1701 bool alloc_userspace_copy, struct iommu_table **ptbl)
1703 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1705 int nid = pe->phb->hose->node;
1706 __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start;
1708 struct iommu_table *tbl;
1710 tbl = pnv_pci_table_alloc(nid);
1714 tbl->it_ops = &pnv_ioda2_iommu_ops;
1716 ret = pnv_pci_ioda2_table_alloc_pages(nid,
1717 bus_offset, page_shift, window_size,
1718 levels, alloc_userspace_copy, tbl);
1720 iommu_tce_table_put(tbl);
1729 static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe)
1731 struct iommu_table *tbl = NULL;
1733 unsigned long res_start, res_end;
1736 * crashkernel= specifies the kdump kernel's maximum memory at
1737 * some offset and there is no guaranteed the result is a power
1738 * of 2, which will cause errors later.
1740 const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max());
1743 * In memory constrained environments, e.g. kdump kernel, the
1744 * DMA window can be larger than available memory, which will
1745 * cause errors later.
1747 const u64 maxblock = 1UL << (PAGE_SHIFT + MAX_ORDER);
1750 * We create the default window as big as we can. The constraint is
1751 * the max order of allocation possible. The TCE table is likely to
1752 * end up being multilevel and with on-demand allocation in place,
1753 * the initial use is not going to be huge as the default window aims
1754 * to support crippled devices (i.e. not fully 64bit DMAble) only.
1756 /* iommu_table::it_map uses 1 bit per IOMMU page, hence 8 */
1757 const u64 window_size = min((maxblock * 8) << PAGE_SHIFT, max_memory);
1758 /* Each TCE level cannot exceed maxblock so go multilevel if needed */
1759 unsigned long tces_order = ilog2(window_size >> PAGE_SHIFT);
1760 unsigned long tcelevel_order = ilog2(maxblock >> 3);
1761 unsigned int levels = tces_order / tcelevel_order;
1763 if (tces_order % tcelevel_order)
1766 * We try to stick to default levels (which is >1 at the moment) in
1767 * order to save memory by relying on on-demain TCE level allocation.
1769 levels = max_t(unsigned int, levels, POWERNV_IOMMU_DEFAULT_LEVELS);
1771 rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, PAGE_SHIFT,
1772 window_size, levels, false, &tbl);
1774 pe_err(pe, "Failed to create 32-bit TCE table, err %ld",
1779 /* We use top part of 32bit space for MMIO so exclude it from DMA */
1782 if (window_size > pe->phb->ioda.m32_pci_base) {
1783 res_start = pe->phb->ioda.m32_pci_base >> tbl->it_page_shift;
1784 res_end = min(window_size, SZ_4G) >> tbl->it_page_shift;
1787 tbl->it_index = (pe->phb->hose->global_number << 16) | pe->pe_number;
1788 if (iommu_init_table(tbl, pe->phb->hose->node, res_start, res_end))
1789 rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
1793 pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", rc);
1794 iommu_tce_table_put(tbl);
1795 tbl = NULL; /* This clears iommu_table_base below */
1797 if (!pnv_iommu_bypass_disabled)
1798 pnv_pci_ioda2_set_bypass(pe, true);
1801 * Set table base for the case of IOMMU DMA use. Usually this is done
1802 * from dma_dev_setup() which is not called when a device is returned
1803 * from VFIO so do it here.
1806 set_iommu_table_base(&pe->pdev->dev, tbl);
1811 static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
1814 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1816 struct pnv_phb *phb = pe->phb;
1819 pe_info(pe, "Removing DMA window #%d\n", num);
1821 ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
1822 (pe->pe_number << 1) + num,
1823 0/* levels */, 0/* table address */,
1824 0/* table size */, 0/* page size */);
1826 pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
1828 pnv_pci_ioda2_tce_invalidate_pe(pe);
1830 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
1835 #ifdef CONFIG_IOMMU_API
1836 unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
1837 __u64 window_size, __u32 levels)
1839 unsigned long bytes = 0;
1840 const unsigned window_shift = ilog2(window_size);
1841 unsigned entries_shift = window_shift - page_shift;
1842 unsigned table_shift = entries_shift + 3;
1843 unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift);
1844 unsigned long direct_table_size;
1846 if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) ||
1847 !is_power_of_2(window_size))
1850 /* Calculate a direct table size from window_size and levels */
1851 entries_shift = (entries_shift + levels - 1) / levels;
1852 table_shift = entries_shift + 3;
1853 table_shift = max_t(unsigned, table_shift, PAGE_SHIFT);
1854 direct_table_size = 1UL << table_shift;
1856 for ( ; levels; --levels) {
1857 bytes += ALIGN(tce_table_size, direct_table_size);
1859 tce_table_size /= direct_table_size;
1860 tce_table_size <<= 3;
1861 tce_table_size = max_t(unsigned long,
1862 tce_table_size, direct_table_size);
1865 return bytes + bytes; /* one for HW table, one for userspace copy */
1868 static long pnv_pci_ioda2_create_table_userspace(
1869 struct iommu_table_group *table_group,
1870 int num, __u32 page_shift, __u64 window_size, __u32 levels,
1871 struct iommu_table **ptbl)
1873 long ret = pnv_pci_ioda2_create_table(table_group,
1874 num, page_shift, window_size, levels, true, ptbl);
1877 (*ptbl)->it_allocated_size = pnv_pci_ioda2_get_table_size(
1878 page_shift, window_size, levels);
1882 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
1884 struct pci_dev *dev;
1886 list_for_each_entry(dev, &bus->devices, bus_list) {
1887 set_iommu_table_base(&dev->dev, pe->table_group.tables[0]);
1888 dev->dev.archdata.dma_offset = pe->tce_bypass_base;
1890 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
1891 pnv_ioda_setup_bus_dma(pe, dev->subordinate);
1895 static long pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
1897 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1899 /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
1900 struct iommu_table *tbl = pe->table_group.tables[0];
1903 * iommu_ops transfers the ownership per a device and we mode
1904 * the group ownership with the first device in the group.
1909 pnv_pci_ioda2_set_bypass(pe, false);
1910 pnv_pci_ioda2_unset_window(&pe->table_group, 0);
1912 pnv_ioda_setup_bus_dma(pe, pe->pbus);
1914 set_iommu_table_base(&pe->pdev->dev, NULL);
1915 iommu_tce_table_put(tbl);
1920 static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
1922 struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1925 /* See the comment about iommu_ops above */
1926 if (pe->table_group.tables[0])
1928 pnv_pci_ioda2_setup_default_config(pe);
1930 pnv_ioda_setup_bus_dma(pe, pe->pbus);
1933 static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
1934 .get_table_size = pnv_pci_ioda2_get_table_size,
1935 .create_table = pnv_pci_ioda2_create_table_userspace,
1936 .set_window = pnv_pci_ioda2_set_window,
1937 .unset_window = pnv_pci_ioda2_unset_window,
1938 .take_ownership = pnv_ioda2_take_ownership,
1939 .release_ownership = pnv_ioda2_release_ownership,
1943 void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
1944 struct pnv_ioda_pe *pe)
1948 /* TVE #1 is selected by PCI address bit 59 */
1949 pe->tce_bypass_base = 1ull << 59;
1951 /* The PE will reserve all possible 32-bits space */
1952 pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
1953 phb->ioda.m32_pci_base);
1955 /* Setup linux iommu table */
1956 pe->table_group.tce32_start = 0;
1957 pe->table_group.tce32_size = phb->ioda.m32_pci_base;
1958 pe->table_group.max_dynamic_windows_supported =
1959 IOMMU_TABLE_GROUP_MAX_TABLES;
1960 pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
1961 pe->table_group.pgsizes = pnv_ioda_parse_tce_sizes(phb);
1963 rc = pnv_pci_ioda2_setup_default_config(pe);
1967 #ifdef CONFIG_IOMMU_API
1968 pe->table_group.ops = &pnv_pci_ioda2_ops;
1969 iommu_register_group(&pe->table_group, phb->hose->global_number,
1972 pe->dma_setup_done = true;
1976 * Called from KVM in real mode to EOI passthru interrupts. The ICP
1977 * EOI is handled directly in KVM in kvmppc_deliver_irq_passthru().
1979 * The IRQ data is mapped in the PCI-MSI domain and the EOI OPAL call
1980 * needs an HW IRQ number mapped in the XICS IRQ domain. The HW IRQ
1981 * numbers of the in-the-middle MSI domain are vector numbers and it's
1982 * good enough for OPAL. Use that.
1984 int64_t pnv_opal_pci_msi_eoi(struct irq_data *d)
1986 struct pci_controller *hose = irq_data_get_irq_chip_data(d->parent_data);
1987 struct pnv_phb *phb = hose->private_data;
1989 return opal_pci_msi_eoi(phb->opal_id, d->parent_data->hwirq);
1993 * The IRQ data is mapped in the XICS domain, with OPAL HW IRQ numbers
1995 static void pnv_ioda2_msi_eoi(struct irq_data *d)
1998 unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
1999 struct pci_controller *hose = irq_data_get_irq_chip_data(d);
2000 struct pnv_phb *phb = hose->private_data;
2002 rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
2009 void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
2011 struct irq_data *idata;
2012 struct irq_chip *ichip;
2014 /* The MSI EOI OPAL call is only needed on PHB3 */
2015 if (phb->model != PNV_PHB_MODEL_PHB3)
2018 if (!phb->ioda.irq_chip_init) {
2020 * First time we setup an MSI IRQ, we need to setup the
2021 * corresponding IRQ chip to route correctly.
2023 idata = irq_get_irq_data(virq);
2024 ichip = irq_data_get_irq_chip(idata);
2025 phb->ioda.irq_chip_init = 1;
2026 phb->ioda.irq_chip = *ichip;
2027 phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
2029 irq_set_chip(virq, &phb->ioda.irq_chip);
2030 irq_set_chip_data(virq, phb->hose);
2033 static struct irq_chip pnv_pci_msi_irq_chip;
2036 * Returns true iff chip is something that we could call
2037 * pnv_opal_pci_msi_eoi for.
2039 bool is_pnv_opal_msi(struct irq_chip *chip)
2041 return chip == &pnv_pci_msi_irq_chip;
2043 EXPORT_SYMBOL_GPL(is_pnv_opal_msi);
2045 static int __pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
2046 unsigned int xive_num,
2047 unsigned int is_64, struct msi_msg *msg)
2049 struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
2053 dev_dbg(&dev->dev, "%s: setup %s-bit MSI for vector #%d\n", __func__,
2054 is_64 ? "64" : "32", xive_num);
2056 /* No PE assigned ? bail out ... no MSI for you ! */
2060 /* Check if we have an MVE */
2061 if (pe->mve_number < 0)
2064 /* Force 32-bit MSI on some broken devices */
2065 if (dev->no_64bit_msi)
2068 /* Assign XIVE to PE */
2069 rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
2071 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
2072 pci_name(dev), rc, xive_num);
2079 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
2082 pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
2086 msg->address_hi = be64_to_cpu(addr64) >> 32;
2087 msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful;
2091 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
2094 pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
2098 msg->address_hi = 0;
2099 msg->address_lo = be32_to_cpu(addr32);
2101 msg->data = be32_to_cpu(data);
2107 * The msi_free() op is called before irq_domain_free_irqs_top() when
2108 * the handler data is still available. Use that to clear the XIVE
2111 static void pnv_msi_ops_msi_free(struct irq_domain *domain,
2112 struct msi_domain_info *info,
2116 xive_irq_free_data(irq);
2119 static struct msi_domain_ops pnv_pci_msi_domain_ops = {
2120 .msi_free = pnv_msi_ops_msi_free,
2123 static void pnv_msi_shutdown(struct irq_data *d)
2126 if (d->chip->irq_shutdown)
2127 d->chip->irq_shutdown(d);
2130 static void pnv_msi_mask(struct irq_data *d)
2132 pci_msi_mask_irq(d);
2133 irq_chip_mask_parent(d);
2136 static void pnv_msi_unmask(struct irq_data *d)
2138 pci_msi_unmask_irq(d);
2139 irq_chip_unmask_parent(d);
2142 static struct irq_chip pnv_pci_msi_irq_chip = {
2143 .name = "PNV-PCI-MSI",
2144 .irq_shutdown = pnv_msi_shutdown,
2145 .irq_mask = pnv_msi_mask,
2146 .irq_unmask = pnv_msi_unmask,
2147 .irq_eoi = irq_chip_eoi_parent,
2150 static struct msi_domain_info pnv_msi_domain_info = {
2151 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
2152 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
2153 .ops = &pnv_pci_msi_domain_ops,
2154 .chip = &pnv_pci_msi_irq_chip,
2157 static void pnv_msi_compose_msg(struct irq_data *d, struct msi_msg *msg)
2159 struct msi_desc *entry = irq_data_get_msi_desc(d);
2160 struct pci_dev *pdev = msi_desc_to_pci_dev(entry);
2161 struct pci_controller *hose = irq_data_get_irq_chip_data(d);
2162 struct pnv_phb *phb = hose->private_data;
2165 rc = __pnv_pci_ioda_msi_setup(phb, pdev, d->hwirq,
2166 entry->pci.msi_attrib.is_64, msg);
2168 dev_err(&pdev->dev, "Failed to setup %s-bit MSI #%ld : %d\n",
2169 entry->pci.msi_attrib.is_64 ? "64" : "32", d->hwirq, rc);
2173 * The IRQ data is mapped in the MSI domain in which HW IRQ numbers
2174 * correspond to vector numbers.
2176 static void pnv_msi_eoi(struct irq_data *d)
2178 struct pci_controller *hose = irq_data_get_irq_chip_data(d);
2179 struct pnv_phb *phb = hose->private_data;
2181 if (phb->model == PNV_PHB_MODEL_PHB3) {
2183 * The EOI OPAL call takes an OPAL HW IRQ number but
2184 * since it is translated into a vector number in
2185 * OPAL, use that directly.
2187 WARN_ON_ONCE(opal_pci_msi_eoi(phb->opal_id, d->hwirq));
2190 irq_chip_eoi_parent(d);
2193 static struct irq_chip pnv_msi_irq_chip = {
2195 .irq_shutdown = pnv_msi_shutdown,
2196 .irq_mask = irq_chip_mask_parent,
2197 .irq_unmask = irq_chip_unmask_parent,
2198 .irq_eoi = pnv_msi_eoi,
2199 .irq_set_affinity = irq_chip_set_affinity_parent,
2200 .irq_compose_msi_msg = pnv_msi_compose_msg,
2203 static int pnv_irq_parent_domain_alloc(struct irq_domain *domain,
2204 unsigned int virq, int hwirq)
2206 struct irq_fwspec parent_fwspec;
2209 parent_fwspec.fwnode = domain->parent->fwnode;
2210 parent_fwspec.param_count = 2;
2211 parent_fwspec.param[0] = hwirq;
2212 parent_fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
2214 ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
2221 static int pnv_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
2222 unsigned int nr_irqs, void *arg)
2224 struct pci_controller *hose = domain->host_data;
2225 struct pnv_phb *phb = hose->private_data;
2226 msi_alloc_info_t *info = arg;
2227 struct pci_dev *pdev = msi_desc_to_pci_dev(info->desc);
2231 hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, nr_irqs);
2233 dev_warn(&pdev->dev, "failed to find a free MSI\n");
2237 dev_dbg(&pdev->dev, "%s bridge %pOF %d/%x #%d\n", __func__,
2238 hose->dn, virq, hwirq, nr_irqs);
2240 for (i = 0; i < nr_irqs; i++) {
2241 ret = pnv_irq_parent_domain_alloc(domain, virq + i,
2242 phb->msi_base + hwirq + i);
2246 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
2247 &pnv_msi_irq_chip, hose);
2253 irq_domain_free_irqs_parent(domain, virq, i - 1);
2254 msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, nr_irqs);
2258 static void pnv_irq_domain_free(struct irq_domain *domain, unsigned int virq,
2259 unsigned int nr_irqs)
2261 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
2262 struct pci_controller *hose = irq_data_get_irq_chip_data(d);
2263 struct pnv_phb *phb = hose->private_data;
2265 pr_debug("%s bridge %pOF %d/%lx #%d\n", __func__, hose->dn,
2266 virq, d->hwirq, nr_irqs);
2268 msi_bitmap_free_hwirqs(&phb->msi_bmp, d->hwirq, nr_irqs);
2269 /* XIVE domain is cleared through ->msi_free() */
2272 static const struct irq_domain_ops pnv_irq_domain_ops = {
2273 .alloc = pnv_irq_domain_alloc,
2274 .free = pnv_irq_domain_free,
2277 static int __init pnv_msi_allocate_domains(struct pci_controller *hose, unsigned int count)
2279 struct pnv_phb *phb = hose->private_data;
2280 struct irq_domain *parent = irq_get_default_host();
2282 hose->fwnode = irq_domain_alloc_named_id_fwnode("PNV-MSI", phb->opal_id);
2286 hose->dev_domain = irq_domain_create_hierarchy(parent, 0, count,
2288 &pnv_irq_domain_ops, hose);
2289 if (!hose->dev_domain) {
2290 pr_err("PCI: failed to create IRQ domain bridge %pOF (domain %d)\n",
2291 hose->dn, hose->global_number);
2292 irq_domain_free_fwnode(hose->fwnode);
2296 hose->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(hose->dn),
2297 &pnv_msi_domain_info,
2299 if (!hose->msi_domain) {
2300 pr_err("PCI: failed to create MSI IRQ domain bridge %pOF (domain %d)\n",
2301 hose->dn, hose->global_number);
2302 irq_domain_free_fwnode(hose->fwnode);
2303 irq_domain_remove(hose->dev_domain);
2310 static void __init pnv_pci_init_ioda_msis(struct pnv_phb *phb)
2313 const __be32 *prop = of_get_property(phb->hose->dn,
2314 "ibm,opal-msi-ranges", NULL);
2317 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
2322 phb->msi_base = be32_to_cpup(prop);
2323 count = be32_to_cpup(prop + 1);
2324 if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
2325 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
2326 phb->hose->global_number);
2330 pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
2331 count, phb->msi_base);
2333 pnv_msi_allocate_domains(phb->hose, count);
2336 static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe,
2337 struct resource *res)
2339 struct pnv_phb *phb = pe->phb;
2340 struct pci_bus_region region;
2344 if (!res || !res->flags || res->start > res->end ||
2345 res->flags & IORESOURCE_UNSET)
2348 if (res->flags & IORESOURCE_IO) {
2349 region.start = res->start - phb->ioda.io_pci_base;
2350 region.end = res->end - phb->ioda.io_pci_base;
2351 index = region.start / phb->ioda.io_segsize;
2353 while (index < phb->ioda.total_pe_num &&
2354 region.start <= region.end) {
2355 phb->ioda.io_segmap[index] = pe->pe_number;
2356 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2357 pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
2358 if (rc != OPAL_SUCCESS) {
2359 pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n",
2360 __func__, rc, index, pe->pe_number);
2364 region.start += phb->ioda.io_segsize;
2367 } else if ((res->flags & IORESOURCE_MEM) &&
2368 !pnv_pci_is_m64(phb, res)) {
2369 region.start = res->start -
2370 phb->hose->mem_offset[0] -
2371 phb->ioda.m32_pci_base;
2372 region.end = res->end -
2373 phb->hose->mem_offset[0] -
2374 phb->ioda.m32_pci_base;
2375 index = region.start / phb->ioda.m32_segsize;
2377 while (index < phb->ioda.total_pe_num &&
2378 region.start <= region.end) {
2379 phb->ioda.m32_segmap[index] = pe->pe_number;
2380 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2381 pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
2382 if (rc != OPAL_SUCCESS) {
2383 pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x",
2384 __func__, rc, index, pe->pe_number);
2388 region.start += phb->ioda.m32_segsize;
2395 * This function is supposed to be called on basis of PE from top
2396 * to bottom style. So the I/O or MMIO segment assigned to
2397 * parent PE could be overridden by its child PEs if necessary.
2399 static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe)
2401 struct pci_dev *pdev;
2405 * NOTE: We only care PCI bus based PE for now. For PCI
2406 * device based PE, for example SRIOV sensitive VF should
2407 * be figured out later.
2409 BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
2411 list_for_each_entry(pdev, &pe->pbus->devices, bus_list) {
2412 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
2413 pnv_ioda_setup_pe_res(pe, &pdev->resource[i]);
2416 * If the PE contains all subordinate PCI buses, the
2417 * windows of the child bridges should be mapped to
2420 if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev))
2422 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
2423 pnv_ioda_setup_pe_res(pe,
2424 &pdev->resource[PCI_BRIDGE_RESOURCES + i]);
2428 #ifdef CONFIG_DEBUG_FS
2429 static int pnv_pci_diag_data_set(void *data, u64 val)
2431 struct pnv_phb *phb = data;
2434 /* Retrieve the diag data from firmware */
2435 ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data,
2436 phb->diag_data_size);
2437 if (ret != OPAL_SUCCESS)
2440 /* Print the diag data to the kernel log */
2441 pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data);
2445 DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, pnv_pci_diag_data_set,
2448 static int pnv_pci_ioda_pe_dump(void *data, u64 val)
2450 struct pnv_phb *phb = data;
2453 for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) {
2454 struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_num];
2456 if (!test_bit(pe_num, phb->ioda.pe_alloc))
2459 pe_warn(pe, "rid: %04x dev count: %2d flags: %s%s%s%s%s%s\n",
2460 pe->rid, pe->device_count,
2461 (pe->flags & PNV_IODA_PE_DEV) ? "dev " : "",
2462 (pe->flags & PNV_IODA_PE_BUS) ? "bus " : "",
2463 (pe->flags & PNV_IODA_PE_BUS_ALL) ? "all " : "",
2464 (pe->flags & PNV_IODA_PE_MASTER) ? "master " : "",
2465 (pe->flags & PNV_IODA_PE_SLAVE) ? "slave " : "",
2466 (pe->flags & PNV_IODA_PE_VF) ? "vf " : "");
2472 DEFINE_DEBUGFS_ATTRIBUTE(pnv_pci_ioda_pe_dump_fops, NULL,
2473 pnv_pci_ioda_pe_dump, "%llu\n");
2475 #endif /* CONFIG_DEBUG_FS */
2477 static void pnv_pci_ioda_create_dbgfs(void)
2479 #ifdef CONFIG_DEBUG_FS
2480 struct pci_controller *hose, *tmp;
2481 struct pnv_phb *phb;
2484 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
2485 phb = hose->private_data;
2487 sprintf(name, "PCI%04x", hose->global_number);
2488 phb->dbgfs = debugfs_create_dir(name, arch_debugfs_dir);
2490 debugfs_create_file_unsafe("dump_diag_regs", 0200, phb->dbgfs,
2491 phb, &pnv_pci_diag_data_fops);
2492 debugfs_create_file_unsafe("dump_ioda_pe_state", 0200, phb->dbgfs,
2493 phb, &pnv_pci_ioda_pe_dump_fops);
2495 #endif /* CONFIG_DEBUG_FS */
2498 static void pnv_pci_enable_bridge(struct pci_bus *bus)
2500 struct pci_dev *dev = bus->self;
2501 struct pci_bus *child;
2503 /* Empty bus ? bail */
2504 if (list_empty(&bus->devices))
2508 * If there's a bridge associated with that bus enable it. This works
2509 * around races in the generic code if the enabling is done during
2510 * parallel probing. This can be removed once those races have been
2514 int rc = pci_enable_device(dev);
2516 pci_err(dev, "Error enabling bridge (%d)\n", rc);
2517 pci_set_master(dev);
2520 /* Perform the same to child busses */
2521 list_for_each_entry(child, &bus->children, node)
2522 pnv_pci_enable_bridge(child);
2525 static void pnv_pci_enable_bridges(void)
2527 struct pci_controller *hose;
2529 list_for_each_entry(hose, &hose_list, list_node)
2530 pnv_pci_enable_bridge(hose->bus);
2533 static void pnv_pci_ioda_fixup(void)
2535 pnv_pci_ioda_create_dbgfs();
2537 pnv_pci_enable_bridges();
2540 pnv_eeh_post_init();
2545 * Returns the alignment for I/O or memory windows for P2P
2546 * bridges. That actually depends on how PEs are segmented.
2547 * For now, we return I/O or M32 segment size for PE sensitive
2548 * P2P bridges. Otherwise, the default values (4KiB for I/O,
2549 * 1MiB for memory) will be returned.
2551 * The current PCI bus might be put into one PE, which was
2552 * create against the parent PCI bridge. For that case, we
2553 * needn't enlarge the alignment so that we can save some
2556 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
2559 struct pnv_phb *phb = pci_bus_to_pnvhb(bus);
2560 int num_pci_bridges = 0;
2561 struct pci_dev *bridge;
2565 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
2567 if (num_pci_bridges >= 2)
2571 bridge = bridge->bus->self;
2575 * We fall back to M32 if M64 isn't supported. We enforce the M64
2576 * alignment for any 64-bit resource, PCIe doesn't care and
2577 * bridges only do 64-bit prefetchable anyway.
2579 if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type))
2580 return phb->ioda.m64_segsize;
2581 if (type & IORESOURCE_MEM)
2582 return phb->ioda.m32_segsize;
2584 return phb->ioda.io_segsize;
2588 * We are updating root port or the upstream port of the
2589 * bridge behind the root port with PHB's windows in order
2590 * to accommodate the changes on required resources during
2591 * PCI (slot) hotplug, which is connected to either root
2592 * port or the downstream ports of PCIe switch behind the
2595 static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus,
2598 struct pci_controller *hose = pci_bus_to_host(bus);
2599 struct pnv_phb *phb = hose->private_data;
2600 struct pci_dev *bridge = bus->self;
2601 struct resource *r, *w;
2602 bool msi_region = false;
2605 /* Check if we need apply fixup to the bridge's windows */
2606 if (!pci_is_root_bus(bridge->bus) &&
2607 !pci_is_root_bus(bridge->bus->self->bus))
2610 /* Fixup the resources */
2611 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
2612 r = &bridge->resource[PCI_BRIDGE_RESOURCES + i];
2613 if (!r->flags || !r->parent)
2617 if (r->flags & type & IORESOURCE_IO)
2618 w = &hose->io_resource;
2619 else if (pnv_pci_is_m64(phb, r) &&
2620 (type & IORESOURCE_PREFETCH) &&
2621 phb->ioda.m64_segsize)
2622 w = &hose->mem_resources[1];
2623 else if (r->flags & type & IORESOURCE_MEM) {
2624 w = &hose->mem_resources[0];
2628 r->start = w->start;
2631 /* The 64KB 32-bits MSI region shouldn't be included in
2632 * the 32-bits bridge window. Otherwise, we can see strange
2633 * issues. One of them is EEH error observed on Garrison.
2635 * Exclude top 1MB region which is the minimal alignment of
2636 * 32-bits bridge window.
2645 static void pnv_pci_configure_bus(struct pci_bus *bus)
2647 struct pci_dev *bridge = bus->self;
2648 struct pnv_ioda_pe *pe;
2649 bool all = (bridge && pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE);
2651 dev_info(&bus->dev, "Configuring PE for bus\n");
2653 /* Don't assign PE to PCI bus, which doesn't have subordinate devices */
2654 if (WARN_ON(list_empty(&bus->devices)))
2657 /* Reserve PEs according to used M64 resources */
2658 pnv_ioda_reserve_m64_pe(bus, NULL, all);
2661 * Assign PE. We might run here because of partial hotplug.
2662 * For the case, we just pick up the existing PE and should
2663 * not allocate resources again.
2665 pe = pnv_ioda_setup_bus_PE(bus, all);
2669 pnv_ioda_setup_pe_seg(pe);
2672 static resource_size_t pnv_pci_default_alignment(void)
2677 /* Prevent enabling devices for which we couldn't properly
2680 static bool pnv_pci_enable_device_hook(struct pci_dev *dev)
2684 pdn = pci_get_pdn(dev);
2685 if (!pdn || pdn->pe_number == IODA_INVALID_PE) {
2686 pci_err(dev, "pci_enable_device() blocked, no PE assigned.\n");
2693 static bool pnv_ocapi_enable_device_hook(struct pci_dev *dev)
2696 struct pnv_ioda_pe *pe;
2698 pdn = pci_get_pdn(dev);
2702 if (pdn->pe_number == IODA_INVALID_PE) {
2703 pe = pnv_ioda_setup_dev_PE(dev);
2710 static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group,
2713 struct pnv_ioda_pe *pe = container_of(table_group,
2714 struct pnv_ioda_pe, table_group);
2715 struct pnv_phb *phb = pe->phb;
2719 pe_info(pe, "Removing DMA window #%d\n", num);
2720 for (idx = 0; idx < phb->ioda.dma32_count; idx++) {
2721 if (phb->ioda.dma32_segmap[idx] != pe->pe_number)
2724 rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
2725 idx, 0, 0ul, 0ul, 0ul);
2726 if (rc != OPAL_SUCCESS) {
2727 pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n",
2732 phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE;
2735 pnv_pci_unlink_table_and_group(table_group->tables[num], table_group);
2736 return OPAL_SUCCESS;
2739 static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe)
2741 struct iommu_table *tbl = pe->table_group.tables[0];
2744 if (!pe->dma_setup_done)
2747 rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0);
2748 if (rc != OPAL_SUCCESS)
2751 pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size);
2752 if (pe->table_group.group) {
2753 iommu_group_put(pe->table_group.group);
2754 WARN_ON(pe->table_group.group);
2757 free_pages(tbl->it_base, get_order(tbl->it_size << 3));
2758 iommu_tce_table_put(tbl);
2761 void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe)
2763 struct iommu_table *tbl = pe->table_group.tables[0];
2766 if (!pe->dma_setup_done)
2769 rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0);
2771 pe_warn(pe, "OPAL error %lld release DMA window\n", rc);
2773 pnv_pci_ioda2_set_bypass(pe, false);
2774 if (pe->table_group.group) {
2775 iommu_group_put(pe->table_group.group);
2776 WARN_ON(pe->table_group.group);
2779 iommu_tce_table_put(tbl);
2782 static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe,
2786 struct pnv_phb *phb = pe->phb;
2790 for (idx = 0; idx < phb->ioda.total_pe_num; idx++) {
2791 if (map[idx] != pe->pe_number)
2794 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
2795 phb->ioda.reserved_pe_idx, win, 0, idx);
2797 if (rc != OPAL_SUCCESS)
2798 pe_warn(pe, "Error %lld unmapping (%d) segment#%d\n",
2801 map[idx] = IODA_INVALID_PE;
2805 static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe)
2807 struct pnv_phb *phb = pe->phb;
2809 if (phb->type == PNV_PHB_IODA1) {
2810 pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE,
2811 phb->ioda.io_segmap);
2812 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
2813 phb->ioda.m32_segmap);
2814 /* M64 is pre-configured by pnv_ioda1_init_m64() */
2815 } else if (phb->type == PNV_PHB_IODA2) {
2816 pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE,
2817 phb->ioda.m32_segmap);
2821 static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe)
2823 struct pnv_phb *phb = pe->phb;
2824 struct pnv_ioda_pe *slave, *tmp;
2826 pe_info(pe, "Releasing PE\n");
2828 mutex_lock(&phb->ioda.pe_list_mutex);
2829 list_del(&pe->list);
2830 mutex_unlock(&phb->ioda.pe_list_mutex);
2832 switch (phb->type) {
2834 pnv_pci_ioda1_release_pe_dma(pe);
2837 pnv_pci_ioda2_release_pe_dma(pe);
2839 case PNV_PHB_NPU_OCAPI:
2845 pnv_ioda_release_pe_seg(pe);
2846 pnv_ioda_deconfigure_pe(pe->phb, pe);
2848 /* Release slave PEs in the compound PE */
2849 if (pe->flags & PNV_IODA_PE_MASTER) {
2850 list_for_each_entry_safe(slave, tmp, &pe->slaves, list) {
2851 list_del(&slave->list);
2852 pnv_ioda_free_pe(slave);
2857 * The PE for root bus can be removed because of hotplug in EEH
2858 * recovery for fenced PHB error. We need to mark the PE dead so
2859 * that it can be populated again in PCI hot add path. The PE
2860 * shouldn't be destroyed as it's the global reserved resource.
2862 if (phb->ioda.root_pe_idx == pe->pe_number)
2865 pnv_ioda_free_pe(pe);
2868 static void pnv_pci_release_device(struct pci_dev *pdev)
2870 struct pnv_phb *phb = pci_bus_to_pnvhb(pdev->bus);
2871 struct pci_dn *pdn = pci_get_pdn(pdev);
2872 struct pnv_ioda_pe *pe;
2874 /* The VF PE state is torn down when sriov_disable() is called */
2875 if (pdev->is_virtfn)
2878 if (!pdn || pdn->pe_number == IODA_INVALID_PE)
2881 #ifdef CONFIG_PCI_IOV
2883 * FIXME: Try move this to sriov_disable(). It's here since we allocate
2884 * the iov state at probe time since we need to fiddle with the IOV
2887 if (pdev->is_physfn)
2888 kfree(pdev->dev.archdata.iov_data);
2892 * PCI hotplug can happen as part of EEH error recovery. The @pdn
2893 * isn't removed and added afterwards in this scenario. We should
2894 * set the PE number in @pdn to an invalid one. Otherwise, the PE's
2895 * device count is decreased on removing devices while failing to
2896 * be increased on adding devices. It leads to unbalanced PE's device
2897 * count and eventually make normal PCI hotplug path broken.
2899 pe = &phb->ioda.pe_array[pdn->pe_number];
2900 pdn->pe_number = IODA_INVALID_PE;
2902 WARN_ON(--pe->device_count < 0);
2903 if (pe->device_count == 0)
2904 pnv_ioda_release_pe(pe);
2907 static void pnv_pci_ioda_shutdown(struct pci_controller *hose)
2909 struct pnv_phb *phb = hose->private_data;
2911 opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE,
2915 static void pnv_pci_ioda_dma_bus_setup(struct pci_bus *bus)
2917 struct pnv_phb *phb = pci_bus_to_pnvhb(bus);
2918 struct pnv_ioda_pe *pe;
2920 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
2921 if (!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)))
2927 if (bus->number == ((pe->rid >> 8) & 0xFF)) {
2934 #ifdef CONFIG_IOMMU_API
2935 static struct iommu_group *pnv_pci_device_group(struct pci_controller *hose,
2936 struct pci_dev *pdev)
2938 struct pnv_phb *phb = hose->private_data;
2939 struct pnv_ioda_pe *pe;
2942 return ERR_PTR(-ENODEV);
2944 pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8));
2946 return ERR_PTR(-ENODEV);
2948 if (!pe->table_group.group)
2949 return ERR_PTR(-ENODEV);
2951 return iommu_group_ref_get(pe->table_group.group);
2955 static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
2956 .dma_dev_setup = pnv_pci_ioda_dma_dev_setup,
2957 .dma_bus_setup = pnv_pci_ioda_dma_bus_setup,
2958 .iommu_bypass_supported = pnv_pci_ioda_iommu_bypass_supported,
2959 .enable_device_hook = pnv_pci_enable_device_hook,
2960 .release_device = pnv_pci_release_device,
2961 .window_alignment = pnv_pci_window_alignment,
2962 .setup_bridge = pnv_pci_fixup_bridge_resources,
2963 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
2964 .shutdown = pnv_pci_ioda_shutdown,
2965 #ifdef CONFIG_IOMMU_API
2966 .device_group = pnv_pci_device_group,
2970 static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
2971 .enable_device_hook = pnv_ocapi_enable_device_hook,
2972 .release_device = pnv_pci_release_device,
2973 .window_alignment = pnv_pci_window_alignment,
2974 .reset_secondary_bus = pnv_pci_reset_secondary_bus,
2975 .shutdown = pnv_pci_ioda_shutdown,
2978 static void __init pnv_pci_init_ioda_phb(struct device_node *np,
2979 u64 hub_id, int ioda_type)
2981 struct pci_controller *hose;
2982 struct pnv_phb *phb;
2983 unsigned long size, m64map_off, m32map_off, pemap_off;
2984 unsigned long iomap_off = 0, dma32map_off = 0;
2985 struct pnv_ioda_pe *root_pe;
2987 const __be64 *prop64;
2988 const __be32 *prop32;
2995 if (!of_device_is_available(np))
2998 pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np);
3000 prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
3002 pr_err(" Missing \"ibm,opal-phbid\" property !\n");
3005 phb_id = be64_to_cpup(prop64);
3006 pr_debug(" PHB-ID : 0x%016llx\n", phb_id);
3008 phb = kzalloc(sizeof(*phb), GFP_KERNEL);
3010 panic("%s: Failed to allocate %zu bytes\n", __func__,
3013 /* Allocate PCI controller */
3014 phb->hose = hose = pcibios_alloc_controller(np);
3016 pr_err(" Can't allocate PCI controller for %pOF\n",
3018 memblock_free(phb, sizeof(struct pnv_phb));
3022 spin_lock_init(&phb->lock);
3023 prop32 = of_get_property(np, "bus-range", &len);
3024 if (prop32 && len == 8) {
3025 hose->first_busno = be32_to_cpu(prop32[0]);
3026 hose->last_busno = be32_to_cpu(prop32[1]);
3028 pr_warn(" Broken <bus-range> on %pOF\n", np);
3029 hose->first_busno = 0;
3030 hose->last_busno = 0xff;
3032 hose->private_data = phb;
3033 phb->hub_id = hub_id;
3034 phb->opal_id = phb_id;
3035 phb->type = ioda_type;
3036 mutex_init(&phb->ioda.pe_alloc_mutex);
3038 /* Detect specific models for error handling */
3039 if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
3040 phb->model = PNV_PHB_MODEL_P7IOC;
3041 else if (of_device_is_compatible(np, "ibm,power8-pciex"))
3042 phb->model = PNV_PHB_MODEL_PHB3;
3044 phb->model = PNV_PHB_MODEL_UNKNOWN;
3046 /* Initialize diagnostic data buffer */
3047 prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL);
3049 phb->diag_data_size = be32_to_cpup(prop32);
3051 phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE;
3053 phb->diag_data = kzalloc(phb->diag_data_size, GFP_KERNEL);
3054 if (!phb->diag_data)
3055 panic("%s: Failed to allocate %u bytes\n", __func__,
3056 phb->diag_data_size);
3058 /* Parse 32-bit and IO ranges (if any) */
3059 pci_process_bridge_OF_ranges(hose, np, !hose->global_number);
3062 if (!of_address_to_resource(np, 0, &r)) {
3063 phb->regs_phys = r.start;
3064 phb->regs = ioremap(r.start, resource_size(&r));
3065 if (phb->regs == NULL)
3066 pr_err(" Failed to map registers !\n");
3069 /* Initialize more IODA stuff */
3070 phb->ioda.total_pe_num = 1;
3071 prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
3073 phb->ioda.total_pe_num = be32_to_cpup(prop32);
3074 prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL);
3076 phb->ioda.reserved_pe_idx = be32_to_cpup(prop32);
3078 /* Invalidate RID to PE# mapping */
3079 for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++)
3080 phb->ioda.pe_rmap[segno] = IODA_INVALID_PE;
3082 /* Parse 64-bit MMIO range */
3083 pnv_ioda_parse_m64_window(phb);
3085 phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
3086 /* FW Has already off top 64k of M32 space (MSI space) */
3087 phb->ioda.m32_size += 0x10000;
3089 phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num;
3090 phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
3091 phb->ioda.io_size = hose->pci_io_size;
3092 phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num;
3093 phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
3095 /* Calculate how many 32-bit TCE segments we have */
3096 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3097 PNV_IODA1_DMA32_SEGSIZE;
3099 /* Allocate aux data & arrays. We don't have IO ports on PHB3 */
3100 size = ALIGN(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8,
3101 sizeof(unsigned long));
3103 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]);
3105 size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]);
3106 if (phb->type == PNV_PHB_IODA1) {
3108 size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]);
3109 dma32map_off = size;
3110 size += phb->ioda.dma32_count *
3111 sizeof(phb->ioda.dma32_segmap[0]);
3114 size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe);
3115 aux = kzalloc(size, GFP_KERNEL);
3117 panic("%s: Failed to allocate %lu bytes\n", __func__, size);
3119 phb->ioda.pe_alloc = aux;
3120 phb->ioda.m64_segmap = aux + m64map_off;
3121 phb->ioda.m32_segmap = aux + m32map_off;
3122 for (segno = 0; segno < phb->ioda.total_pe_num; segno++) {
3123 phb->ioda.m64_segmap[segno] = IODA_INVALID_PE;
3124 phb->ioda.m32_segmap[segno] = IODA_INVALID_PE;
3126 if (phb->type == PNV_PHB_IODA1) {
3127 phb->ioda.io_segmap = aux + iomap_off;
3128 for (segno = 0; segno < phb->ioda.total_pe_num; segno++)
3129 phb->ioda.io_segmap[segno] = IODA_INVALID_PE;
3131 phb->ioda.dma32_segmap = aux + dma32map_off;
3132 for (segno = 0; segno < phb->ioda.dma32_count; segno++)
3133 phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE;
3135 phb->ioda.pe_array = aux + pemap_off;
3138 * Choose PE number for root bus, which shouldn't have
3139 * M64 resources consumed by its child devices. To pick
3140 * the PE number adjacent to the reserved one if possible.
3142 pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx);
3143 if (phb->ioda.reserved_pe_idx == 0) {
3144 phb->ioda.root_pe_idx = 1;
3145 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3146 } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) {
3147 phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1;
3148 pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx);
3150 /* otherwise just allocate one */
3151 root_pe = pnv_ioda_alloc_pe(phb, 1);
3152 phb->ioda.root_pe_idx = root_pe->pe_number;
3155 INIT_LIST_HEAD(&phb->ioda.pe_list);
3156 mutex_init(&phb->ioda.pe_list_mutex);
3158 /* Calculate how many 32-bit TCE segments we have */
3159 phb->ioda.dma32_count = phb->ioda.m32_pci_base /
3160 PNV_IODA1_DMA32_SEGSIZE;
3162 #if 0 /* We should really do that ... */
3163 rc = opal_pci_set_phb_mem_window(opal->phb_id,
3166 starting_real_address,
3167 starting_pci_address,
3171 pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n",
3172 phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx,
3173 phb->ioda.m32_size, phb->ioda.m32_segsize);
3174 if (phb->ioda.m64_size)
3175 pr_info(" M64: 0x%lx [segment=0x%lx]\n",
3176 phb->ioda.m64_size, phb->ioda.m64_segsize);
3177 if (phb->ioda.io_size)
3178 pr_info(" IO: 0x%x [segment=0x%x]\n",
3179 phb->ioda.io_size, phb->ioda.io_segsize);
3182 phb->hose->ops = &pnv_pci_ops;
3183 phb->get_pe_state = pnv_ioda_get_pe_state;
3184 phb->freeze_pe = pnv_ioda_freeze_pe;
3185 phb->unfreeze_pe = pnv_ioda_unfreeze_pe;
3187 /* Setup MSI support */
3188 pnv_pci_init_ioda_msis(phb);
3191 * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
3192 * to let the PCI core do resource assignment. It's supposed
3193 * that the PCI core will do correct I/O and MMIO alignment
3194 * for the P2P bridge bars so that each PCI bus (excluding
3195 * the child P2P bridges) can form individual PE.
3197 ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
3199 switch (phb->type) {
3200 case PNV_PHB_NPU_OCAPI:
3201 hose->controller_ops = pnv_npu_ocapi_ioda_controller_ops;
3204 hose->controller_ops = pnv_pci_ioda_controller_ops;
3207 ppc_md.pcibios_default_alignment = pnv_pci_default_alignment;
3209 #ifdef CONFIG_PCI_IOV
3210 ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov;
3211 ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment;
3212 ppc_md.pcibios_sriov_enable = pnv_pcibios_sriov_enable;
3213 ppc_md.pcibios_sriov_disable = pnv_pcibios_sriov_disable;
3216 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
3218 /* Reset IODA tables to a clean state */
3219 rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET);
3221 pr_warn(" OPAL Error %ld performing IODA table reset !\n", rc);
3224 * If we're running in kdump kernel, the previous kernel never
3225 * shutdown PCI devices correctly. We already got IODA table
3226 * cleaned out. So we have to issue PHB reset to stop all PCI
3227 * transactions from previous kernel. The ppc_pci_reset_phbs
3228 * kernel parameter will force this reset too. Additionally,
3229 * if the IODA reset above failed then use a bigger hammer.
3230 * This can happen if we get a PHB fatal error in very early
3233 if (is_kdump_kernel() || pci_reset_phbs || rc) {
3234 pr_info(" Issue PHB reset ...\n");
3235 pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL);
3236 pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE);
3239 /* Remove M64 resource if we can't configure it successfully */
3240 if (!phb->init_m64 || phb->init_m64(phb))
3241 hose->mem_resources[1].flags = 0;
3243 /* create pci_dn's for DT nodes under this PHB */
3244 pci_devs_phb_init_dynamic(hose);
3247 void __init pnv_pci_init_ioda2_phb(struct device_node *np)
3249 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
3252 void __init pnv_pci_init_npu2_opencapi_phb(struct device_node *np)
3254 pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU_OCAPI);
3257 static void pnv_npu2_opencapi_cfg_size_fixup(struct pci_dev *dev)
3259 struct pnv_phb *phb = pci_bus_to_pnvhb(dev->bus);
3261 if (!machine_is(powernv))
3264 if (phb->type == PNV_PHB_NPU_OCAPI)
3265 dev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
3267 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pnv_npu2_opencapi_cfg_size_fixup);
3269 void __init pnv_pci_init_ioda_hub(struct device_node *np)
3271 struct device_node *phbn;
3272 const __be64 *prop64;
3275 pr_info("Probing IODA IO-Hub %pOF\n", np);
3277 prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
3279 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
3282 hub_id = be64_to_cpup(prop64);
3283 pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
3285 /* Count child PHBs */
3286 for_each_child_of_node(np, phbn) {
3287 /* Look for IODA1 PHBs */
3288 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
3289 pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);