2 * The file intends to implement the platform dependent EEH operations on
3 * powernv platform. Actually, the powernv was created in order to fully
6 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/atomic.h>
15 #include <linux/debugfs.h>
16 #include <linux/delay.h>
17 #include <linux/export.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/list.h>
21 #include <linux/msi.h>
23 #include <linux/pci.h>
24 #include <linux/proc_fs.h>
25 #include <linux/rbtree.h>
26 #include <linux/sched.h>
27 #include <linux/seq_file.h>
28 #include <linux/spinlock.h>
31 #include <asm/eeh_event.h>
32 #include <asm/firmware.h>
34 #include <asm/iommu.h>
35 #include <asm/machdep.h>
36 #include <asm/msi_bitmap.h>
38 #include <asm/ppc-pci.h>
39 #include <asm/pnv-pci.h>
44 static bool pnv_eeh_nb_init = false;
45 static int eeh_event_irq = -EINVAL;
47 static int pnv_eeh_init(void)
49 struct pci_controller *hose;
52 if (!firmware_has_feature(FW_FEATURE_OPAL)) {
53 pr_warn("%s: OPAL is required !\n",
59 eeh_add_flag(EEH_PROBE_MODE_DEV);
62 * P7IOC blocks PCI config access to frozen PE, but PHB3
63 * doesn't do that. So we have to selectively enable I/O
64 * prior to collecting error log.
66 list_for_each_entry(hose, &hose_list, list_node) {
67 phb = hose->private_data;
69 if (phb->model == PNV_PHB_MODEL_P7IOC)
70 eeh_add_flag(EEH_ENABLE_IO_FOR_LOG);
73 * PE#0 should be regarded as valid by EEH core
74 * if it's not the reserved one. Currently, we
75 * have the reserved PE#255 and PE#127 for PHB3
76 * and P7IOC separately. So we should regard
77 * PE#0 as valid for PHB3 and P7IOC.
79 if (phb->ioda.reserved_pe_idx != 0)
80 eeh_add_flag(EEH_VALID_PE_ZERO);
88 static irqreturn_t pnv_eeh_event(int irq, void *data)
91 * We simply send a special EEH event if EEH has been
92 * enabled. We don't care about EEH events until we've
93 * finished processing the outstanding ones. Event processing
94 * gets unmasked in next_error() if EEH is enabled.
96 disable_irq_nosync(irq);
99 eeh_send_failure_event(NULL);
104 #ifdef CONFIG_DEBUG_FS
105 static ssize_t pnv_eeh_ei_write(struct file *filp,
106 const char __user *user_buf,
107 size_t count, loff_t *ppos)
109 struct pci_controller *hose = filp->private_data;
110 struct eeh_dev *edev;
112 int pe_no, type, func;
113 unsigned long addr, mask;
117 if (!eeh_ops || !eeh_ops->err_inject)
120 /* Copy over argument buffer */
121 ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
125 /* Retrieve parameters */
126 ret = sscanf(buf, "%x:%x:%x:%lx:%lx",
127 &pe_no, &type, &func, &addr, &mask);
132 edev = kzalloc(sizeof(*edev), GFP_KERNEL);
136 edev->pe_config_addr = pe_no;
137 pe = eeh_pe_get(edev);
142 /* Do error injection */
143 ret = eeh_ops->err_inject(pe, type, func, addr, mask);
144 return ret < 0 ? ret : count;
147 static const struct file_operations pnv_eeh_ei_fops = {
150 .write = pnv_eeh_ei_write,
153 static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val)
155 struct pci_controller *hose = data;
156 struct pnv_phb *phb = hose->private_data;
158 out_be64(phb->regs + offset, val);
162 static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val)
164 struct pci_controller *hose = data;
165 struct pnv_phb *phb = hose->private_data;
167 *val = in_be64(phb->regs + offset);
171 #define PNV_EEH_DBGFS_ENTRY(name, reg) \
172 static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \
174 return pnv_eeh_dbgfs_set(data, reg, val); \
177 static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \
179 return pnv_eeh_dbgfs_get(data, reg, val); \
182 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \
183 pnv_eeh_dbgfs_get_##name, \
184 pnv_eeh_dbgfs_set_##name, \
187 PNV_EEH_DBGFS_ENTRY(outb, 0xD10);
188 PNV_EEH_DBGFS_ENTRY(inbA, 0xD90);
189 PNV_EEH_DBGFS_ENTRY(inbB, 0xE10);
191 #endif /* CONFIG_DEBUG_FS */
194 * pnv_eeh_post_init - EEH platform dependent post initialization
196 * EEH platform dependent post initialization on powernv. When
197 * the function is called, the EEH PEs and devices should have
198 * been built. If the I/O cache staff has been built, EEH is
199 * ready to supply service.
201 static int pnv_eeh_post_init(void)
203 struct pci_controller *hose;
207 /* Register OPAL event notifier */
208 if (!pnv_eeh_nb_init) {
209 eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR));
210 if (eeh_event_irq < 0) {
211 pr_err("%s: Can't register OPAL event interrupt (%d)\n",
212 __func__, eeh_event_irq);
213 return eeh_event_irq;
216 ret = request_irq(eeh_event_irq, pnv_eeh_event,
217 IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL);
219 irq_dispose_mapping(eeh_event_irq);
220 pr_err("%s: Can't request OPAL event interrupt (%d)\n",
221 __func__, eeh_event_irq);
225 pnv_eeh_nb_init = true;
229 disable_irq(eeh_event_irq);
231 list_for_each_entry(hose, &hose_list, list_node) {
232 phb = hose->private_data;
235 * If EEH is enabled, we're going to rely on that.
236 * Otherwise, we restore to conventional mechanism
237 * to clear frozen PE during PCI config access.
240 phb->flags |= PNV_PHB_FLAG_EEH;
242 phb->flags &= ~PNV_PHB_FLAG_EEH;
244 /* Create debugfs entries */
245 #ifdef CONFIG_DEBUG_FS
246 if (phb->has_dbgfs || !phb->dbgfs)
250 debugfs_create_file("err_injct", 0200,
254 debugfs_create_file("err_injct_outbound", 0600,
256 &pnv_eeh_dbgfs_ops_outb);
257 debugfs_create_file("err_injct_inboundA", 0600,
259 &pnv_eeh_dbgfs_ops_inbA);
260 debugfs_create_file("err_injct_inboundB", 0600,
262 &pnv_eeh_dbgfs_ops_inbB);
263 #endif /* CONFIG_DEBUG_FS */
269 static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap)
271 int pos = PCI_CAPABILITY_LIST;
272 int cnt = 48; /* Maximal number of capabilities */
278 /* Check if the device supports capabilities */
279 pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status);
280 if (!(status & PCI_STATUS_CAP_LIST))
284 pnv_pci_cfg_read(pdn, pos, 1, &pos);
289 pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id);
298 pos += PCI_CAP_LIST_NEXT;
304 static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap)
306 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
308 int pos = 256, ttl = (4096 - 256) / 8;
310 if (!edev || !edev->pcie_cap)
312 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
318 if (PCI_EXT_CAP_ID(header) == cap && pos)
321 pos = PCI_EXT_CAP_NEXT(header);
325 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL)
333 * pnv_eeh_probe - Do probe on PCI device
334 * @pdn: PCI device node
337 * When EEH module is installed during system boot, all PCI devices
338 * are checked one by one to see if it supports EEH. The function
339 * is introduced for the purpose. By default, EEH has been enabled
340 * on all PCI devices. That's to say, we only need do necessary
341 * initialization on the corresponding eeh device and create PE
344 * It's notable that's unsafe to retrieve the EEH device through
345 * the corresponding PCI device. During the PCI device hotplug, which
346 * was possiblly triggered by EEH core, the binding between EEH device
347 * and the PCI device isn't built yet.
349 static void *pnv_eeh_probe(struct pci_dn *pdn, void *data)
351 struct pci_controller *hose = pdn->phb;
352 struct pnv_phb *phb = hose->private_data;
353 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
358 * When probing the root bridge, which doesn't have any
359 * subordinate PCI devices. We don't have OF node for
360 * the root bridge. So it's not reasonable to continue
363 if (!edev || edev->pe)
366 /* Skip for PCI-ISA bridge */
367 if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA)
370 /* Initialize eeh device */
371 edev->class_code = pdn->class_code;
372 edev->mode &= 0xFFFFFF00;
373 edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX);
374 edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP);
375 edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF);
376 edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR);
377 if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) {
378 edev->mode |= EEH_DEV_BRIDGE;
379 if (edev->pcie_cap) {
380 pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS,
382 pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4;
383 if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT)
384 edev->mode |= EEH_DEV_ROOT_PORT;
385 else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM)
386 edev->mode |= EEH_DEV_DS_PORT;
390 edev->config_addr = (pdn->busno << 8) | (pdn->devfn);
391 edev->pe_config_addr = phb->ioda.pe_rmap[edev->config_addr];
394 ret = eeh_add_to_parent_pe(edev);
396 pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%d)\n",
397 __func__, hose->global_number, pdn->busno,
398 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret);
403 * If the PE contains any one of following adapters, the
404 * PCI config space can't be accessed when dumping EEH log.
405 * Otherwise, we will run into fenced PHB caused by shortage
406 * of outbound credits in the adapter. The PCI config access
407 * should be blocked until PE reset. MMIO access is dropped
408 * by hardware certainly. In order to drop PCI config requests,
409 * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which
410 * will be checked in the backend for PE state retrival. If
411 * the PE becomes frozen for the first time and the flag has
412 * been set for the PE, we will set EEH_PE_CFG_BLOCKED for
413 * that PE to block its config space.
415 * Broadcom Austin 4-ports NICs (14e4:1657)
416 * Broadcom Shiner 4-ports 1G NICs (14e4:168a)
417 * Broadcom Shiner 2-ports 10G NICs (14e4:168e)
419 if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
420 pdn->device_id == 0x1657) ||
421 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
422 pdn->device_id == 0x168a) ||
423 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM &&
424 pdn->device_id == 0x168e))
425 edev->pe->state |= EEH_PE_CFG_RESTRICTED;
428 * Cache the PE primary bus, which can't be fetched when
429 * full hotplug is in progress. In that case, all child
430 * PCI devices of the PE are expected to be removed prior
433 if (!(edev->pe->state & EEH_PE_PRI_BUS)) {
434 edev->pe->bus = pci_find_bus(hose->global_number,
437 edev->pe->state |= EEH_PE_PRI_BUS;
441 * Enable EEH explicitly so that we will do EEH check
442 * while accessing I/O stuff
444 eeh_add_flag(EEH_ENABLED);
446 /* Save memory bars */
453 * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable
455 * @option: operation to be issued
457 * The function is used to control the EEH functionality globally.
458 * Currently, following options are support according to PAPR:
459 * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
461 static int pnv_eeh_set_option(struct eeh_pe *pe, int option)
463 struct pci_controller *hose = pe->phb;
464 struct pnv_phb *phb = hose->private_data;
465 bool freeze_pe = false;
470 case EEH_OPT_DISABLE:
474 case EEH_OPT_THAW_MMIO:
475 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO;
477 case EEH_OPT_THAW_DMA:
478 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA;
480 case EEH_OPT_FREEZE_PE:
482 opt = OPAL_EEH_ACTION_SET_FREEZE_ALL;
485 pr_warn("%s: Invalid option %d\n", __func__, option);
489 /* Freeze master and slave PEs if PHB supports compound PEs */
491 if (phb->freeze_pe) {
492 phb->freeze_pe(phb, pe->addr);
496 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt);
497 if (rc != OPAL_SUCCESS) {
498 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n",
499 __func__, rc, phb->hose->global_number,
507 /* Unfreeze master and slave PEs if PHB supports */
508 if (phb->unfreeze_pe)
509 return phb->unfreeze_pe(phb, pe->addr, opt);
511 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt);
512 if (rc != OPAL_SUCCESS) {
513 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n",
514 __func__, rc, option, phb->hose->global_number,
523 * pnv_eeh_get_pe_addr - Retrieve PE address
526 * Retrieve the PE address according to the given tranditional
527 * PCI BDF (Bus/Device/Function) address.
529 static int pnv_eeh_get_pe_addr(struct eeh_pe *pe)
534 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe)
536 struct pnv_phb *phb = pe->phb->private_data;
539 rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data,
540 PNV_PCI_DIAG_BUF_SIZE);
541 if (rc != OPAL_SUCCESS)
542 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n",
543 __func__, rc, pe->phb->global_number);
546 static int pnv_eeh_get_phb_state(struct eeh_pe *pe)
548 struct pnv_phb *phb = pe->phb->private_data;
554 rc = opal_pci_eeh_freeze_status(phb->opal_id,
559 if (rc != OPAL_SUCCESS) {
560 pr_warn("%s: Failure %lld getting PHB#%x state\n",
561 __func__, rc, phb->hose->global_number);
562 return EEH_STATE_NOT_SUPPORT;
566 * Check PHB state. If the PHB is frozen for the
567 * first time, to dump the PHB diag-data.
569 if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) {
570 result = (EEH_STATE_MMIO_ACTIVE |
571 EEH_STATE_DMA_ACTIVE |
572 EEH_STATE_MMIO_ENABLED |
573 EEH_STATE_DMA_ENABLED);
574 } else if (!(pe->state & EEH_PE_ISOLATED)) {
575 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
576 pnv_eeh_get_phb_diag(pe);
578 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
579 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
585 static int pnv_eeh_get_pe_state(struct eeh_pe *pe)
587 struct pnv_phb *phb = pe->phb->private_data;
594 * We don't clobber hardware frozen state until PE
595 * reset is completed. In order to keep EEH core
596 * moving forward, we have to return operational
597 * state during PE reset.
599 if (pe->state & EEH_PE_RESET) {
600 result = (EEH_STATE_MMIO_ACTIVE |
601 EEH_STATE_DMA_ACTIVE |
602 EEH_STATE_MMIO_ENABLED |
603 EEH_STATE_DMA_ENABLED);
608 * Fetch PE state from hardware. If the PHB
609 * supports compound PE, let it handle that.
611 if (phb->get_pe_state) {
612 fstate = phb->get_pe_state(phb, pe->addr);
614 rc = opal_pci_eeh_freeze_status(phb->opal_id,
619 if (rc != OPAL_SUCCESS) {
620 pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n",
621 __func__, rc, phb->hose->global_number,
623 return EEH_STATE_NOT_SUPPORT;
627 /* Figure out state */
629 case OPAL_EEH_STOPPED_NOT_FROZEN:
630 result = (EEH_STATE_MMIO_ACTIVE |
631 EEH_STATE_DMA_ACTIVE |
632 EEH_STATE_MMIO_ENABLED |
633 EEH_STATE_DMA_ENABLED);
635 case OPAL_EEH_STOPPED_MMIO_FREEZE:
636 result = (EEH_STATE_DMA_ACTIVE |
637 EEH_STATE_DMA_ENABLED);
639 case OPAL_EEH_STOPPED_DMA_FREEZE:
640 result = (EEH_STATE_MMIO_ACTIVE |
641 EEH_STATE_MMIO_ENABLED);
643 case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
646 case OPAL_EEH_STOPPED_RESET:
647 result = EEH_STATE_RESET_ACTIVE;
649 case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
650 result = EEH_STATE_UNAVAILABLE;
652 case OPAL_EEH_STOPPED_PERM_UNAVAIL:
653 result = EEH_STATE_NOT_SUPPORT;
656 result = EEH_STATE_NOT_SUPPORT;
657 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n",
658 __func__, phb->hose->global_number,
663 * If PHB supports compound PE, to freeze all
664 * slave PEs for consistency.
666 * If the PE is switching to frozen state for the
667 * first time, to dump the PHB diag-data.
669 if (!(result & EEH_STATE_NOT_SUPPORT) &&
670 !(result & EEH_STATE_UNAVAILABLE) &&
671 !(result & EEH_STATE_MMIO_ACTIVE) &&
672 !(result & EEH_STATE_DMA_ACTIVE) &&
673 !(pe->state & EEH_PE_ISOLATED)) {
675 phb->freeze_pe(phb, pe->addr);
677 eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
678 pnv_eeh_get_phb_diag(pe);
680 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
681 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
688 * pnv_eeh_get_state - Retrieve PE state
690 * @delay: delay while PE state is temporarily unavailable
692 * Retrieve the state of the specified PE. For IODA-compitable
693 * platform, it should be retrieved from IODA table. Therefore,
694 * we prefer passing down to hardware implementation to handle
697 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay)
701 if (pe->type & EEH_PE_PHB)
702 ret = pnv_eeh_get_phb_state(pe);
704 ret = pnv_eeh_get_pe_state(pe);
710 * If the PE state is temporarily unavailable,
711 * to inform the EEH core delay for default
715 if (ret & EEH_STATE_UNAVAILABLE)
721 static s64 pnv_eeh_poll(unsigned long id)
723 s64 rc = OPAL_HARDWARE;
726 rc = opal_pci_poll(id);
730 if (system_state < SYSTEM_RUNNING)
739 int pnv_eeh_phb_reset(struct pci_controller *hose, int option)
741 struct pnv_phb *phb = hose->private_data;
742 s64 rc = OPAL_HARDWARE;
744 pr_debug("%s: Reset PHB#%x, option=%d\n",
745 __func__, hose->global_number, option);
747 /* Issue PHB complete reset request */
748 if (option == EEH_RESET_FUNDAMENTAL ||
749 option == EEH_RESET_HOT)
750 rc = opal_pci_reset(phb->opal_id,
751 OPAL_RESET_PHB_COMPLETE,
753 else if (option == EEH_RESET_DEACTIVATE)
754 rc = opal_pci_reset(phb->opal_id,
755 OPAL_RESET_PHB_COMPLETE,
756 OPAL_DEASSERT_RESET);
761 * Poll state of the PHB until the request is done
762 * successfully. The PHB reset is usually PHB complete
763 * reset followed by hot reset on root bus. So we also
764 * need the PCI bus settlement delay.
766 rc = pnv_eeh_poll(phb->opal_id);
767 if (option == EEH_RESET_DEACTIVATE) {
768 if (system_state < SYSTEM_RUNNING)
769 udelay(1000 * EEH_PE_RST_SETTLE_TIME);
771 msleep(EEH_PE_RST_SETTLE_TIME);
774 if (rc != OPAL_SUCCESS)
780 static int pnv_eeh_root_reset(struct pci_controller *hose, int option)
782 struct pnv_phb *phb = hose->private_data;
783 s64 rc = OPAL_HARDWARE;
785 pr_debug("%s: Reset PHB#%x, option=%d\n",
786 __func__, hose->global_number, option);
789 * During the reset deassert time, we needn't care
790 * the reset scope because the firmware does nothing
791 * for fundamental or hot reset during deassert phase.
793 if (option == EEH_RESET_FUNDAMENTAL)
794 rc = opal_pci_reset(phb->opal_id,
795 OPAL_RESET_PCI_FUNDAMENTAL,
797 else if (option == EEH_RESET_HOT)
798 rc = opal_pci_reset(phb->opal_id,
801 else if (option == EEH_RESET_DEACTIVATE)
802 rc = opal_pci_reset(phb->opal_id,
804 OPAL_DEASSERT_RESET);
808 /* Poll state of the PHB until the request is done */
809 rc = pnv_eeh_poll(phb->opal_id);
810 if (option == EEH_RESET_DEACTIVATE)
811 msleep(EEH_PE_RST_SETTLE_TIME);
813 if (rc != OPAL_SUCCESS)
819 static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option)
821 struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
822 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
823 int aer = edev ? edev->aer_cap : 0;
826 pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n",
827 __func__, pci_domain_nr(dev->bus),
828 dev->bus->number, option);
831 case EEH_RESET_FUNDAMENTAL:
833 /* Don't report linkDown event */
835 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
837 ctrl |= PCI_ERR_UNC_SURPDN;
838 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
842 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
843 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
844 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
846 msleep(EEH_PE_RST_HOLD_TIME);
848 case EEH_RESET_DEACTIVATE:
849 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl);
850 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
851 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl);
853 msleep(EEH_PE_RST_SETTLE_TIME);
855 /* Continue reporting linkDown event */
857 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK,
859 ctrl &= ~PCI_ERR_UNC_SURPDN;
860 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK,
870 static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option)
872 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
873 struct pnv_phb *phb = hose->private_data;
874 struct device_node *dn = pci_device_to_OF_node(pdev);
875 uint64_t id = PCI_SLOT_ID(phb->opal_id,
876 (pdev->bus->number << 8) | pdev->devfn);
880 /* Hot reset to the bus if firmware cannot handle */
881 if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL))
882 return __pnv_eeh_bridge_reset(pdev, option);
885 case EEH_RESET_FUNDAMENTAL:
886 scope = OPAL_RESET_PCI_FUNDAMENTAL;
889 scope = OPAL_RESET_PCI_HOT;
891 case EEH_RESET_DEACTIVATE:
894 dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n",
899 rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET);
900 if (rc <= OPAL_SUCCESS)
903 rc = pnv_eeh_poll(id);
905 return (rc == OPAL_SUCCESS) ? 0 : -EIO;
908 void pnv_pci_reset_secondary_bus(struct pci_dev *dev)
910 struct pci_controller *hose;
912 if (pci_is_root_bus(dev->bus)) {
913 hose = pci_bus_to_host(dev->bus);
914 pnv_eeh_root_reset(hose, EEH_RESET_HOT);
915 pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE);
917 pnv_eeh_bridge_reset(dev, EEH_RESET_HOT);
918 pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE);
922 static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type,
925 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
928 /* Wait for Transaction Pending bit to be cleared */
929 for (i = 0; i < 4; i++) {
930 eeh_ops->read_config(pdn, pos, 2, &status);
931 if (!(status & mask))
934 msleep((1 << i) * 100);
937 pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n",
939 edev->phb->global_number, pdn->busno,
940 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
943 static int pnv_eeh_do_flr(struct pci_dn *pdn, int option)
945 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
948 if (WARN_ON(!edev->pcie_cap))
951 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®);
952 if (!(reg & PCI_EXP_DEVCAP_FLR))
957 case EEH_RESET_FUNDAMENTAL:
958 pnv_eeh_wait_for_pending(pdn, "",
959 edev->pcie_cap + PCI_EXP_DEVSTA,
960 PCI_EXP_DEVSTA_TRPND);
961 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
963 reg |= PCI_EXP_DEVCTL_BCR_FLR;
964 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
966 msleep(EEH_PE_RST_HOLD_TIME);
968 case EEH_RESET_DEACTIVATE:
969 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
971 reg &= ~PCI_EXP_DEVCTL_BCR_FLR;
972 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
974 msleep(EEH_PE_RST_SETTLE_TIME);
981 static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option)
983 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
986 if (WARN_ON(!edev->af_cap))
989 eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap);
990 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
995 case EEH_RESET_FUNDAMENTAL:
997 * Wait for Transaction Pending bit to clear. A word-aligned
998 * test is used, so we use the conrol offset rather than status
999 * and shift the test bit to match.
1001 pnv_eeh_wait_for_pending(pdn, "AF",
1002 edev->af_cap + PCI_AF_CTRL,
1003 PCI_AF_STATUS_TP << 8);
1004 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL,
1005 1, PCI_AF_CTRL_FLR);
1006 msleep(EEH_PE_RST_HOLD_TIME);
1008 case EEH_RESET_DEACTIVATE:
1009 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0);
1010 msleep(EEH_PE_RST_SETTLE_TIME);
1017 static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option)
1019 struct eeh_dev *edev;
1023 /* The VF PE should have only one child device */
1024 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list);
1025 pdn = eeh_dev_to_pdn(edev);
1029 ret = pnv_eeh_do_flr(pdn, option);
1033 return pnv_eeh_do_af_flr(pdn, option);
1037 * pnv_eeh_reset - Reset the specified PE
1039 * @option: reset option
1041 * Do reset on the indicated PE. For PCI bus sensitive PE,
1042 * we need to reset the parent p2p bridge. The PHB has to
1043 * be reinitialized if the p2p bridge is root bridge. For
1044 * PCI device sensitive PE, we will try to reset the device
1045 * through FLR. For now, we don't have OPAL APIs to do HARD
1046 * reset yet, so all reset would be SOFT (HOT) reset.
1048 static int pnv_eeh_reset(struct eeh_pe *pe, int option)
1050 struct pci_controller *hose = pe->phb;
1051 struct pnv_phb *phb;
1052 struct pci_bus *bus;
1056 * For PHB reset, we always have complete reset. For those PEs whose
1057 * primary bus derived from root complex (root bus) or root port
1058 * (usually bus#1), we apply hot or fundamental reset on the root port.
1059 * For other PEs, we always have hot reset on the PE primary bus.
1061 * Here, we have different design to pHyp, which always clear the
1062 * frozen state during PE reset. However, the good idea here from
1063 * benh is to keep frozen state before we get PE reset done completely
1064 * (until BAR restore). With the frozen state, HW drops illegal IO
1065 * or MMIO access, which can incur recrusive frozen PE during PE
1066 * reset. The side effect is that EEH core has to clear the frozen
1067 * state explicitly after BAR restore.
1069 if (pe->type & EEH_PE_PHB)
1070 return pnv_eeh_phb_reset(hose, option);
1073 * The frozen PE might be caused by PAPR error injection
1074 * registers, which are expected to be cleared after hitting
1075 * frozen PE as stated in the hardware spec. Unfortunately,
1076 * that's not true on P7IOC. So we have to clear it manually
1077 * to avoid recursive EEH errors during recovery.
1079 phb = hose->private_data;
1080 if (phb->model == PNV_PHB_MODEL_P7IOC &&
1081 (option == EEH_RESET_HOT ||
1082 option == EEH_RESET_FUNDAMENTAL)) {
1083 rc = opal_pci_reset(phb->opal_id,
1084 OPAL_RESET_PHB_ERROR,
1086 if (rc != OPAL_SUCCESS) {
1087 pr_warn("%s: Failure %lld clearing error injection registers\n",
1093 bus = eeh_pe_bus_get(pe);
1094 if (pe->type & EEH_PE_VF)
1095 return pnv_eeh_reset_vf_pe(pe, option);
1097 if (pci_is_root_bus(bus) ||
1098 pci_is_root_bus(bus->parent))
1099 return pnv_eeh_root_reset(hose, option);
1101 return pnv_eeh_bridge_reset(bus->self, option);
1105 * pnv_eeh_wait_state - Wait for PE state
1107 * @max_wait: maximal period in millisecond
1109 * Wait for the state of associated PE. It might take some time
1110 * to retrieve the PE's state.
1112 static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait)
1118 ret = pnv_eeh_get_state(pe, &mwait);
1121 * If the PE's state is temporarily unavailable,
1122 * we have to wait for the specified time. Otherwise,
1123 * the PE's state will be returned immediately.
1125 if (ret != EEH_STATE_UNAVAILABLE)
1128 if (max_wait <= 0) {
1129 pr_warn("%s: Timeout getting PE#%x's state (%d)\n",
1130 __func__, pe->addr, max_wait);
1131 return EEH_STATE_NOT_SUPPORT;
1138 return EEH_STATE_NOT_SUPPORT;
1142 * pnv_eeh_get_log - Retrieve error log
1144 * @severity: temporary or permanent error log
1145 * @drv_log: driver log to be combined with retrieved error log
1146 * @len: length of driver log
1148 * Retrieve the temporary or permanent error from the PE.
1150 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity,
1151 char *drv_log, unsigned long len)
1153 if (!eeh_has_flag(EEH_EARLY_DUMP_LOG))
1154 pnv_pci_dump_phb_diag_data(pe->phb, pe->data);
1160 * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
1163 * The function will be called to reconfigure the bridges included
1164 * in the specified PE so that the mulfunctional PE would be recovered
1167 static int pnv_eeh_configure_bridge(struct eeh_pe *pe)
1173 * pnv_pe_err_inject - Inject specified error to the indicated PE
1174 * @pe: the indicated PE
1176 * @func: specific error type
1178 * @mask: address mask
1180 * The routine is called to inject specified error, which is
1181 * determined by @type and @func, to the indicated PE for
1184 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func,
1185 unsigned long addr, unsigned long mask)
1187 struct pci_controller *hose = pe->phb;
1188 struct pnv_phb *phb = hose->private_data;
1191 if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR &&
1192 type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) {
1193 pr_warn("%s: Invalid error type %d\n",
1198 if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR ||
1199 func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) {
1200 pr_warn("%s: Invalid error function %d\n",
1205 /* Firmware supports error injection ? */
1206 if (!opal_check_token(OPAL_PCI_ERR_INJECT)) {
1207 pr_warn("%s: Firmware doesn't support error injection\n",
1212 /* Do error injection */
1213 rc = opal_pci_err_inject(phb->opal_id, pe->addr,
1214 type, func, addr, mask);
1215 if (rc != OPAL_SUCCESS) {
1216 pr_warn("%s: Failure %lld injecting error "
1217 "%d-%d to PHB#%x-PE#%x\n",
1218 __func__, rc, type, func,
1219 hose->global_number, pe->addr);
1226 static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn)
1228 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1230 if (!edev || !edev->pe)
1234 * We will issue FLR or AF FLR to all VFs, which are contained
1235 * in VF PE. It relies on the EEH PCI config accessors. So we
1236 * can't block them during the window.
1238 if (edev->physfn && (edev->pe->state & EEH_PE_RESET))
1241 if (edev->pe->state & EEH_PE_CFG_BLOCKED)
1247 static int pnv_eeh_read_config(struct pci_dn *pdn,
1248 int where, int size, u32 *val)
1251 return PCIBIOS_DEVICE_NOT_FOUND;
1253 if (pnv_eeh_cfg_blocked(pdn)) {
1255 return PCIBIOS_SET_FAILED;
1258 return pnv_pci_cfg_read(pdn, where, size, val);
1261 static int pnv_eeh_write_config(struct pci_dn *pdn,
1262 int where, int size, u32 val)
1265 return PCIBIOS_DEVICE_NOT_FOUND;
1267 if (pnv_eeh_cfg_blocked(pdn))
1268 return PCIBIOS_SET_FAILED;
1270 return pnv_pci_cfg_write(pdn, where, size, val);
1273 static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data)
1276 if (data->gemXfir || data->gemRfir ||
1277 data->gemRirqfir || data->gemMask || data->gemRwof)
1278 pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n",
1279 be64_to_cpu(data->gemXfir),
1280 be64_to_cpu(data->gemRfir),
1281 be64_to_cpu(data->gemRirqfir),
1282 be64_to_cpu(data->gemMask),
1283 be64_to_cpu(data->gemRwof));
1286 if (data->lemFir || data->lemErrMask ||
1287 data->lemAction0 || data->lemAction1 || data->lemWof)
1288 pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n",
1289 be64_to_cpu(data->lemFir),
1290 be64_to_cpu(data->lemErrMask),
1291 be64_to_cpu(data->lemAction0),
1292 be64_to_cpu(data->lemAction1),
1293 be64_to_cpu(data->lemWof));
1296 static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose)
1298 struct pnv_phb *phb = hose->private_data;
1299 struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag;
1302 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
1303 if (rc != OPAL_SUCCESS) {
1304 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n",
1305 __func__, phb->hub_id, rc);
1309 switch (data->type) {
1310 case OPAL_P7IOC_DIAG_TYPE_RGC:
1311 pr_info("P7IOC diag-data for RGC\n\n");
1312 pnv_eeh_dump_hub_diag_common(data);
1313 if (data->rgc.rgcStatus || data->rgc.rgcLdcp)
1314 pr_info(" RGC: %016llx %016llx\n",
1315 be64_to_cpu(data->rgc.rgcStatus),
1316 be64_to_cpu(data->rgc.rgcLdcp));
1318 case OPAL_P7IOC_DIAG_TYPE_BI:
1319 pr_info("P7IOC diag-data for BI %s\n\n",
1320 data->bi.biDownbound ? "Downbound" : "Upbound");
1321 pnv_eeh_dump_hub_diag_common(data);
1322 if (data->bi.biLdcp0 || data->bi.biLdcp1 ||
1323 data->bi.biLdcp2 || data->bi.biFenceStatus)
1324 pr_info(" BI: %016llx %016llx %016llx %016llx\n",
1325 be64_to_cpu(data->bi.biLdcp0),
1326 be64_to_cpu(data->bi.biLdcp1),
1327 be64_to_cpu(data->bi.biLdcp2),
1328 be64_to_cpu(data->bi.biFenceStatus));
1330 case OPAL_P7IOC_DIAG_TYPE_CI:
1331 pr_info("P7IOC diag-data for CI Port %d\n\n",
1333 pnv_eeh_dump_hub_diag_common(data);
1334 if (data->ci.ciPortStatus || data->ci.ciPortLdcp)
1335 pr_info(" CI: %016llx %016llx\n",
1336 be64_to_cpu(data->ci.ciPortStatus),
1337 be64_to_cpu(data->ci.ciPortLdcp));
1339 case OPAL_P7IOC_DIAG_TYPE_MISC:
1340 pr_info("P7IOC diag-data for MISC\n\n");
1341 pnv_eeh_dump_hub_diag_common(data);
1343 case OPAL_P7IOC_DIAG_TYPE_I2C:
1344 pr_info("P7IOC diag-data for I2C\n\n");
1345 pnv_eeh_dump_hub_diag_common(data);
1348 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n",
1349 __func__, phb->hub_id, data->type);
1353 static int pnv_eeh_get_pe(struct pci_controller *hose,
1354 u16 pe_no, struct eeh_pe **pe)
1356 struct pnv_phb *phb = hose->private_data;
1357 struct pnv_ioda_pe *pnv_pe;
1358 struct eeh_pe *dev_pe;
1359 struct eeh_dev edev;
1362 * If PHB supports compound PE, to fetch
1363 * the master PE because slave PE is invisible
1366 pnv_pe = &phb->ioda.pe_array[pe_no];
1367 if (pnv_pe->flags & PNV_IODA_PE_SLAVE) {
1368 pnv_pe = pnv_pe->master;
1370 !(pnv_pe->flags & PNV_IODA_PE_MASTER));
1371 pe_no = pnv_pe->pe_number;
1374 /* Find the PE according to PE# */
1375 memset(&edev, 0, sizeof(struct eeh_dev));
1377 edev.pe_config_addr = pe_no;
1378 dev_pe = eeh_pe_get(&edev);
1382 /* Freeze the (compound) PE */
1384 if (!(dev_pe->state & EEH_PE_ISOLATED))
1385 phb->freeze_pe(phb, pe_no);
1388 * At this point, we're sure the (compound) PE should
1389 * have been frozen. However, we still need poke until
1390 * hitting the frozen PE on top level.
1392 dev_pe = dev_pe->parent;
1393 while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) {
1395 int active_flags = (EEH_STATE_MMIO_ACTIVE |
1396 EEH_STATE_DMA_ACTIVE);
1398 ret = eeh_ops->get_state(dev_pe, NULL);
1399 if (ret <= 0 || (ret & active_flags) == active_flags) {
1400 dev_pe = dev_pe->parent;
1404 /* Frozen parent PE */
1406 if (!(dev_pe->state & EEH_PE_ISOLATED))
1407 phb->freeze_pe(phb, dev_pe->addr);
1410 dev_pe = dev_pe->parent;
1417 * pnv_eeh_next_error - Retrieve next EEH error to handle
1420 * The function is expected to be called by EEH core while it gets
1421 * special EEH event (without binding PE). The function calls to
1422 * OPAL APIs for next error to handle. The informational error is
1423 * handled internally by platform. However, the dead IOC, dead PHB,
1424 * fenced PHB and frozen PE should be handled by EEH core eventually.
1426 static int pnv_eeh_next_error(struct eeh_pe **pe)
1428 struct pci_controller *hose;
1429 struct pnv_phb *phb;
1430 struct eeh_pe *phb_pe, *parent_pe;
1431 __be64 frozen_pe_no;
1432 __be16 err_type, severity;
1433 int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
1435 int state, ret = EEH_NEXT_ERR_NONE;
1438 * While running here, it's safe to purge the event queue. The
1439 * event should still be masked.
1441 eeh_remove_event(NULL, false);
1443 list_for_each_entry(hose, &hose_list, list_node) {
1445 * If the subordinate PCI buses of the PHB has been
1446 * removed or is exactly under error recovery, we
1447 * needn't take care of it any more.
1449 phb = hose->private_data;
1450 phb_pe = eeh_phb_pe_get(hose);
1451 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED))
1454 rc = opal_pci_next_error(phb->opal_id,
1455 &frozen_pe_no, &err_type, &severity);
1456 if (rc != OPAL_SUCCESS) {
1457 pr_devel("%s: Invalid return value on "
1458 "PHB#%x (0x%lx) from opal_pci_next_error",
1459 __func__, hose->global_number, rc);
1463 /* If the PHB doesn't have error, stop processing */
1464 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR ||
1465 be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) {
1466 pr_devel("%s: No error found on PHB#%x\n",
1467 __func__, hose->global_number);
1472 * Processing the error. We're expecting the error with
1473 * highest priority reported upon multiple errors on the
1476 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
1477 __func__, be16_to_cpu(err_type),
1478 be16_to_cpu(severity), be64_to_cpu(frozen_pe_no),
1479 hose->global_number);
1480 switch (be16_to_cpu(err_type)) {
1481 case OPAL_EEH_IOC_ERROR:
1482 if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) {
1483 pr_err("EEH: dead IOC detected\n");
1484 ret = EEH_NEXT_ERR_DEAD_IOC;
1485 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1486 pr_info("EEH: IOC informative error "
1488 pnv_eeh_get_and_dump_hub_diag(hose);
1489 ret = EEH_NEXT_ERR_NONE;
1493 case OPAL_EEH_PHB_ERROR:
1494 if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) {
1496 pr_err("EEH: dead PHB#%x detected, "
1498 hose->global_number,
1499 eeh_pe_loc_get(phb_pe));
1500 ret = EEH_NEXT_ERR_DEAD_PHB;
1501 } else if (be16_to_cpu(severity) ==
1502 OPAL_EEH_SEV_PHB_FENCED) {
1504 pr_err("EEH: Fenced PHB#%x detected, "
1506 hose->global_number,
1507 eeh_pe_loc_get(phb_pe));
1508 ret = EEH_NEXT_ERR_FENCED_PHB;
1509 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
1510 pr_info("EEH: PHB#%x informative error "
1511 "detected, location: %s\n",
1512 hose->global_number,
1513 eeh_pe_loc_get(phb_pe));
1514 pnv_eeh_get_phb_diag(phb_pe);
1515 pnv_pci_dump_phb_diag_data(hose, phb_pe->data);
1516 ret = EEH_NEXT_ERR_NONE;
1520 case OPAL_EEH_PE_ERROR:
1522 * If we can't find the corresponding PE, we
1523 * just try to unfreeze.
1525 if (pnv_eeh_get_pe(hose,
1526 be64_to_cpu(frozen_pe_no), pe)) {
1527 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n",
1528 hose->global_number, be64_to_cpu(frozen_pe_no));
1529 pr_info("EEH: PHB location: %s\n",
1530 eeh_pe_loc_get(phb_pe));
1532 /* Dump PHB diag-data */
1533 rc = opal_pci_get_phb_diag_data2(phb->opal_id,
1534 phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
1535 if (rc == OPAL_SUCCESS)
1536 pnv_pci_dump_phb_diag_data(hose,
1539 /* Try best to clear it */
1540 opal_pci_eeh_freeze_clear(phb->opal_id,
1542 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
1543 ret = EEH_NEXT_ERR_NONE;
1544 } else if ((*pe)->state & EEH_PE_ISOLATED ||
1545 eeh_pe_passed(*pe)) {
1546 ret = EEH_NEXT_ERR_NONE;
1548 pr_err("EEH: Frozen PE#%x "
1549 "on PHB#%x detected\n",
1551 (*pe)->phb->global_number);
1552 pr_err("EEH: PE location: %s, "
1553 "PHB location: %s\n",
1554 eeh_pe_loc_get(*pe),
1555 eeh_pe_loc_get(phb_pe));
1556 ret = EEH_NEXT_ERR_FROZEN_PE;
1561 pr_warn("%s: Unexpected error type %d\n",
1562 __func__, be16_to_cpu(err_type));
1566 * EEH core will try recover from fenced PHB or
1567 * frozen PE. In the time for frozen PE, EEH core
1568 * enable IO path for that before collecting logs,
1569 * but it ruins the site. So we have to dump the
1570 * log in advance here.
1572 if ((ret == EEH_NEXT_ERR_FROZEN_PE ||
1573 ret == EEH_NEXT_ERR_FENCED_PHB) &&
1574 !((*pe)->state & EEH_PE_ISOLATED)) {
1575 eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1576 pnv_eeh_get_phb_diag(*pe);
1578 if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
1579 pnv_pci_dump_phb_diag_data((*pe)->phb,
1584 * We probably have the frozen parent PE out there and
1585 * we need have to handle frozen parent PE firstly.
1587 if (ret == EEH_NEXT_ERR_FROZEN_PE) {
1588 parent_pe = (*pe)->parent;
1590 /* Hit the ceiling ? */
1591 if (parent_pe->type & EEH_PE_PHB)
1594 /* Frozen parent PE ? */
1595 state = eeh_ops->get_state(parent_pe, NULL);
1597 (state & active_flags) != active_flags)
1600 /* Next parent level */
1601 parent_pe = parent_pe->parent;
1604 /* We possibly migrate to another PE */
1605 eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
1609 * If we have no errors on the specific PHB or only
1610 * informative error there, we continue poking it.
1611 * Otherwise, we need actions to be taken by upper
1614 if (ret > EEH_NEXT_ERR_INF)
1618 /* Unmask the event */
1619 if (ret == EEH_NEXT_ERR_NONE && eeh_enabled())
1620 enable_irq(eeh_event_irq);
1625 static int pnv_eeh_restore_vf_config(struct pci_dn *pdn)
1627 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1628 u32 devctl, cmd, cap2, aer_capctl;
1631 if (edev->pcie_cap) {
1633 old_mps = (ffs(pdn->mps) - 8) << 5;
1634 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
1636 devctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
1638 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
1641 /* Disable Completion Timeout */
1642 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP2,
1645 eeh_ops->read_config(pdn,
1646 edev->pcie_cap + PCI_EXP_DEVCTL2,
1649 eeh_ops->write_config(pdn,
1650 edev->pcie_cap + PCI_EXP_DEVCTL2,
1655 /* Enable SERR and parity checking */
1656 eeh_ops->read_config(pdn, PCI_COMMAND, 2, &cmd);
1657 cmd |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1658 eeh_ops->write_config(pdn, PCI_COMMAND, 2, cmd);
1660 /* Enable report various errors */
1661 if (edev->pcie_cap) {
1662 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
1664 devctl &= ~PCI_EXP_DEVCTL_CERE;
1665 devctl |= (PCI_EXP_DEVCTL_NFERE |
1666 PCI_EXP_DEVCTL_FERE |
1667 PCI_EXP_DEVCTL_URRE);
1668 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
1672 /* Enable ECRC generation and check */
1673 if (edev->pcie_cap && edev->aer_cap) {
1674 eeh_ops->read_config(pdn, edev->aer_cap + PCI_ERR_CAP,
1676 aer_capctl |= (PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
1677 eeh_ops->write_config(pdn, edev->aer_cap + PCI_ERR_CAP,
1684 static int pnv_eeh_restore_config(struct pci_dn *pdn)
1686 struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1687 struct pnv_phb *phb;
1694 * We have to restore the PCI config space after reset since the
1695 * firmware can't see SRIOV VFs.
1697 * FIXME: The MPS, error routing rules, timeout setting are worthy
1698 * to be exported by firmware in extendible way.
1701 ret = pnv_eeh_restore_vf_config(pdn);
1703 phb = edev->phb->private_data;
1704 ret = opal_pci_reinit(phb->opal_id,
1705 OPAL_REINIT_PCI_DEV, edev->config_addr);
1709 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n",
1710 __func__, edev->config_addr, ret);
1717 static struct eeh_ops pnv_eeh_ops = {
1719 .init = pnv_eeh_init,
1720 .post_init = pnv_eeh_post_init,
1721 .probe = pnv_eeh_probe,
1722 .set_option = pnv_eeh_set_option,
1723 .get_pe_addr = pnv_eeh_get_pe_addr,
1724 .get_state = pnv_eeh_get_state,
1725 .reset = pnv_eeh_reset,
1726 .wait_state = pnv_eeh_wait_state,
1727 .get_log = pnv_eeh_get_log,
1728 .configure_bridge = pnv_eeh_configure_bridge,
1729 .err_inject = pnv_eeh_err_inject,
1730 .read_config = pnv_eeh_read_config,
1731 .write_config = pnv_eeh_write_config,
1732 .next_error = pnv_eeh_next_error,
1733 .restore_config = pnv_eeh_restore_config
1736 void pcibios_bus_add_device(struct pci_dev *pdev)
1738 struct pci_dn *pdn = pci_get_pdn(pdev);
1740 if (!pdev->is_virtfn)
1744 * The following operations will fail if VF's sysfs files
1745 * aren't created or its resources aren't finalized.
1747 eeh_add_device_early(pdn);
1748 eeh_add_device_late(pdev);
1749 eeh_sysfs_add_device(pdev);
1752 #ifdef CONFIG_PCI_IOV
1753 static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev)
1755 struct pci_dn *pdn = pci_get_pdn(pdev);
1758 if (!pdev->is_virtfn)
1761 /* Synchronize MPS for VF and PF */
1762 parent_mps = pcie_get_mps(pdev->physfn);
1763 if ((128 << pdev->pcie_mpss) >= parent_mps)
1764 pcie_set_mps(pdev, parent_mps);
1765 pdn->mps = pcie_get_mps(pdev);
1767 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps);
1768 #endif /* CONFIG_PCI_IOV */
1771 * eeh_powernv_init - Register platform dependent EEH operations
1773 * EEH initialization on powernv platform. This function should be
1774 * called before any EEH related functions.
1776 static int __init eeh_powernv_init(void)
1780 eeh_set_pe_aux_size(PNV_PCI_DIAG_BUF_SIZE);
1781 ret = eeh_ops_register(&pnv_eeh_ops);
1783 pr_info("EEH: PowerNV platform initialized\n");
1785 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret);
1789 machine_early_initcall(powernv, eeh_powernv_init);