2 * Support for the interrupt controllers found on Power Macintosh,
3 * currently Apple's "Grand Central" interrupt controller in all
4 * it's incarnations. OpenPIC support used on newer machines is
7 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
8 * Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
18 #include <linux/stddef.h>
19 #include <linux/init.h>
20 #include <linux/sched.h>
21 #include <linux/signal.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/adb.h>
26 #include <linux/pmu.h>
28 #include <asm/sections.h>
32 #include <asm/pci-bridge.h>
34 #include <asm/pmac_feature.h>
48 /* Workaround flags for 32bit powermac machines */
49 unsigned int of_irq_workarounds;
50 struct device_node *of_irq_dflt_pic;
52 /* Default addresses */
53 static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
56 static int max_real_irqs;
58 static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
60 #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
61 static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
62 static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
63 static int pmac_irq_cascade = -1;
64 static struct irq_domain *pmac_pic_host;
66 static void __pmac_retrigger(unsigned int irq_nr)
68 if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) {
69 __set_bit(irq_nr, ppc_lost_interrupts);
70 irq_nr = pmac_irq_cascade;
73 if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
74 atomic_inc(&ppc_n_lost_interrupts);
79 static void pmac_mask_and_ack_irq(struct irq_data *d)
81 unsigned int src = irqd_to_hwirq(d);
82 unsigned long bit = 1UL << (src & 0x1f);
86 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
87 __clear_bit(src, ppc_cached_irq_mask);
88 if (__test_and_clear_bit(src, ppc_lost_interrupts))
89 atomic_dec(&ppc_n_lost_interrupts);
90 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
91 out_le32(&pmac_irq_hw[i]->ack, bit);
93 /* make sure ack gets to controller before we enable
96 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
97 != (ppc_cached_irq_mask[i] & bit));
98 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
101 static void pmac_ack_irq(struct irq_data *d)
103 unsigned int src = irqd_to_hwirq(d);
104 unsigned long bit = 1UL << (src & 0x1f);
108 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
109 if (__test_and_clear_bit(src, ppc_lost_interrupts))
110 atomic_dec(&ppc_n_lost_interrupts);
111 out_le32(&pmac_irq_hw[i]->ack, bit);
112 (void)in_le32(&pmac_irq_hw[i]->ack);
113 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
116 static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
118 unsigned long bit = 1UL << (irq_nr & 0x1f);
121 if ((unsigned)irq_nr >= max_irqs)
124 /* enable unmasked interrupts */
125 out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
128 /* make sure mask gets to controller before we
131 } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
132 != (ppc_cached_irq_mask[i] & bit));
135 * Unfortunately, setting the bit in the enable register
136 * when the device interrupt is already on *doesn't* set
137 * the bit in the flag register or request another interrupt.
139 if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
140 __pmac_retrigger(irq_nr);
143 /* When an irq gets requested for the first client, if it's an
144 * edge interrupt, we clear any previous one on the controller
146 static unsigned int pmac_startup_irq(struct irq_data *d)
149 unsigned int src = irqd_to_hwirq(d);
150 unsigned long bit = 1UL << (src & 0x1f);
153 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
154 if (!irqd_is_level_type(d))
155 out_le32(&pmac_irq_hw[i]->ack, bit);
156 __set_bit(src, ppc_cached_irq_mask);
157 __pmac_set_irq_mask(src, 0);
158 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
163 static void pmac_mask_irq(struct irq_data *d)
166 unsigned int src = irqd_to_hwirq(d);
168 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
169 __clear_bit(src, ppc_cached_irq_mask);
170 __pmac_set_irq_mask(src, 1);
171 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
174 static void pmac_unmask_irq(struct irq_data *d)
177 unsigned int src = irqd_to_hwirq(d);
179 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
180 __set_bit(src, ppc_cached_irq_mask);
181 __pmac_set_irq_mask(src, 0);
182 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
185 static int pmac_retrigger(struct irq_data *d)
189 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
190 __pmac_retrigger(irqd_to_hwirq(d));
191 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
195 static struct irq_chip pmac_pic = {
197 .irq_startup = pmac_startup_irq,
198 .irq_mask = pmac_mask_irq,
199 .irq_ack = pmac_ack_irq,
200 .irq_mask_ack = pmac_mask_and_ack_irq,
201 .irq_unmask = pmac_unmask_irq,
202 .irq_retrigger = pmac_retrigger,
205 static irqreturn_t gatwick_action(int cpl, void *dev_id)
211 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
212 for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
214 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
215 bits |= in_le32(&pmac_irq_hw[i]->level);
216 bits &= ppc_cached_irq_mask[i];
219 irq += __ilog2(bits);
220 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
221 generic_handle_irq(irq);
222 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
225 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
229 static unsigned int pmac_pic_get_irq(void)
232 unsigned long bits = 0;
235 #ifdef CONFIG_PPC_PMAC32_PSURGE
236 /* IPI's are a hack on the powersurge -- Cort */
237 if (smp_processor_id() != 0) {
238 return psurge_secondary_virq;
240 #endif /* CONFIG_PPC_PMAC32_PSURGE */
241 raw_spin_lock_irqsave(&pmac_pic_lock, flags);
242 for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
244 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
245 bits |= in_le32(&pmac_irq_hw[i]->level);
246 bits &= ppc_cached_irq_mask[i];
249 irq += __ilog2(bits);
252 raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
253 if (unlikely(irq < 0))
255 return irq_linear_revmap(pmac_pic_host, irq);
259 static struct irqaction xmon_action = {
266 static struct irqaction gatwick_cascade_action = {
267 .handler = gatwick_action,
271 static int pmac_pic_host_match(struct irq_domain *h, struct device_node *node)
273 /* We match all, we don't always have a node anyway */
277 static int pmac_pic_host_map(struct irq_domain *h, unsigned int virq,
283 /* Mark level interrupts, set delayed disable for edge ones and set
286 irq_set_status_flags(virq, IRQ_LEVEL);
287 irq_set_chip_and_handler(virq, &pmac_pic, handle_level_irq);
291 static int pmac_pic_host_xlate(struct irq_domain *h, struct device_node *ct,
292 const u32 *intspec, unsigned int intsize,
293 irq_hw_number_t *out_hwirq,
294 unsigned int *out_flags)
297 *out_flags = IRQ_TYPE_NONE;
298 *out_hwirq = *intspec;
302 static struct irq_domain_ops pmac_pic_host_ops = {
303 .match = pmac_pic_host_match,
304 .map = pmac_pic_host_map,
305 .xlate = pmac_pic_host_xlate,
308 static void __init pmac_pic_probe_oldstyle(void)
311 struct device_node *master = NULL;
312 struct device_node *slave = NULL;
316 /* Set our get_irq function */
317 ppc_md.get_irq = pmac_pic_get_irq;
320 * Find the interrupt controller type & node
323 if ((master = of_find_node_by_name(NULL, "gc")) != NULL) {
324 max_irqs = max_real_irqs = 32;
325 } else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) {
326 max_irqs = max_real_irqs = 32;
327 /* We might have a second cascaded ohare */
328 slave = of_find_node_by_name(NULL, "pci106b,7");
331 } else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) {
332 max_irqs = max_real_irqs = 64;
334 /* We might have a second cascaded heathrow */
335 slave = of_find_node_by_name(master, "mac-io");
337 /* Check ordering of master & slave */
338 if (of_device_is_compatible(master, "gatwick")) {
339 struct device_node *tmp;
340 BUG_ON(slave == NULL);
346 /* We found a slave */
350 BUG_ON(master == NULL);
353 * Allocate an irq host
355 pmac_pic_host = irq_domain_add_linear(master, max_irqs,
356 &pmac_pic_host_ops, NULL);
357 BUG_ON(pmac_pic_host == NULL);
358 irq_set_default_host(pmac_pic_host);
360 /* Get addresses of first controller if we have a node for it */
361 BUG_ON(of_address_to_resource(master, 0, &r));
363 /* Map interrupts of primary controller */
364 addr = (u8 __iomem *) ioremap(r.start, 0x40);
366 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
368 if (max_real_irqs > 32)
369 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
373 printk(KERN_INFO "irq: Found primary Apple PIC %s for %d irqs\n",
374 master->full_name, max_real_irqs);
376 /* Map interrupts of cascaded controller */
377 if (slave && !of_address_to_resource(slave, 0, &r)) {
378 addr = (u8 __iomem *)ioremap(r.start, 0x40);
379 pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
383 (volatile struct pmac_irq_hw __iomem *)
385 pmac_irq_cascade = irq_of_parse_and_map(slave, 0);
387 printk(KERN_INFO "irq: Found slave Apple PIC %s for %d irqs"
388 " cascade: %d\n", slave->full_name,
389 max_irqs - max_real_irqs, pmac_irq_cascade);
393 /* Disable all interrupts in all controllers */
394 for (i = 0; i * 32 < max_irqs; ++i)
395 out_le32(&pmac_irq_hw[i]->enable, 0);
397 /* Hookup cascade irq */
398 if (slave && pmac_irq_cascade != NO_IRQ)
399 setup_irq(pmac_irq_cascade, &gatwick_cascade_action);
401 printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs);
403 setup_irq(irq_create_mapping(NULL, 20), &xmon_action);
407 int of_irq_map_oldworld(struct device_node *device, int index,
408 struct of_irq *out_irq)
410 const u32 *ints = NULL;
414 * Old machines just have a list of interrupt numbers
415 * and no interrupt-controller nodes. We also have dodgy
416 * cases where the APPL,interrupts property is completely
417 * missing behind pci-pci bridges and we have to get it
418 * from the parent (the bridge itself, as apple just wired
419 * everything together on these)
422 ints = of_get_property(device, "AAPL,interrupts", &intlen);
425 device = device->parent;
426 if (device && strcmp(device->type, "pci") != 0)
431 intlen /= sizeof(u32);
436 out_irq->controller = NULL;
437 out_irq->specifier[0] = ints[index];
442 #endif /* CONFIG_PPC32 */
444 static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
446 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
447 struct device_node* pswitch;
450 pswitch = of_find_node_by_name(NULL, "programmer-switch");
452 nmi_irq = irq_of_parse_and_map(pswitch, 0);
453 if (nmi_irq != NO_IRQ) {
454 mpic_irq_set_priority(nmi_irq, 9);
455 setup_irq(nmi_irq, &xmon_action);
457 of_node_put(pswitch);
459 #endif /* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
462 static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
465 const char *name = master ? " MPIC 1 " : " MPIC 2 ";
467 unsigned int flags = master ? 0 : MPIC_SECONDARY;
469 pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
471 flags |= MPIC_WANTS_RESET;
472 if (of_get_property(np, "big-endian", NULL))
473 flags |= MPIC_BIG_ENDIAN;
475 /* Primary Big Endian means HT interrupts. This is quite dodgy
476 * but works until I find a better way
478 if (master && (flags & MPIC_BIG_ENDIAN))
479 flags |= MPIC_U3_HT_IRQS;
481 mpic = mpic_alloc(np, 0, flags, 0, 0, name);
490 static int __init pmac_pic_probe_mpic(void)
492 struct mpic *mpic1, *mpic2;
493 struct device_node *np, *master = NULL, *slave = NULL;
495 /* We can have up to 2 MPICs cascaded */
496 for (np = NULL; (np = of_find_node_by_type(np, "open-pic"))
498 if (master == NULL &&
499 of_get_property(np, "interrupts", NULL) == NULL)
500 master = of_node_get(np);
501 else if (slave == NULL)
502 slave = of_node_get(np);
507 /* Check for bogus setups */
508 if (master == NULL && slave != NULL) {
513 /* Not found, default to good old pmac pic */
517 /* Set master handler */
518 ppc_md.get_irq = mpic_get_irq;
521 mpic1 = pmac_setup_one_mpic(master, 1);
522 BUG_ON(mpic1 == NULL);
524 /* Install NMI if any */
525 pmac_pic_setup_mpic_nmi(mpic1);
529 /* Set up a cascaded controller, if present */
531 mpic2 = pmac_setup_one_mpic(slave, 0);
533 printk(KERN_ERR "Failed to setup slave MPIC\n");
541 void __init pmac_pic_init(void)
543 /* We configure the OF parsing based on our oldworld vs. newworld
544 * platform type and wether we were booted by BootX.
548 of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC;
549 if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL)
550 of_irq_workarounds |= OF_IMAP_NO_PHANDLE;
552 /* If we don't have phandles on a newworld, then try to locate a
553 * default interrupt controller (happens when booting with BootX).
554 * We do a first match here, hopefully, that only ever happens on
555 * machines with one controller.
557 if (pmac_newworld && (of_irq_workarounds & OF_IMAP_NO_PHANDLE)) {
558 struct device_node *np;
560 for_each_node_with_property(np, "interrupt-controller") {
561 /* Skip /chosen/interrupt-controller */
562 if (strcmp(np->name, "chosen") == 0)
564 /* It seems like at least one person wants
565 * to use BootX on a machine with an AppleKiwi
566 * controller which happens to pretend to be an
567 * interrupt controller too. */
568 if (strcmp(np->name, "AppleKiwi") == 0)
570 /* I think we found one ! */
571 of_irq_dflt_pic = np;
575 #endif /* CONFIG_PPC32 */
577 /* We first try to detect Apple's new Core99 chipset, since mac-io
578 * is quite different on those machines and contains an IBM MPIC2.
580 if (pmac_pic_probe_mpic() == 0)
584 pmac_pic_probe_oldstyle();
588 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
590 * These procedures are used in implementing sleep on the powerbooks.
591 * sleep_save_intrs() saves the states of all interrupt enables
592 * and disables all interrupts except for the nominated one.
593 * sleep_restore_intrs() restores the states of all interrupt enables.
595 unsigned long sleep_save_mask[2];
597 /* This used to be passed by the PMU driver but that link got
598 * broken with the new driver model. We use this tweak for now...
599 * We really want to do things differently though...
601 static int pmacpic_find_viaint(void)
605 #ifdef CONFIG_ADB_PMU
606 struct device_node *np;
608 if (pmu_get_model() != PMU_OHARE_BASED)
610 np = of_find_node_by_name(NULL, "via-pmu");
613 viaint = irq_of_parse_and_map(np, 0);
616 #endif /* CONFIG_ADB_PMU */
620 static int pmacpic_suspend(void)
622 int viaint = pmacpic_find_viaint();
624 sleep_save_mask[0] = ppc_cached_irq_mask[0];
625 sleep_save_mask[1] = ppc_cached_irq_mask[1];
626 ppc_cached_irq_mask[0] = 0;
627 ppc_cached_irq_mask[1] = 0;
629 set_bit(viaint, ppc_cached_irq_mask);
630 out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
631 if (max_real_irqs > 32)
632 out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
633 (void)in_le32(&pmac_irq_hw[0]->event);
634 /* make sure mask gets to controller before we return to caller */
636 (void)in_le32(&pmac_irq_hw[0]->enable);
641 static void pmacpic_resume(void)
645 out_le32(&pmac_irq_hw[0]->enable, 0);
646 if (max_real_irqs > 32)
647 out_le32(&pmac_irq_hw[1]->enable, 0);
649 for (i = 0; i < max_real_irqs; ++i)
650 if (test_bit(i, sleep_save_mask))
651 pmac_unmask_irq(irq_get_irq_data(i));
654 static struct syscore_ops pmacpic_syscore_ops = {
655 .suspend = pmacpic_suspend,
656 .resume = pmacpic_resume,
659 static int __init init_pmacpic_syscore(void)
662 register_syscore_ops(&pmacpic_syscore_ops);
666 machine_subsys_initcall(powermac, init_pmacpic_syscore);
668 #endif /* CONFIG_PM && CONFIG_PPC32 */