2 * Support for PCI bridges found on Power Macintoshes.
4 * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org)
5 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/delay.h>
16 #include <linux/string.h>
17 #include <linux/init.h>
18 #include <linux/irq.h>
19 #include <linux/of_pci.h>
21 #include <asm/sections.h>
24 #include <asm/pci-bridge.h>
25 #include <asm/machdep.h>
26 #include <asm/pmac_feature.h>
27 #include <asm/grackle.h>
28 #include <asm/ppc-pci.h>
35 #define DBG(x...) printk(x)
40 /* XXX Could be per-controller, but I don't think we risk anything by
41 * assuming we won't have both UniNorth and Bandit */
42 static int has_uninorth;
44 static struct pci_controller *u3_agp;
46 static int has_second_ohare;
47 #endif /* CONFIG_PPC64 */
49 extern int pcibios_assign_bus_offset;
51 struct device_node *k2_skiplist[2];
54 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
56 #define BANDIT_DEVID_2 8
57 #define BANDIT_REVID 3
59 #define BANDIT_DEVNUM 11
60 #define BANDIT_MAGIC 0x50
61 #define BANDIT_COHERENT 0x40
63 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
65 for (; node; node = node->sibling) {
66 const int * bus_range;
67 const unsigned int *class_code;
70 /* For PCI<->PCI bridges or CardBus bridges, we go down */
71 class_code = of_get_property(node, "class-code", NULL);
72 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
73 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
75 bus_range = of_get_property(node, "bus-range", &len);
76 if (bus_range != NULL && len > 2 * sizeof(int)) {
77 if (bus_range[1] > higher)
78 higher = bus_range[1];
80 higher = fixup_one_level_bus_range(node->child, higher);
85 /* This routine fixes the "bus-range" property of all bridges in the
86 * system since they tend to have their "last" member wrong on macs
88 * Note that the bus numbers manipulated here are OF bus numbers, they
89 * are not Linux bus numbers.
91 static void __init fixup_bus_range(struct device_node *bridge)
94 struct property *prop;
96 /* Lookup the "bus-range" property for the hose */
97 prop = of_find_property(bridge, "bus-range", &len);
98 if (prop == NULL || prop->length < 2 * sizeof(int))
101 bus_range = prop->value;
102 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
106 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
108 * The "Bandit" version is present in all early PCI PowerMacs,
109 * and up to the first ones using Grackle. Some machines may
110 * have 2 bandit controllers (2 PCI busses).
112 * "Chaos" is used in some "Bandit"-type machines as a bridge
113 * for the separate display bus. It is accessed the same
114 * way as bandit, but cannot be probed for devices. It therefore
115 * has its own config access functions.
117 * The "UniNorth" version is present in all Core99 machines
118 * (iBook, G4, new IMacs, and all the recent Apple machines).
119 * It contains 3 controllers in one ASIC.
121 * The U3 is the bridge used on G5 machines. It contains an
122 * AGP bus which is dealt with the old UniNorth access routines
123 * and a HyperTransport bus which uses its own set of access
127 #define MACRISC_CFA0(devfn, off) \
128 ((1 << (unsigned int)PCI_SLOT(dev_fn)) \
129 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
130 | (((unsigned int)(off)) & 0xFCUL))
132 #define MACRISC_CFA1(bus, devfn, off) \
133 ((((unsigned int)(bus)) << 16) \
134 |(((unsigned int)(devfn)) << 8) \
135 |(((unsigned int)(off)) & 0xFCUL) \
138 static void __iomem *macrisc_cfg_map_bus(struct pci_bus *bus,
143 struct pci_controller *hose;
145 hose = pci_bus_to_host(bus);
149 if (bus->number == hose->first_busno) {
150 if (dev_fn < (11 << 3))
152 caddr = MACRISC_CFA0(dev_fn, offset);
154 caddr = MACRISC_CFA1(bus->number, dev_fn, offset);
156 /* Uninorth will return garbage if we don't read back the value ! */
158 out_le32(hose->cfg_addr, caddr);
159 } while (in_le32(hose->cfg_addr) != caddr);
161 offset &= has_uninorth ? 0x07 : 0x03;
162 return hose->cfg_data + offset;
165 static struct pci_ops macrisc_pci_ops =
167 .map_bus = macrisc_cfg_map_bus,
168 .read = pci_generic_config_read,
169 .write = pci_generic_config_write,
174 * Verify that a specific (bus, dev_fn) exists on chaos
176 static void __iomem *chaos_map_bus(struct pci_bus *bus, unsigned int devfn,
179 struct device_node *np;
180 const u32 *vendor, *device;
184 np = of_pci_find_child_device(bus->dev.of_node, devfn);
188 vendor = of_get_property(np, "vendor-id", NULL);
189 device = of_get_property(np, "device-id", NULL);
190 if (vendor == NULL || device == NULL)
193 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10)
194 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24))
197 return macrisc_cfg_map_bus(bus, devfn, offset);
200 static struct pci_ops chaos_pci_ops =
202 .map_bus = chaos_map_bus,
203 .read = pci_generic_config_read,
204 .write = pci_generic_config_write,
207 static void __init setup_chaos(struct pci_controller *hose,
208 struct resource *addr)
210 /* assume a `chaos' bridge */
211 hose->ops = &chaos_pci_ops;
212 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
213 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
215 #endif /* CONFIG_PPC32 */
219 * These versions of U3 HyperTransport config space access ops do not
220 * implement self-view of the HT host yet
224 * This function deals with some "special cases" devices.
226 * 0 -> No special case
227 * 1 -> Skip the device but act as if the access was successful
228 * (return 0xff's on reads, eventually, cache config space
229 * accesses in a later version)
230 * -1 -> Hide the device (unsuccessful access)
232 static int u3_ht_skip_device(struct pci_controller *hose,
233 struct pci_bus *bus, unsigned int devfn)
235 struct device_node *busdn, *dn;
238 /* We only allow config cycles to devices that are in OF device-tree
239 * as we are apparently having some weird things going on with some
240 * revs of K2 on recent G5s, except for the host bridge itself, which
241 * is missing from the tree but we know we can probe.
244 busdn = pci_device_to_OF_node(bus->self);
249 for (dn = busdn->child; dn; dn = dn->sibling)
250 if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn)
256 * When a device in K2 is powered down, we die on config
257 * cycle accesses. Fix that here.
260 if (k2_skiplist[i] == dn)
266 #define U3_HT_CFA0(devfn, off) \
267 ((((unsigned int)devfn) << 8) | offset)
268 #define U3_HT_CFA1(bus, devfn, off) \
269 (U3_HT_CFA0(devfn, off) \
270 + (((unsigned int)bus) << 16) \
273 static void __iomem *u3_ht_cfg_access(struct pci_controller *hose, u8 bus,
274 u8 devfn, u8 offset, int *swap)
277 if (bus == hose->first_busno) {
279 return hose->cfg_data + U3_HT_CFA0(devfn, offset);
281 return ((void __iomem *)hose->cfg_addr) + (offset << 2);
283 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset);
286 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
287 int offset, int len, u32 *val)
289 struct pci_controller *hose;
293 hose = pci_bus_to_host(bus);
295 return PCIBIOS_DEVICE_NOT_FOUND;
297 return PCIBIOS_BAD_REGISTER_NUMBER;
298 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap);
300 return PCIBIOS_DEVICE_NOT_FOUND;
302 switch (u3_ht_skip_device(hose, bus, devfn)) {
310 *val = 0xffff; break;
312 *val = 0xfffffffful; break;
314 return PCIBIOS_SUCCESSFUL;
316 return PCIBIOS_DEVICE_NOT_FOUND;
320 * Note: the caller has already checked that offset is
321 * suitably aligned and that len is 1, 2 or 4.
328 *val = swap ? in_le16(addr) : in_be16(addr);
331 *val = swap ? in_le32(addr) : in_be32(addr);
334 return PCIBIOS_SUCCESSFUL;
337 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
338 int offset, int len, u32 val)
340 struct pci_controller *hose;
344 hose = pci_bus_to_host(bus);
346 return PCIBIOS_DEVICE_NOT_FOUND;
348 return PCIBIOS_BAD_REGISTER_NUMBER;
349 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap);
351 return PCIBIOS_DEVICE_NOT_FOUND;
353 switch (u3_ht_skip_device(hose, bus, devfn)) {
357 return PCIBIOS_SUCCESSFUL;
359 return PCIBIOS_DEVICE_NOT_FOUND;
363 * Note: the caller has already checked that offset is
364 * suitably aligned and that len is 1, 2 or 4.
371 swap ? out_le16(addr, val) : out_be16(addr, val);
374 swap ? out_le32(addr, val) : out_be32(addr, val);
377 return PCIBIOS_SUCCESSFUL;
380 static struct pci_ops u3_ht_pci_ops =
382 .read = u3_ht_read_config,
383 .write = u3_ht_write_config,
386 #define U4_PCIE_CFA0(devfn, off) \
387 ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \
388 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \
389 | ((((unsigned int)(off)) >> 8) << 28) \
390 | (((unsigned int)(off)) & 0xfcU))
392 #define U4_PCIE_CFA1(bus, devfn, off) \
393 ((((unsigned int)(bus)) << 16) \
394 |(((unsigned int)(devfn)) << 8) \
395 | ((((unsigned int)(off)) >> 8) << 28) \
396 |(((unsigned int)(off)) & 0xfcU) \
399 static void __iomem *u4_pcie_cfg_map_bus(struct pci_bus *bus,
403 struct pci_controller *hose;
406 if (offset >= 0x1000)
409 hose = pci_bus_to_host(bus);
413 if (bus->number == hose->first_busno) {
414 caddr = U4_PCIE_CFA0(dev_fn, offset);
416 caddr = U4_PCIE_CFA1(bus->number, dev_fn, offset);
418 /* Uninorth will return garbage if we don't read back the value ! */
420 out_le32(hose->cfg_addr, caddr);
421 } while (in_le32(hose->cfg_addr) != caddr);
424 return hose->cfg_data + offset;
427 static struct pci_ops u4_pcie_pci_ops =
429 .map_bus = u4_pcie_cfg_map_bus,
430 .read = pci_generic_config_read,
431 .write = pci_generic_config_write,
434 static void pmac_pci_fixup_u4_of_node(struct pci_dev *dev)
436 /* Apple's device-tree "hides" the root complex virtual P2P bridge
437 * on U4. However, Linux sees it, causing the PCI <-> OF matching
438 * code to fail to properly match devices below it. This works around
439 * it by setting the node of the bridge to point to the PHB node,
440 * which is not entirely correct but fixes the matching code and
441 * doesn't break anything else. It's also the simplest possible fix.
443 if (dev->dev.of_node == NULL)
444 dev->dev.of_node = pcibios_get_phb_of_node(dev->bus);
446 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, 0x5b, pmac_pci_fixup_u4_of_node);
448 #endif /* CONFIG_PPC64 */
452 * For a bandit bridge, turn on cache coherency if necessary.
453 * N.B. we could clean this up using the hose ops directly.
455 static void __init init_bandit(struct pci_controller *bp)
457 unsigned int vendev, magic;
460 /* read the word at offset 0 in config space for device 11 */
461 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID);
463 vendev = in_le32(bp->cfg_data);
464 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) +
465 PCI_VENDOR_ID_APPLE) {
466 /* read the revision id */
467 out_le32(bp->cfg_addr,
468 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID);
470 rev = in_8(bp->cfg_data);
471 if (rev != BANDIT_REVID)
473 "Unknown revision %d for bandit\n", rev);
474 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) {
475 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev);
479 /* read the word at offset 0x50 */
480 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC);
482 magic = in_le32(bp->cfg_data);
483 if ((magic & BANDIT_COHERENT) != 0)
485 magic |= BANDIT_COHERENT;
487 out_le32(bp->cfg_data, magic);
488 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n");
492 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
494 static void __init init_p2pbridge(void)
496 struct device_node *p2pbridge;
497 struct pci_controller* hose;
501 /* XXX it would be better here to identify the specific
502 PCI-PCI bridge chip we have. */
503 p2pbridge = of_find_node_by_name(NULL, "pci-bridge");
504 if (p2pbridge == NULL || !of_node_name_eq(p2pbridge->parent, "pci"))
506 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) {
507 DBG("Can't find PCI infos for PCI<->PCI bridge\n");
510 /* Warning: At this point, we have not yet renumbered all busses.
511 * So we must use OF walking to find out hose
513 hose = pci_find_hose_for_OF_device(p2pbridge);
515 DBG("Can't find hose for PCI<->PCI bridge\n");
518 if (early_read_config_word(hose, bus, devfn,
519 PCI_BRIDGE_CONTROL, &val) < 0) {
520 printk(KERN_ERR "init_p2pbridge: couldn't read bridge"
524 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT;
525 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val);
527 of_node_put(p2pbridge);
530 static void __init init_second_ohare(void)
532 struct device_node *np = of_find_node_by_name(NULL, "pci106b,7");
533 unsigned char bus, devfn;
539 /* This must run before we initialize the PICs since the second
540 * ohare hosts a PIC that will be accessed there.
542 if (pci_device_from_OF_node(np, &bus, &devfn) == 0) {
543 struct pci_controller* hose =
544 pci_find_hose_for_OF_device(np);
546 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n");
550 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd);
551 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
552 cmd &= ~PCI_COMMAND_IO;
553 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd);
555 has_second_ohare = 1;
560 * Some Apple desktop machines have a NEC PD720100A USB2 controller
561 * on the motherboard. Open Firmware, on these, will disable the
562 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
563 * code re-enables it ;)
565 static void __init fixup_nec_usb2(void)
567 struct device_node *nec;
569 for_each_node_by_name(nec, "usb") {
570 struct pci_controller *hose;
575 prop = of_get_property(nec, "vendor-id", NULL);
580 prop = of_get_property(nec, "device-id", NULL);
585 prop = of_get_property(nec, "reg", NULL);
588 devfn = (prop[0] >> 8) & 0xff;
589 bus = (prop[0] >> 16) & 0xff;
590 if (PCI_FUNC(devfn) != 0)
592 hose = pci_find_hose_for_OF_device(nec);
595 early_read_config_dword(hose, bus, devfn, 0xe4, &data);
597 printk("Found NEC PD720100A USB2 chip with disabled"
598 " EHCI, fixing up...\n");
600 early_write_config_dword(hose, bus, devfn, 0xe4, data);
605 static void __init setup_bandit(struct pci_controller *hose,
606 struct resource *addr)
608 hose->ops = ¯isc_pci_ops;
609 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
610 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
614 static int __init setup_uninorth(struct pci_controller *hose,
615 struct resource *addr)
617 pci_add_flags(PCI_REASSIGN_ALL_BUS);
619 hose->ops = ¯isc_pci_ops;
620 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000);
621 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000);
622 /* We "know" that the bridge at f2000000 has the PCI slots. */
623 return addr->start == 0xf2000000;
625 #endif /* CONFIG_PPC32 */
628 static void __init setup_u3_agp(struct pci_controller* hose)
630 /* On G5, we move AGP up to high bus number so we don't need
631 * to reassign bus numbers for HT. If we ever have P2P bridges
632 * on AGP, we'll have to move pci_assign_all_busses to the
633 * pci_controller structure so we enable it for AGP and not for
635 * We hard code the address because of the different size of
636 * the reg address cell, we shall fix that by killing struct
637 * reg_property and using some accessor functions instead
639 hose->first_busno = 0xf0;
640 hose->last_busno = 0xff;
642 hose->ops = ¯isc_pci_ops;
643 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
644 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
648 static void __init setup_u4_pcie(struct pci_controller* hose)
650 /* We currently only implement the "non-atomic" config space, to
651 * be optimised later.
653 hose->ops = &u4_pcie_pci_ops;
654 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
655 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
657 /* The bus contains a bridge from root -> device, we need to
658 * make it visible on bus 0 so that we pick the right type
659 * of config cycles. If we didn't, we would have to force all
660 * config cycles to be type 1. So we override the "bus-range"
663 hose->first_busno = 0x00;
664 hose->last_busno = 0xff;
667 static void __init parse_region_decode(struct pci_controller *hose,
670 unsigned long base, end, next = -1;
673 /* Iterate through all bits. We ignore the last bit as this region is
674 * reserved for the ROM among other niceties
676 for (i = 0; i < 31; i++) {
677 if ((decode & (0x80000000 >> i)) == 0)
680 base = 0xf0000000 | (((u32)i) << 24);
681 end = base + 0x00ffffff;
683 base = ((u32)i-16) << 28;
684 end = base + 0x0fffffff;
688 printk(KERN_WARNING "PCI: Too many ranges !\n");
691 hose->mem_resources[cur].flags = IORESOURCE_MEM;
692 hose->mem_resources[cur].name = hose->dn->full_name;
693 hose->mem_resources[cur].start = base;
694 hose->mem_resources[cur].end = end;
695 hose->mem_offset[cur] = 0;
696 DBG(" %d: 0x%08lx-0x%08lx\n", cur, base, end);
698 DBG(" : -0x%08lx\n", end);
699 hose->mem_resources[cur].end = end;
705 static void __init setup_u3_ht(struct pci_controller* hose)
707 struct device_node *np = hose->dn;
708 struct resource cfg_res, self_res;
711 hose->ops = &u3_ht_pci_ops;
713 /* Get base addresses from OF tree
715 if (of_address_to_resource(np, 0, &cfg_res) ||
716 of_address_to_resource(np, 1, &self_res)) {
717 printk(KERN_ERR "PCI: Failed to get U3/U4 HT resources !\n");
721 /* Map external cfg space access into cfg_data and self registers
724 hose->cfg_data = ioremap(cfg_res.start, 0x02000000);
725 hose->cfg_addr = ioremap(self_res.start, resource_size(&self_res));
728 * /ht node doesn't expose a "ranges" property, we read the register
729 * that controls the decoding logic and use that for memory regions.
730 * The IO region is hard coded since it is fixed in HW as well.
732 hose->io_base_phys = 0xf4000000;
733 hose->pci_io_size = 0x00400000;
734 hose->io_resource.name = np->full_name;
735 hose->io_resource.start = 0;
736 hose->io_resource.end = 0x003fffff;
737 hose->io_resource.flags = IORESOURCE_IO;
738 hose->first_busno = 0;
739 hose->last_busno = 0xef;
741 /* Note: fix offset when cfg_addr becomes a void * */
742 decode = in_be32(hose->cfg_addr + 0x80);
744 DBG("PCI: Apple HT bridge decode register: 0x%08x\n", decode);
746 /* NOTE: The decode register setup is a bit weird... region
747 * 0xf8000000 for example is marked as enabled in there while it's
748 & actually the memory controller registers.
749 * That means that we are incorrectly attributing it to HT.
751 * In a similar vein, region 0xf4000000 is actually the HT IO space but
752 * also marked as enabled in here and 0xf9000000 is used by some other
753 * internal bits of the northbridge.
755 * Unfortunately, we can't just mask out those bit as we would end
756 * up with more regions than we can cope (linux can only cope with
757 * 3 memory regions for a PHB at this stage).
759 * So for now, we just do a little hack. We happen to -know- that
760 * Apple firmware doesn't assign things below 0xfa000000 for that
761 * bridge anyway so we mask out all bits we don't want.
763 decode &= 0x003fffff;
765 /* Now parse the resulting bits and build resources */
766 parse_region_decode(hose, decode);
768 #endif /* CONFIG_PPC64 */
771 * We assume that if we have a G3 powermac, we have one bridge called
772 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
773 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
775 static int __init pmac_add_bridge(struct device_node *dev)
778 struct pci_controller *hose;
779 struct resource rsrc;
781 const int *bus_range;
784 DBG("Adding PCI host bridge %pOF\n", dev);
786 /* Fetch host bridge registers address */
787 of_address_to_resource(dev, 0, &rsrc);
789 /* Get bus range if any */
790 bus_range = of_get_property(dev, "bus-range", &len);
791 if (bus_range == NULL || len < 2 * sizeof(int)) {
792 printk(KERN_WARNING "Can't get bus-range for %pOF, assume"
796 hose = pcibios_alloc_controller(dev);
799 hose->first_busno = bus_range ? bus_range[0] : 0;
800 hose->last_busno = bus_range ? bus_range[1] : 0xff;
801 hose->controller_ops = pmac_pci_controller_ops;
805 /* 64 bits only bridges */
807 if (of_device_is_compatible(dev, "u3-agp")) {
809 disp_name = "U3-AGP";
811 } else if (of_device_is_compatible(dev, "u3-ht")) {
815 } else if (of_device_is_compatible(dev, "u4-pcie")) {
817 disp_name = "U4-PCIE";
820 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:"
821 " %d->%d\n", disp_name, hose->first_busno, hose->last_busno);
822 #endif /* CONFIG_PPC64 */
824 /* 32 bits only bridges */
826 if (of_device_is_compatible(dev, "uni-north")) {
827 primary = setup_uninorth(hose, &rsrc);
828 disp_name = "UniNorth";
829 } else if (of_node_name_eq(dev, "pci")) {
830 /* XXX assume this is a mpc106 (grackle) */
832 disp_name = "Grackle (MPC106)";
833 } else if (of_node_name_eq(dev, "bandit")) {
834 setup_bandit(hose, &rsrc);
835 disp_name = "Bandit";
836 } else if (of_node_name_eq(dev, "chaos")) {
837 setup_chaos(hose, &rsrc);
841 printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. "
842 "Firmware bus number: %d->%d\n",
843 disp_name, (unsigned long long)rsrc.start, hose->first_busno,
845 #endif /* CONFIG_PPC32 */
847 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
848 hose, hose->cfg_addr, hose->cfg_data);
850 /* Interpret the "ranges" property */
851 /* This also maps the I/O region and sets isa_io/mem_base */
852 pci_process_bridge_OF_ranges(hose, dev, primary);
854 /* Fixup "bus-range" OF property */
855 fixup_bus_range(dev);
860 void pmac_pci_irq_fixup(struct pci_dev *dev)
863 /* Fixup interrupt for the modem/ethernet combo controller.
864 * on machines with a second ohare chip.
865 * The number in the device tree (27) is bogus (correct for
866 * the ethernet-only board but not the combo ethernet/modem
867 * board). The real interrupt is 28 on the second controller
870 if (has_second_ohare &&
871 dev->vendor == PCI_VENDOR_ID_DEC &&
872 dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) {
873 dev->irq = irq_create_mapping(NULL, 60);
874 irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
876 #endif /* CONFIG_PPC32 */
880 static int pmac_pci_root_bridge_prepare(struct pci_host_bridge *bridge)
882 struct pci_controller *hose = pci_bus_to_host(bridge->bus);
883 struct device_node *np, *child;
888 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
889 * assume there is no P2P bridge on the AGP bus, which should be a
890 * safe assumptions for now. We should do something better in the
894 PCI_DN(np)->busno = 0xf0;
895 for_each_child_of_node(np, child)
896 PCI_DN(child)->busno = 0xf0;
900 #endif /* CONFIG_PPC64 */
902 void __init pmac_pci_init(void)
904 struct device_node *np, *root;
905 struct device_node *ht __maybe_unused = NULL;
907 pci_set_flags(PCI_CAN_SKIP_ISA_ALIGN);
909 root = of_find_node_by_path("/");
911 printk(KERN_CRIT "pmac_pci_init: can't find root "
915 for_each_child_of_node(root, np) {
916 if (of_node_name_eq(np, "bandit")
917 || of_node_name_eq(np, "chaos")
918 || of_node_name_eq(np, "pci")) {
919 if (pmac_add_bridge(np) == 0)
922 if (of_node_name_eq(np, "ht")) {
930 /* Probe HT last as it relies on the agp resources to be already
933 if (ht && pmac_add_bridge(ht) != 0)
936 ppc_md.pcibios_root_bridge_prepare = pmac_pci_root_bridge_prepare;
937 /* pmac_check_ht_link(); */
939 #else /* CONFIG_PPC64 */
944 /* We are still having some issues with the Xserve G4, enabling
945 * some offset between bus number and domains for now when we
946 * assign all busses should help for now
948 if (pci_has_flag(PCI_REASSIGN_ALL_BUS))
949 pcibios_assign_bus_offset = 0x10;
954 static bool pmac_pci_enable_device_hook(struct pci_dev *dev)
956 struct device_node* node;
960 node = pci_device_to_OF_node(dev);
962 /* We don't want to enable USB controllers absent from the OF tree
963 * (iBook second controller)
965 if (dev->vendor == PCI_VENDOR_ID_APPLE
966 && dev->class == PCI_CLASS_SERIAL_USB_OHCI
968 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n",
976 uninorth_child = node->parent &&
977 of_device_is_compatible(node->parent, "uni-north");
979 /* Firewire & GMAC were disabled after PCI probe, the driver is
980 * claiming them, we must re-enable them now.
982 if (uninorth_child && of_node_name_eq(node, "firewire") &&
983 (of_device_is_compatible(node, "pci106b,18") ||
984 of_device_is_compatible(node, "pci106b,30") ||
985 of_device_is_compatible(node, "pci11c1,5811"))) {
986 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1);
987 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1);
990 if (uninorth_child && of_node_name_eq(node, "ethernet") &&
991 of_device_is_compatible(node, "gmac")) {
992 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1);
997 * Fixup various header fields on 32 bits. We don't do that on
998 * 64 bits as some of these have strange values behind the HT
999 * bridge and we must not, for example, enable MWI or set the
1000 * cache line size on them.
1005 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1006 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
1007 | PCI_COMMAND_INVALIDATE;
1008 pci_write_config_word(dev, PCI_COMMAND, cmd);
1009 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16);
1011 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
1012 L1_CACHE_BYTES >> 2);
1018 static void pmac_pci_fixup_ohci(struct pci_dev *dev)
1020 struct device_node *node = pci_device_to_OF_node(dev);
1022 /* We don't want to assign resources to USB controllers
1023 * absent from the OF tree (iBook second controller)
1025 if (dev->class == PCI_CLASS_SERIAL_USB_OHCI && !node)
1026 dev->resource[0].flags = 0;
1028 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_ANY_ID, pmac_pci_fixup_ohci);
1030 /* We power down some devices after they have been probed. They'll
1031 * be powered back on later on
1033 void __init pmac_pcibios_after_init(void)
1035 struct device_node* nd;
1037 for_each_node_by_name(nd, "firewire") {
1038 if (nd->parent && (of_device_is_compatible(nd, "pci106b,18") ||
1039 of_device_is_compatible(nd, "pci106b,30") ||
1040 of_device_is_compatible(nd, "pci11c1,5811"))
1041 && of_device_is_compatible(nd->parent, "uni-north")) {
1042 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0);
1043 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0);
1046 for_each_node_by_name(nd, "ethernet") {
1047 if (nd->parent && of_device_is_compatible(nd, "gmac")
1048 && of_device_is_compatible(nd->parent, "uni-north"))
1049 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0);
1053 static void pmac_pci_fixup_cardbus(struct pci_dev *dev)
1055 if (!machine_is(powermac))
1058 * Fix the interrupt routing on the various cardbus bridges
1059 * used on powerbooks
1061 if (dev->vendor != PCI_VENDOR_ID_TI)
1063 if (dev->device == PCI_DEVICE_ID_TI_1130 ||
1064 dev->device == PCI_DEVICE_ID_TI_1131) {
1066 /* Enable PCI interrupt */
1067 if (pci_read_config_byte(dev, 0x91, &val) == 0)
1068 pci_write_config_byte(dev, 0x91, val | 0x30);
1069 /* Disable ISA interrupt mode */
1070 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1071 pci_write_config_byte(dev, 0x92, val & ~0x06);
1073 if (dev->device == PCI_DEVICE_ID_TI_1210 ||
1074 dev->device == PCI_DEVICE_ID_TI_1211 ||
1075 dev->device == PCI_DEVICE_ID_TI_1410 ||
1076 dev->device == PCI_DEVICE_ID_TI_1510) {
1078 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1079 signal out the MFUNC0 pin */
1080 if (pci_read_config_byte(dev, 0x8c, &val) == 0)
1081 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2);
1082 /* Disable ISA interrupt mode */
1083 if (pci_read_config_byte(dev, 0x92, &val) == 0)
1084 pci_write_config_byte(dev, 0x92, val & ~0x06);
1088 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus);
1090 static void pmac_pci_fixup_pciata(struct pci_dev *dev)
1095 * On PowerMacs, we try to switch any PCI ATA controller to
1098 if (!machine_is(powermac))
1101 /* Some controllers don't have the class IDE */
1102 if (dev->vendor == PCI_VENDOR_ID_PROMISE)
1103 switch(dev->device) {
1104 case PCI_DEVICE_ID_PROMISE_20246:
1105 case PCI_DEVICE_ID_PROMISE_20262:
1106 case PCI_DEVICE_ID_PROMISE_20263:
1107 case PCI_DEVICE_ID_PROMISE_20265:
1108 case PCI_DEVICE_ID_PROMISE_20267:
1109 case PCI_DEVICE_ID_PROMISE_20268:
1110 case PCI_DEVICE_ID_PROMISE_20269:
1111 case PCI_DEVICE_ID_PROMISE_20270:
1112 case PCI_DEVICE_ID_PROMISE_20271:
1113 case PCI_DEVICE_ID_PROMISE_20275:
1114 case PCI_DEVICE_ID_PROMISE_20276:
1115 case PCI_DEVICE_ID_PROMISE_20277:
1118 /* Others, check PCI class */
1119 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
1122 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1123 if ((progif & 5) != 5) {
1124 printk(KERN_INFO "PCI: %s Forcing PCI IDE into native mode\n",
1126 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5);
1127 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) ||
1129 printk(KERN_ERR "Rewrite of PROGIF failed !\n");
1131 /* Clear IO BARs, they will be reassigned */
1132 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
1133 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
1134 pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0);
1135 pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, 0);
1139 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata);
1140 #endif /* CONFIG_PPC32 */
1143 * Disable second function on K2-SATA, it's broken
1144 * and disable IO BARs on first one
1146 static void fixup_k2_sata(struct pci_dev* dev)
1151 if (PCI_FUNC(dev->devfn) > 0) {
1152 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1153 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1154 pci_write_config_word(dev, PCI_COMMAND, cmd);
1155 for (i = 0; i < 6; i++) {
1156 dev->resource[i].start = dev->resource[i].end = 0;
1157 dev->resource[i].flags = 0;
1158 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
1162 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1163 cmd &= ~PCI_COMMAND_IO;
1164 pci_write_config_word(dev, PCI_COMMAND, cmd);
1165 for (i = 0; i < 5; i++) {
1166 dev->resource[i].start = dev->resource[i].end = 0;
1167 dev->resource[i].flags = 0;
1168 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i,
1173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);
1176 * On U4 (aka CPC945) the PCIe root complex "P2P" bridge resource ranges aren't
1177 * configured by the firmware. The bridge itself seems to ignore them but it
1178 * causes problems with Linux which then re-assigns devices below the bridge,
1179 * thus changing addresses of those devices from what was in the device-tree,
1180 * which sucks when those are video cards using offb
1182 * We could just mark it transparent but I prefer fixing up the resources to
1183 * properly show what's going on here, as I have some doubts about having them
1184 * badly configured potentially being an issue for DMA.
1186 * We leave PIO alone, it seems to be fine
1188 * Oh and there's another funny bug. The OF properties advertize the region
1189 * 0xf1000000..0xf1ffffff as being forwarded as memory space. But that's
1190 * actually not true, this region is the memory mapped config space. So we
1191 * also need to filter it out or we'll map things in the wrong place.
1193 static void fixup_u4_pcie(struct pci_dev* dev)
1195 struct pci_controller *host = pci_bus_to_host(dev->bus);
1196 struct resource *region = NULL;
1200 /* Only do that on PowerMac */
1201 if (!machine_is(powermac))
1204 /* Find the largest MMIO region */
1205 for (i = 0; i < 3; i++) {
1206 struct resource *r = &host->mem_resources[i];
1207 if (!(r->flags & IORESOURCE_MEM))
1209 /* Skip the 0xf0xxxxxx..f2xxxxxx regions, we know they
1210 * are reserved by HW for other things
1212 if (r->start >= 0xf0000000 && r->start < 0xf3000000)
1214 if (!region || resource_size(r) > resource_size(region))
1217 /* Nothing found, bail */
1221 /* Print things out */
1222 printk(KERN_INFO "PCI: Fixup U4 PCIe bridge range: %pR\n", region);
1224 /* Fixup bridge config space. We know it's a Mac, resource aren't
1225 * offset so let's just blast them as-is. We also know that they
1228 reg = ((region->start >> 16) & 0xfff0) | (region->end & 0xfff00000);
1229 pci_write_config_dword(dev, PCI_MEMORY_BASE, reg);
1230 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0);
1231 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
1232 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0);
1234 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_U4_PCIE, fixup_u4_pcie);
1237 static int pmac_pci_probe_mode(struct pci_bus *bus)
1239 struct device_node *node = pci_bus_to_OF_node(bus);
1241 /* We need to use normal PCI probing for the AGP bus,
1242 * since the device for the AGP bridge isn't in the tree.
1243 * Same for the PCIe host on U4 and the HT host bridge.
1245 if (bus->self == NULL && (of_device_is_compatible(node, "u3-agp") ||
1246 of_device_is_compatible(node, "u4-pcie") ||
1247 of_device_is_compatible(node, "u3-ht")))
1248 return PCI_PROBE_NORMAL;
1249 return PCI_PROBE_DEVTREE;
1251 #endif /* CONFIG_PPC64 */
1253 struct pci_controller_ops pmac_pci_controller_ops = {
1255 .probe_mode = pmac_pci_probe_mode,
1258 .enable_device_hook = pmac_pci_enable_device_hook,