arch/powerpc/platforms/powermac/nvram.c

   1 /*
   2  *  Copyright (C) 2002 Benjamin Herrenschmidt (benh@kernel.crashing.org)
   3  *
   4  *  This program is free software; you can redistribute it and/or
   5  *  modify it under the terms of the GNU General Public License
   6  *  as published by the Free Software Foundation; either version
   7  *  2 of the License, or (at your option) any later version.
   8  *
   9  *  Todo: - add support for the OF persistent properties
  10  */
  11 #include <linux/export.h>
  12 #include <linux/kernel.h>
  13 #include <linux/stddef.h>
  14 #include <linux/string.h>
  15 #include <linux/nvram.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/errno.h>
  19 #include <linux/adb.h>
  20 #include <linux/pmu.h>
  21 #include <linux/memblock.h>
  22 #include <linux/completion.h>
  23 #include <linux/spinlock.h>
  24 #include <asm/sections.h>
  25 #include <asm/io.h>
  26 #include <asm/prom.h>
  27 #include <asm/machdep.h>
  28 #include <asm/nvram.h>
  29
  30 #include "pmac.h"
  31
  32 #define DEBUG
  33
  34 #ifdef DEBUG
  35 #define DBG(x...) printk(x)
  36 #else
  37 #define DBG(x...)
  38 #endif
  39
  40 #define NVRAM_SIZE              0x2000  /* 8kB of non-volatile RAM */
  41
  42 #define CORE99_SIGNATURE        0x5a
  43 #define CORE99_ADLER_START      0x14
  44
  45 /* On Core99, nvram is either a sharp, a micron or an AMD flash */
  46 #define SM_FLASH_STATUS_DONE    0x80
  47 #define SM_FLASH_STATUS_ERR     0x38
  48
  49 #define SM_FLASH_CMD_ERASE_CONFIRM      0xd0
  50 #define SM_FLASH_CMD_ERASE_SETUP        0x20
  51 #define SM_FLASH_CMD_RESET              0xff
  52 #define SM_FLASH_CMD_WRITE_SETUP        0x40
  53 #define SM_FLASH_CMD_CLEAR_STATUS       0x50
  54 #define SM_FLASH_CMD_READ_STATUS        0x70
  55
  56 /* CHRP NVRAM header */
  57 struct chrp_header {
  58   u8            signature;
  59   u8            cksum;
  60   u16           len;
  61   char          name[12];
  62   u8            data[0];
  63 };
  64
  65 struct core99_header {
  66   struct chrp_header    hdr;
  67   u32                   adler;
  68   u32                   generation;
  69   u32                   reserved[2];
  70 };
  71
  72 /*
  73  * Read and write the non-volatile RAM on PowerMacs and CHRP machines.
  74  */
  75 static int nvram_naddrs;
  76 static volatile unsigned char __iomem *nvram_data;
  77 static int is_core_99;
  78 static int core99_bank = 0;
  79 static int nvram_partitions[3];
  80 // XXX Turn that into a sem
  81 static DEFINE_RAW_SPINLOCK(nv_lock);
  82
  83 static int (*core99_write_bank)(int bank, u8* datas);
  84 static int (*core99_erase_bank)(int bank);
  85
  86 static char *nvram_image;
  87
  88
  89 static unsigned char core99_nvram_read_byte(int addr)
  90 {
  91         if (nvram_image == NULL)
  92                 return 0xff;
  93         return nvram_image[addr];
  94 }
  95
  96 static void core99_nvram_write_byte(int addr, unsigned char val)
  97 {
  98         if (nvram_image == NULL)
  99                 return;
 100         nvram_image[addr] = val;
 101 }
 102
 103 static ssize_t core99_nvram_read(char *buf, size_t count, loff_t *index)
 104 {
 105         int i;
 106
 107         if (nvram_image == NULL)
 108                 return -ENODEV;
 109         if (*index > NVRAM_SIZE)
 110                 return 0;
 111
 112         i = *index;
 113         if (i + count > NVRAM_SIZE)
 114                 count = NVRAM_SIZE - i;
 115
 116         memcpy(buf, &nvram_image[i], count);
 117         *index = i + count;
 118         return count;
 119 }
 120
 121 static ssize_t core99_nvram_write(char *buf, size_t count, loff_t *index)
 122 {
 123         int i;
 124
 125         if (nvram_image == NULL)
 126                 return -ENODEV;
 127         if (*index > NVRAM_SIZE)
 128                 return 0;
 129
 130         i = *index;
 131         if (i + count > NVRAM_SIZE)
 132                 count = NVRAM_SIZE - i;
 133
 134         memcpy(&nvram_image[i], buf, count);
 135         *index = i + count;
 136         return count;
 137 }
 138
 139 static ssize_t core99_nvram_size(void)
 140 {
 141         if (nvram_image == NULL)
 142                 return -ENODEV;
 143         return NVRAM_SIZE;
 144 }
 145
 146 #ifdef CONFIG_PPC32
 147 static volatile unsigned char __iomem *nvram_addr;
 148 static int nvram_mult;
 149
 150 static ssize_t ppc32_nvram_size(void)
 151 {
 152         return NVRAM_SIZE;
 153 }
 154
 155 static unsigned char direct_nvram_read_byte(int addr)
 156 {
 157         return in_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult]);
 158 }
 159
 160 static void direct_nvram_write_byte(int addr, unsigned char val)
 161 {
 162         out_8(&nvram_data[(addr & (NVRAM_SIZE - 1)) * nvram_mult], val);
 163 }
 164
 165
 166 static unsigned char indirect_nvram_read_byte(int addr)
 167 {
 168         unsigned char val;
 169         unsigned long flags;
 170
 171         raw_spin_lock_irqsave(&nv_lock, flags);
 172         out_8(nvram_addr, addr >> 5);
 173         val = in_8(&nvram_data[(addr & 0x1f) << 4]);
 174         raw_spin_unlock_irqrestore(&nv_lock, flags);
 175
 176         return val;
 177 }
 178
 179 static void indirect_nvram_write_byte(int addr, unsigned char val)
 180 {
 181         unsigned long flags;
 182
 183         raw_spin_lock_irqsave(&nv_lock, flags);
 184         out_8(nvram_addr, addr >> 5);
 185         out_8(&nvram_data[(addr & 0x1f) << 4], val);
 186         raw_spin_unlock_irqrestore(&nv_lock, flags);
 187 }
 188
 189
 190 #ifdef CONFIG_ADB_PMU
 191
 192 static void pmu_nvram_complete(struct adb_request *req)
 193 {
 194         if (req->arg)
 195                 complete((struct completion *)req->arg);
 196 }
 197
 198 static unsigned char pmu_nvram_read_byte(int addr)
 199 {
 200         struct adb_request req;
 201         DECLARE_COMPLETION_ONSTACK(req_complete);
 202
 203         req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
 204         if (pmu_request(&req, pmu_nvram_complete, 3, PMU_READ_NVRAM,
 205                         (addr >> 8) & 0xff, addr & 0xff))
 206                 return 0xff;
 207         if (system_state == SYSTEM_RUNNING)
 208                 wait_for_completion(&req_complete);
 209         while (!req.complete)
 210                 pmu_poll();
 211         return req.reply[0];
 212 }
 213
 214 static void pmu_nvram_write_byte(int addr, unsigned char val)
 215 {
 216         struct adb_request req;
 217         DECLARE_COMPLETION_ONSTACK(req_complete);
 218
 219         req.arg = system_state == SYSTEM_RUNNING ? &req_complete : NULL;
 220         if (pmu_request(&req, pmu_nvram_complete, 4, PMU_WRITE_NVRAM,
 221                         (addr >> 8) & 0xff, addr & 0xff, val))
 222                 return;
 223         if (system_state == SYSTEM_RUNNING)
 224                 wait_for_completion(&req_complete);
 225         while (!req.complete)
 226                 pmu_poll();
 227 }
 228
 229 #endif /* CONFIG_ADB_PMU */
 230 #endif /* CONFIG_PPC32 */
 231
 232 static u8 chrp_checksum(struct chrp_header* hdr)
 233 {
 234         u8 *ptr;
 235         u16 sum = hdr->signature;
 236         for (ptr = (u8 *)&hdr->len; ptr < hdr->data; ptr++)
 237                 sum += *ptr;
 238         while (sum > 0xFF)
 239                 sum = (sum & 0xFF) + (sum>>8);
 240         return sum;
 241 }
 242
 243 static u32 core99_calc_adler(u8 *buffer)
 244 {
 245         int cnt;
 246         u32 low, high;
 247
 248         buffer += CORE99_ADLER_START;
 249         low = 1;
 250         high = 0;
 251         for (cnt=0; cnt<(NVRAM_SIZE-CORE99_ADLER_START); cnt++) {
 252                 if ((cnt % 5000) == 0) {
 253                         high  %= 65521UL;
 254                         high %= 65521UL;
 255                 }
 256                 low += buffer[cnt];
 257                 high += low;
 258         }
 259         low  %= 65521UL;
 260         high %= 65521UL;
 261
 262         return (high << 16) | low;
 263 }
 264
 265 static u32 core99_check(u8* datas)
 266 {
 267         struct core99_header* hdr99 = (struct core99_header*)datas;
 268
 269         if (hdr99->hdr.signature != CORE99_SIGNATURE) {
 270                 DBG("Invalid signature\n");
 271                 return 0;
 272         }
 273         if (hdr99->hdr.cksum != chrp_checksum(&hdr99->hdr)) {
 274                 DBG("Invalid checksum\n");
 275                 return 0;
 276         }
 277         if (hdr99->adler != core99_calc_adler(datas)) {
 278                 DBG("Invalid adler\n");
 279                 return 0;
 280         }
 281         return hdr99->generation;
 282 }
 283
 284 static int sm_erase_bank(int bank)
 285 {
 286         int stat;
 287         unsigned long timeout;
 288
 289         u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
 290
 291         DBG("nvram: Sharp/Micron Erasing bank %d...\n", bank);
 292
 293         out_8(base, SM_FLASH_CMD_ERASE_SETUP);
 294         out_8(base, SM_FLASH_CMD_ERASE_CONFIRM);
 295         timeout = 0;
 296         do {
 297                 if (++timeout > 1000000) {
 298                         printk(KERN_ERR "nvram: Sharp/Micron flash erase timeout !\n");
 299                         break;
 300                 }
 301                 out_8(base, SM_FLASH_CMD_READ_STATUS);
 302                 stat = in_8(base);
 303         } while (!(stat & SM_FLASH_STATUS_DONE));
 304
 305         out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
 306         out_8(base, SM_FLASH_CMD_RESET);
 307
 308         if (memchr_inv(base, 0xff, NVRAM_SIZE)) {
 309                 printk(KERN_ERR "nvram: Sharp/Micron flash erase failed !\n");
 310                 return -ENXIO;
 311         }
 312         return 0;
 313 }
 314
 315 static int sm_write_bank(int bank, u8* datas)
 316 {
 317         int i, stat = 0;
 318         unsigned long timeout;
 319
 320         u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
 321
 322         DBG("nvram: Sharp/Micron Writing bank %d...\n", bank);
 323
 324         for (i=0; i<NVRAM_SIZE; i++) {
 325                 out_8(base+i, SM_FLASH_CMD_WRITE_SETUP);
 326                 udelay(1);
 327                 out_8(base+i, datas[i]);
 328                 timeout = 0;
 329                 do {
 330                         if (++timeout > 1000000) {
 331                                 printk(KERN_ERR "nvram: Sharp/Micron flash write timeout !\n");
 332                                 break;
 333                         }
 334                         out_8(base, SM_FLASH_CMD_READ_STATUS);
 335                         stat = in_8(base);
 336                 } while (!(stat & SM_FLASH_STATUS_DONE));
 337                 if (!(stat & SM_FLASH_STATUS_DONE))
 338                         break;
 339         }
 340         out_8(base, SM_FLASH_CMD_CLEAR_STATUS);
 341         out_8(base, SM_FLASH_CMD_RESET);
 342         if (memcmp(base, datas, NVRAM_SIZE)) {
 343                 printk(KERN_ERR "nvram: Sharp/Micron flash write failed !\n");
 344                 return -ENXIO;
 345         }
 346         return 0;
 347 }
 348
 349 static int amd_erase_bank(int bank)
 350 {
 351         int stat = 0;
 352         unsigned long timeout;
 353
 354         u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
 355
 356         DBG("nvram: AMD Erasing bank %d...\n", bank);
 357
 358         /* Unlock 1 */
 359         out_8(base+0x555, 0xaa);
 360         udelay(1);
 361         /* Unlock 2 */
 362         out_8(base+0x2aa, 0x55);
 363         udelay(1);
 364
 365         /* Sector-Erase */
 366         out_8(base+0x555, 0x80);
 367         udelay(1);
 368         out_8(base+0x555, 0xaa);
 369         udelay(1);
 370         out_8(base+0x2aa, 0x55);
 371         udelay(1);
 372         out_8(base, 0x30);
 373         udelay(1);
 374
 375         timeout = 0;
 376         do {
 377                 if (++timeout > 1000000) {
 378                         printk(KERN_ERR "nvram: AMD flash erase timeout !\n");
 379                         break;
 380                 }
 381                 stat = in_8(base) ^ in_8(base);
 382         } while (stat != 0);
 383
 384         /* Reset */
 385         out_8(base, 0xf0);
 386         udelay(1);
 387
 388         if (memchr_inv(base, 0xff, NVRAM_SIZE)) {
 389                 printk(KERN_ERR "nvram: AMD flash erase failed !\n");
 390                 return -ENXIO;
 391         }
 392         return 0;
 393 }
 394
 395 static int amd_write_bank(int bank, u8* datas)
 396 {
 397         int i, stat = 0;
 398         unsigned long timeout;
 399
 400         u8 __iomem *base = (u8 __iomem *)nvram_data + core99_bank*NVRAM_SIZE;
 401
 402         DBG("nvram: AMD Writing bank %d...\n", bank);
 403
 404         for (i=0; i<NVRAM_SIZE; i++) {
 405                 /* Unlock 1 */
 406                 out_8(base+0x555, 0xaa);
 407                 udelay(1);
 408                 /* Unlock 2 */
 409                 out_8(base+0x2aa, 0x55);
 410                 udelay(1);
 411
 412                 /* Write single word */
 413                 out_8(base+0x555, 0xa0);
 414                 udelay(1);
 415                 out_8(base+i, datas[i]);
 416
 417                 timeout = 0;
 418                 do {
 419                         if (++timeout > 1000000) {
 420                                 printk(KERN_ERR "nvram: AMD flash write timeout !\n");
 421                                 break;
 422                         }
 423                         stat = in_8(base) ^ in_8(base);
 424                 } while (stat != 0);
 425                 if (stat != 0)
 426                         break;
 427         }
 428
 429         /* Reset */
 430         out_8(base, 0xf0);
 431         udelay(1);
 432
 433         if (memcmp(base, datas, NVRAM_SIZE)) {
 434                 printk(KERN_ERR "nvram: AMD flash write failed !\n");
 435                 return -ENXIO;
 436         }
 437         return 0;
 438 }
 439
 440 static void __init lookup_partitions(void)
 441 {
 442         u8 buffer[17];
 443         int i, offset;
 444         struct chrp_header* hdr;
 445
 446         if (pmac_newworld) {
 447                 nvram_partitions[pmac_nvram_OF] = -1;
 448                 nvram_partitions[pmac_nvram_XPRAM] = -1;
 449                 nvram_partitions[pmac_nvram_NR] = -1;
 450                 hdr = (struct chrp_header *)buffer;
 451
 452                 offset = 0;
 453                 buffer[16] = 0;
 454                 do {
 455                         for (i=0;i<16;i++)
 456                                 buffer[i] = ppc_md.nvram_read_val(offset+i);
 457                         if (!strcmp(hdr->name, "common"))
 458                                 nvram_partitions[pmac_nvram_OF] = offset + 0x10;
 459                         if (!strcmp(hdr->name, "APL,MacOS75")) {
 460                                 nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10;
 461                                 nvram_partitions[pmac_nvram_NR] = offset + 0x110;
 462                         }
 463                         offset += (hdr->len * 0x10);
 464                 } while(offset < NVRAM_SIZE);
 465         } else {
 466                 nvram_partitions[pmac_nvram_OF] = 0x1800;
 467                 nvram_partitions[pmac_nvram_XPRAM] = 0x1300;
 468                 nvram_partitions[pmac_nvram_NR] = 0x1400;
 469         }
 470         DBG("nvram: OF partition at 0x%x\n", nvram_partitions[pmac_nvram_OF]);
 471         DBG("nvram: XP partition at 0x%x\n", nvram_partitions[pmac_nvram_XPRAM]);
 472         DBG("nvram: NR partition at 0x%x\n", nvram_partitions[pmac_nvram_NR]);
 473 }
 474
 475 static void core99_nvram_sync(void)
 476 {
 477         struct core99_header* hdr99;
 478         unsigned long flags;
 479
 480         if (!is_core_99 || !nvram_data || !nvram_image)
 481                 return;
 482
 483         raw_spin_lock_irqsave(&nv_lock, flags);
 484         if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE,
 485                 NVRAM_SIZE))
 486                 goto bail;
 487
 488         DBG("Updating nvram...\n");
 489
 490         hdr99 = (struct core99_header*)nvram_image;
 491         hdr99->generation++;
 492         hdr99->hdr.signature = CORE99_SIGNATURE;
 493         hdr99->hdr.cksum = chrp_checksum(&hdr99->hdr);
 494         hdr99->adler = core99_calc_adler(nvram_image);
 495         core99_bank = core99_bank ? 0 : 1;
 496         if (core99_erase_bank)
 497                 if (core99_erase_bank(core99_bank)) {
 498                         printk("nvram: Error erasing bank %d\n", core99_bank);
 499                         goto bail;
 500                 }
 501         if (core99_write_bank)
 502                 if (core99_write_bank(core99_bank, nvram_image))
 503                         printk("nvram: Error writing bank %d\n", core99_bank);
 504  bail:
 505         raw_spin_unlock_irqrestore(&nv_lock, flags);
 506
 507 #ifdef DEBUG
 508         mdelay(2000);
 509 #endif
 510 }
 511
 512 static int __init core99_nvram_setup(struct device_node *dp, unsigned long addr)
 513 {
 514         int i;
 515         u32 gen_bank0, gen_bank1;
 516
 517         if (nvram_naddrs < 1) {
 518                 printk(KERN_ERR "nvram: no address\n");
 519                 return -EINVAL;
 520         }
 521         nvram_image = memblock_alloc(NVRAM_SIZE, SMP_CACHE_BYTES);
 522         if (!nvram_image)
 523                 panic("%s: Failed to allocate %u bytes\n", __func__,
 524                       NVRAM_SIZE);
 525         nvram_data = ioremap(addr, NVRAM_SIZE*2);
 526         nvram_naddrs = 1; /* Make sure we get the correct case */
 527
 528         DBG("nvram: Checking bank 0...\n");
 529
 530         gen_bank0 = core99_check((u8 *)nvram_data);
 531         gen_bank1 = core99_check((u8 *)nvram_data + NVRAM_SIZE);
 532         core99_bank = (gen_bank0 < gen_bank1) ? 1 : 0;
 533
 534         DBG("nvram: gen0=%d, gen1=%d\n", gen_bank0, gen_bank1);
 535         DBG("nvram: Active bank is: %d\n", core99_bank);
 536
 537         for (i=0; i<NVRAM_SIZE; i++)
 538                 nvram_image[i] = nvram_data[i + core99_bank*NVRAM_SIZE];
 539
 540         ppc_md.nvram_read_val   = core99_nvram_read_byte;
 541         ppc_md.nvram_write_val  = core99_nvram_write_byte;
 542         ppc_md.nvram_read       = core99_nvram_read;
 543         ppc_md.nvram_write      = core99_nvram_write;
 544         ppc_md.nvram_size       = core99_nvram_size;
 545         ppc_md.nvram_sync       = core99_nvram_sync;
 546         ppc_md.machine_shutdown = core99_nvram_sync;
 547         /*
 548          * Maybe we could be smarter here though making an exclusive list
 549          * of known flash chips is a bit nasty as older OF didn't provide us
 550          * with a useful "compatible" entry. A solution would be to really
 551          * identify the chip using flash id commands and base ourselves on
 552          * a list of known chips IDs
 553          */
 554         if (of_device_is_compatible(dp, "amd-0137")) {
 555                 core99_erase_bank = amd_erase_bank;
 556                 core99_write_bank = amd_write_bank;
 557         } else {
 558                 core99_erase_bank = sm_erase_bank;
 559                 core99_write_bank = sm_write_bank;
 560         }
 561         return 0;
 562 }
 563
 564 int __init pmac_nvram_init(void)
 565 {
 566         struct device_node *dp;
 567         struct resource r1, r2;
 568         unsigned int s1 = 0, s2 = 0;
 569         int err = 0;
 570
 571         nvram_naddrs = 0;
 572
 573         dp = of_find_node_by_name(NULL, "nvram");
 574         if (dp == NULL) {
 575                 printk(KERN_ERR "Can't find NVRAM device\n");
 576                 return -ENODEV;
 577         }
 578
 579         /* Try to obtain an address */
 580         if (of_address_to_resource(dp, 0, &r1) == 0) {
 581                 nvram_naddrs = 1;
 582                 s1 = resource_size(&r1);
 583                 if (of_address_to_resource(dp, 1, &r2) == 0) {
 584                         nvram_naddrs = 2;
 585                         s2 = resource_size(&r2);
 586                 }
 587         }
 588
 589         is_core_99 = of_device_is_compatible(dp, "nvram,flash");
 590         if (is_core_99) {
 591                 err = core99_nvram_setup(dp, r1.start);
 592                 goto bail;
 593         }
 594
 595 #ifdef CONFIG_PPC32
 596         if (machine_is(chrp) && nvram_naddrs == 1) {
 597                 nvram_data = ioremap(r1.start, s1);
 598                 nvram_mult = 1;
 599                 ppc_md.nvram_read_val   = direct_nvram_read_byte;
 600                 ppc_md.nvram_write_val  = direct_nvram_write_byte;
 601                 ppc_md.nvram_size       = ppc32_nvram_size;
 602         } else if (nvram_naddrs == 1) {
 603                 nvram_data = ioremap(r1.start, s1);
 604                 nvram_mult = (s1 + NVRAM_SIZE - 1) / NVRAM_SIZE;
 605                 ppc_md.nvram_read_val   = direct_nvram_read_byte;
 606                 ppc_md.nvram_write_val  = direct_nvram_write_byte;
 607                 ppc_md.nvram_size       = ppc32_nvram_size;
 608         } else if (nvram_naddrs == 2) {
 609                 nvram_addr = ioremap(r1.start, s1);
 610                 nvram_data = ioremap(r2.start, s2);
 611                 ppc_md.nvram_read_val   = indirect_nvram_read_byte;
 612                 ppc_md.nvram_write_val  = indirect_nvram_write_byte;
 613                 ppc_md.nvram_size       = ppc32_nvram_size;
 614         } else if (nvram_naddrs == 0 && sys_ctrler == SYS_CTRLER_PMU) {
 615 #ifdef CONFIG_ADB_PMU
 616                 nvram_naddrs = -1;
 617                 ppc_md.nvram_read_val   = pmu_nvram_read_byte;
 618                 ppc_md.nvram_write_val  = pmu_nvram_write_byte;
 619                 ppc_md.nvram_size       = ppc32_nvram_size;
 620 #endif /* CONFIG_ADB_PMU */
 621         } else {
 622                 printk(KERN_ERR "Incompatible type of NVRAM\n");
 623                 err = -ENXIO;
 624         }
 625 #endif /* CONFIG_PPC32 */
 626 bail:
 627         of_node_put(dp);
 628         if (err == 0)
 629                 lookup_partitions();
 630         return err;
 631 }
 632
 633 int pmac_get_partition(int partition)
 634 {
 635         return nvram_partitions[partition];
 636 }
 637
 638 u8 pmac_xpram_read(int xpaddr)
 639 {
 640         int offset = pmac_get_partition(pmac_nvram_XPRAM);
 641
 642         if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
 643                 return 0xff;
 644
 645         return ppc_md.nvram_read_val(xpaddr + offset);
 646 }
 647
 648 void pmac_xpram_write(int xpaddr, u8 data)
 649 {
 650         int offset = pmac_get_partition(pmac_nvram_XPRAM);
 651
 652         if (offset < 0 || xpaddr < 0 || xpaddr > 0x100)
 653                 return;
 654
 655         ppc_md.nvram_write_val(xpaddr + offset, data);
 656 }
 657
 658 EXPORT_SYMBOL(pmac_get_partition);
 659 EXPORT_SYMBOL(pmac_xpram_read);
 660 EXPORT_SYMBOL(pmac_xpram_write);