5 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/string.h>
9 #include <linux/init.h>
10 #include <linux/ide.h>
13 #include <asm/pgtable.h>
15 #include <asm/hydra.h>
18 #include <asm/machdep.h>
19 #include <asm/sections.h>
20 #include <asm/pci-bridge.h>
21 #include <asm/open_pic.h>
22 #include <asm/grackle.h>
28 void __iomem *gg2_pci_config_base;
31 * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
32 * limit the bus number to 3 bits
35 int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
38 volatile void __iomem *cfg_data;
39 struct pci_controller *hose = bus->sysdata;
42 return PCIBIOS_DEVICE_NOT_FOUND;
44 * Note: the caller has already checked that off is
45 * suitably aligned and that len is 1, 2 or 4.
47 cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
50 *val = in_8(cfg_data);
53 *val = in_le16(cfg_data);
56 *val = in_le32(cfg_data);
59 return PCIBIOS_SUCCESSFUL;
62 int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
65 volatile void __iomem *cfg_data;
66 struct pci_controller *hose = bus->sysdata;
69 return PCIBIOS_DEVICE_NOT_FOUND;
71 * Note: the caller has already checked that off is
72 * suitably aligned and that len is 1, 2 or 4.
74 cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
80 out_le16(cfg_data, val);
83 out_le32(cfg_data, val);
86 return PCIBIOS_SUCCESSFUL;
89 static struct pci_ops gg2_pci_ops =
96 * Access functions for PCI config space using RTAS calls.
98 int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
101 struct pci_controller *hose = bus->sysdata;
102 unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
103 | (((bus->number - hose->first_busno) & 0xff) << 16)
104 | (hose->index << 24);
108 rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len);
110 return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
113 int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
116 struct pci_controller *hose = bus->sysdata;
117 unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
118 | (((bus->number - hose->first_busno) & 0xff) << 16)
119 | (hose->index << 24);
122 rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL,
124 return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
127 static struct pci_ops rtas_pci_ops =
133 volatile struct Hydra __iomem *Hydra = NULL;
138 struct device_node *np;
141 np = find_devices("mac-io");
142 if (np == NULL || of_address_to_resource(np, 0, &r))
144 Hydra = ioremap(r.start, r.end-r.start);
145 printk("Hydra Mac I/O at %llx\n", (unsigned long long)r.start);
146 printk("Hydra Feature_Control was %x",
147 in_le32(&Hydra->Feature_Control));
148 out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
149 HYDRA_FC_SCSI_CELL_EN |
150 HYDRA_FC_SCCA_ENABLE |
151 HYDRA_FC_SCCB_ENABLE |
152 HYDRA_FC_ARB_BYPASS |
153 HYDRA_FC_MPIC_ENABLE |
154 HYDRA_FC_SLOW_SCC_PCLK |
155 HYDRA_FC_MPIC_IS_MASTER));
156 printk(", now %x\n", in_le32(&Hydra->Feature_Control));
161 chrp_pcibios_fixup(void)
163 struct pci_dev *dev = NULL;
164 struct device_node *np;
166 /* PCI interrupts are controlled by the OpenPIC */
167 for_each_pci_dev(dev) {
168 np = pci_device_to_OF_node(dev);
169 if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0))
170 dev->irq = np->intrs[0].line;
171 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
175 #define PRG_CL_RESET_VALID 0x00010000
178 setup_python(struct pci_controller *hose, struct device_node *dev)
184 if (of_address_to_resource(dev, 0, &r)) {
185 printk(KERN_ERR "No address for Python PCI controller\n");
189 /* Clear the magic go-slow bit */
190 reg = ioremap(r.start + 0xf6000, 0x40);
192 val = in_be32(®[12]);
193 if (val & PRG_CL_RESET_VALID) {
194 out_be32(®[12], val & ~PRG_CL_RESET_VALID);
199 setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010);
202 /* Marvell Discovery II based Pegasos 2 */
203 static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev)
205 struct device_node *root = find_path_device("/");
206 struct device_node *rtas;
209 rtas = of_find_node_by_name (root, "rtas");
211 hose->ops = &rtas_pci_ops;
214 printk ("RTAS supporting Pegasos OF not found, please upgrade"
217 pci_assign_all_buses = 1;
221 chrp_find_bridges(void)
223 struct device_node *dev;
226 struct pci_controller *hose;
228 char *model, *machine;
229 int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
230 struct device_node *root = find_path_device("/");
233 * The PCI host bridge nodes on some machines don't have
234 * properties to adequately identify them, so we have to
235 * look at what sort of machine this is as well.
237 machine = get_property(root, "model", NULL);
238 if (machine != NULL) {
239 is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
240 is_mot = strncmp(machine, "MOT", 3) == 0;
241 if (strncmp(machine, "Pegasos2", 8) == 0)
243 else if (strncmp(machine, "Pegasos", 7) == 0)
246 for (dev = root->child; dev != NULL; dev = dev->sibling) {
247 if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
250 /* The GG2 bridge on the LongTrail doesn't have an address */
251 if (of_address_to_resource(dev, 0, &r) && !is_longtrail) {
252 printk(KERN_WARNING "Can't use %s: no address\n",
256 bus_range = (int *) get_property(dev, "bus-range", &len);
257 if (bus_range == NULL || len < 2 * sizeof(int)) {
258 printk(KERN_WARNING "Can't get bus-range for %s\n",
262 if (bus_range[1] == bus_range[0])
263 printk(KERN_INFO "PCI bus %d", bus_range[0]);
265 printk(KERN_INFO "PCI buses %d..%d",
266 bus_range[0], bus_range[1]);
267 printk(" controlled by %s", dev->type);
269 printk(" at %llx", (unsigned long long)r.start);
272 hose = pcibios_alloc_controller();
274 printk("Can't allocate PCI controller structure for %s\n",
278 hose->arch_data = dev;
279 hose->first_busno = bus_range[0];
280 hose->last_busno = bus_range[1];
282 model = get_property(dev, "model", NULL);
285 if (device_is_compatible(dev, "IBM,python")) {
286 setup_python(hose, dev);
288 || strncmp(model, "Motorola, Grackle", 17) == 0) {
290 } else if (is_longtrail) {
291 void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
292 hose->ops = &gg2_pci_ops;
294 gg2_pci_config_base = p;
295 } else if (is_pegasos == 1) {
296 setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
297 } else if (is_pegasos == 2) {
298 setup_peg2(hose, dev);
300 printk("No methods for %s (model %s), using RTAS\n",
301 dev->full_name, model);
302 hose->ops = &rtas_pci_ops;
305 pci_process_bridge_OF_ranges(hose, dev, index == 0);
307 /* check the first bridge for a property that we can
308 use to set pci_dram_offset */
309 dma = (unsigned int *)
310 get_property(dev, "ibm,dma-ranges", &len);
311 if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
312 pci_dram_offset = dma[2] - dma[3];
313 printk("pci_dram_offset = %lx\n", pci_dram_offset);
317 /* Do not fixup interrupts from OF tree on pegasos */
319 ppc_md.pcibios_fixup = NULL;