1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/arch/powerpc/platforms/cell/cell_setup.c
5 * Copyright (C) 1995 Linus Torvalds
6 * Adapted from 'alpha' version by Gary Thomas
7 * Modified by Cort Dougan (cort@cs.nmt.edu)
8 * Modified by PPC64 Team, IBM Corp
9 * Modified by Cell Team, IBM Deutschland Entwicklung GmbH
13 #include <linux/sched.h>
14 #include <linux/kernel.h>
16 #include <linux/stddef.h>
17 #include <linux/export.h>
18 #include <linux/unistd.h>
19 #include <linux/user.h>
20 #include <linux/reboot.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/irq.h>
24 #include <linux/seq_file.h>
25 #include <linux/root_dev.h>
26 #include <linux/console.h>
27 #include <linux/mutex.h>
28 #include <linux/memory_hotplug.h>
29 #include <linux/of_platform.h>
32 #include <asm/processor.h>
34 #include <asm/pgtable.h>
37 #include <asm/pci-bridge.h>
38 #include <asm/iommu.h>
40 #include <asm/machdep.h>
42 #include <asm/nvram.h>
43 #include <asm/cputable.h>
44 #include <asm/ppc-pci.h>
47 #include <asm/spu_priv1.h>
50 #include <asm/cell-regs.h>
51 #include <asm/io-workarounds.h>
54 #include "interrupt.h"
55 #include "pervasive.h"
59 #define DBG(fmt...) udbg_printf(fmt)
64 static void cell_show_cpuinfo(struct seq_file *m)
66 struct device_node *root;
67 const char *model = "";
69 root = of_find_node_by_path("/");
71 model = of_get_property(root, "model", NULL);
72 seq_printf(m, "machine\t\t: CHRP %s\n", model);
76 static void cell_progress(char *s, unsigned short hex)
78 printk("*** %04x : %s\n", hex, s ? s : "");
81 static void cell_fixup_pcie_rootcomplex(struct pci_dev *dev)
83 struct pci_controller *hose;
87 if (!machine_is(cell))
90 /* We're searching for a direct child of the PHB */
91 if (dev->bus->self != NULL || dev->devfn != 0)
94 hose = pci_bus_to_host(dev->bus);
99 if (!of_device_is_compatible(hose->dn, "pciex"))
102 /* And only on axon */
103 s = of_get_property(hose->dn, "model", NULL);
104 if (!s || strcmp(s, "Axon") != 0)
107 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
108 dev->resource[i].start = dev->resource[i].end = 0;
109 dev->resource[i].flags = 0;
112 printk(KERN_DEBUG "PCI: Hiding resources on Axon PCIE RC %s\n",
115 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, cell_fixup_pcie_rootcomplex);
117 static int cell_setup_phb(struct pci_controller *phb)
120 struct device_node *np;
122 int rc = rtas_setup_phb(phb);
126 phb->controller_ops = cell_pci_controller_ops;
129 model = of_get_property(np, "model", NULL);
130 if (model == NULL || !of_node_name_eq(np, "pci"))
133 /* Setup workarounds for spider */
134 if (strcmp(model, "Spider"))
137 iowa_register_bus(phb, &spiderpci_ops, &spiderpci_iowa_init,
138 (void *)SPIDER_PCI_REG_BASE);
142 static const struct of_device_id cell_bus_ids[] __initconst = {
144 { .compatible = "soc", },
145 { .type = "spider", },
154 static int __init cell_publish_devices(void)
156 struct device_node *root = of_find_node_by_path("/");
157 struct device_node *np;
160 /* Publish OF platform devices for southbridge IOs */
161 of_platform_bus_probe(NULL, cell_bus_ids, NULL);
163 /* On spider based blades, we need to manually create the OF
164 * platform devices for the PCI host bridges
166 for_each_child_of_node(root, np) {
167 if (!of_node_is_type(np, "pci") && !of_node_is_type(np, "pciex"))
169 of_platform_device_create(np, NULL, NULL);
172 /* There is no device for the MIC memory controller, thus we create
173 * a platform device for it to attach the EDAC driver to.
175 for_each_online_node(node) {
176 if (cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(node)) == NULL)
178 platform_device_register_simple("cbe-mic", node, NULL, 0);
183 machine_subsys_initcall(cell, cell_publish_devices);
185 static void __init mpic_init_IRQ(void)
187 struct device_node *dn;
190 for_each_node_by_name(dn, "interrupt-controller") {
191 if (!of_device_is_compatible(dn, "CBEA,platform-open-pic"))
194 /* The MPIC driver will get everything it needs from the
195 * device-tree, just pass 0 to all arguments
197 mpic = mpic_alloc(dn, 0, MPIC_SECONDARY | MPIC_NO_RESET,
206 static void __init cell_init_irq(void)
213 static void __init cell_set_dabrx(void)
215 mtspr(SPRN_DABRX, DABRX_KERNEL | DABRX_USER);
218 static void __init cell_setup_arch(void)
220 #ifdef CONFIG_SPU_BASE
221 spu_priv1_ops = &spu_priv1_mmio_ops;
222 spu_management_ops = &spu_management_of_ops;
229 #ifdef CONFIG_CBE_RAS
236 /* init to some ~sane value until calibrate_delay() runs */
237 loops_per_jiffy = 50000000;
239 /* Find and initialize PCI host bridges */
240 init_pci_config_tokens();
242 cbe_pervasive_init();
243 #ifdef CONFIG_DUMMY_CONSOLE
244 conswitchp = &dummy_con;
250 static int __init cell_probe(void)
252 if (!of_machine_is_compatible("IBM,CBEA") &&
253 !of_machine_is_compatible("IBM,CPBW-1.0"))
256 pm_power_off = rtas_power_off;
261 define_machine(cell) {
264 .setup_arch = cell_setup_arch,
265 .show_cpuinfo = cell_show_cpuinfo,
266 .restart = rtas_restart,
268 .get_boot_time = rtas_get_boot_time,
269 .get_rtc_time = rtas_get_rtc_time,
270 .set_rtc_time = rtas_set_rtc_time,
271 .calibrate_decr = generic_calibrate_decr,
272 .progress = cell_progress,
273 .init_IRQ = cell_init_irq,
274 .pci_setup_phb = cell_setup_phb,
277 struct pci_controller_ops cell_pci_controller_ops;