6 This option selects whether a 32-bit or a 64-bit kernel
9 menu "Processor support"
11 prompt "Processor Type"
14 There are five families of 32 bit PowerPC chips supported.
15 The most common ones are the desktop and server CPUs (601, 603,
16 604, 740, 750, 74xx) CPUs from Freescale and IBM, with their
17 embedded 512x/52xx/82xx/83xx/86xx counterparts.
18 The other embedded parts, namely 4xx, 8xx, e200 (55xx) and e500
19 (85xx) each form a family of their own that is not compatible
22 If unsure, select 52xx/6xx/7xx/74xx/82xx/83xx/86xx.
25 bool "512x/52xx/6xx/7xx/74xx/82xx/83xx/86xx"
37 select SYS_SUPPORTS_HUGETLBFS
47 bool "AMCC 44x, 46x or 47x"
60 prompt "Processor Type"
63 There are two families of 64 bit PowerPC chips supported.
64 The most common ones are the desktop and server CPUs
65 (POWER4, POWER5, 970, POWER5+, POWER6, POWER7, POWER8 ...)
67 The other are the "embedded" processors compliant with the
68 "Book 3E" variant of the architecture
71 bool "Server processors"
73 select PPC_HAVE_PMU_SUPPORT
74 select SYS_SUPPORTS_HUGETLBFS
75 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
76 select ARCH_SUPPORTS_NUMA_BALANCING
81 bool "Embedded processors"
82 select PPC_FPU # Make it a choice ?
83 select PPC_SMP_MUXED_IPI
89 prompt "CPU selection"
91 default POWER8_CPU if CPU_LITTLE_ENDIAN
94 This will create a kernel which is optimised for a particular CPU.
95 The resulting kernel may not run on other CPUs, so use this with care.
97 If unsure, select Generic.
101 depends on !CPU_LITTLE_ENDIAN
104 bool "Cell Broadband Engine"
105 depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN
109 depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN
113 depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN
117 depends on PPC_BOOK3S_64 && !CPU_LITTLE_ENDIAN
121 depends on PPC_BOOK3S_64
122 select ARCH_HAS_FAST_MULTIPLIER
126 depends on PPC_BOOK3S_64
127 select ARCH_HAS_FAST_MULTIPLIER
130 bool "Freescale e5500"
134 bool "Freescale e6500"
141 depends on PPC_BOOK3S_32 || PPC_BOOK3S_64
145 depends on PPC_BOOK3E_64
149 depends on PPC32 && PPC_BOOK3S
150 select PPC_HAVE_PMU_SUPPORT
152 # this is temp to handle compat with arch=ppc
157 select FSL_EMB_PERFMON
158 select PPC_FSL_BOOK3E
162 bool "e500mc Support"
167 This must be enabled for running on e500mc (and derivatives
168 such as e5500/e6500), and must be disabled for running on
175 config PPC_8xx_PERF_EVENT
176 bool "PPC 8xx perf events"
177 depends on PPC_8xx && PERF_EVENTS
179 This is Performance Events support for PPC 8xx. The 8xx doesn't
180 have a PMU but some events are emulated using 8xx features.
182 config FSL_EMB_PERFMON
183 bool "Freescale Embedded Perfmon"
184 depends on E500 || PPC_83xx
186 This is the Performance Monitor support found on the e500 core
187 and some e300 cores (c3 and c4). Select this only if your
188 core supports the Embedded Performance Monitor APU
190 config FSL_EMB_PERF_EVENT
192 depends on FSL_EMB_PERFMON && PERF_EVENTS && !PPC_PERF_CTRS
195 config FSL_EMB_PERF_EVENT_E500
197 depends on FSL_EMB_PERF_EVENT && E500
202 depends on 40x || 44x
207 depends on E200 || E500 || 44x || PPC_BOOK3E
212 depends on (E200 || E500) && PPC32
215 # this is for common code between PPC32 & PPC64 FSL BOOKE
216 config PPC_FSL_BOOK3E
218 select FSL_EMB_PERFMON
219 select PPC_SMP_MUXED_IPI
220 select SYS_SUPPORTS_HUGETLBFS if PHYS_64BIT || PPC64
222 default y if FSL_BOOKE
226 depends on 44x || E500 || PPC_86xx
227 default y if PHYS_64BIT
230 bool 'Large physical address support' if E500 || PPC_86xx
231 depends on (44x || E500 || PPC_86xx) && !PPC_83xx && !PPC_82xx
233 This option enables kernel support for larger than 32-bit physical
234 addresses. This feature may not be available on all cores.
236 If you have more than 3.5GB of RAM or so, you also need to enable
237 SWIOTLB under Kernel Options for this to work. The actual number
238 is platform-dependent.
240 If in doubt, say N here.
243 bool "AltiVec Support"
244 depends on 6xx || PPC_BOOK3S_64 || (PPC_E500MC && PPC64)
246 This option enables kernel support for the Altivec extensions to the
247 PowerPC processor. The kernel currently supports saving and restoring
248 altivec registers, and turning on the 'altivec enable' bit so user
249 processes can execute altivec instructions.
251 This option is only usefully if you have a processor that supports
252 altivec (G4, otherwise known as 74xx series), but does not have
253 any affect on a non-altivec cpu (it does, however add code to the
256 If in doubt, say Y here.
260 depends on PPC_BOOK3S_64 && ALTIVEC && PPC_FPU
263 This option enables kernel support for the Vector Scaler extensions
264 to the PowerPC processor. The kernel currently supports saving and
265 restoring VSX registers, and turning on the 'VSX enable' bit so user
266 processes can execute VSX instructions.
268 This option is only useful if you have a processor that supports
269 VSX (P7 and above), but does not have any affect on a non-VSX
270 CPUs (it does, however add code to the kernel).
272 If in doubt, say Y here.
275 bool "Support for PowerPC icswx coprocessor instruction"
276 depends on PPC_BOOK3S_64
280 This option enables kernel support for the PowerPC Initiate
281 Coprocessor Store Word (icswx) coprocessor instruction on POWER7
282 and POWER8 processors. POWER9 uses new copy/paste instructions
283 to invoke the coprocessor.
285 This option is only useful if you have a processor that supports
286 the icswx coprocessor instruction. It does not have any effect
287 on processors without the icswx coprocessor instruction.
289 This option slightly increases kernel memory usage.
291 If in doubt, say N here.
294 bool "icswx requires direct PID management"
298 The PID register in server is used explicitly for ICSWX. In
299 embedded systems PID management is done by the system.
301 config PPC_ICSWX_USE_SIGILL
302 bool "Should a bad CT cause a SIGILL?"
306 Should a bad CT used for "non-record form ICSWX" cause an
307 illegal instruction signal or should it be silent as
310 If in doubt, say N here.
314 depends on E200 || (E500 && !PPC_E500MC)
318 depends on SPE_POSSIBLE
321 This option enables kernel support for the Signal Processing
322 Extensions (SPE) to the PowerPC processor. The kernel currently
323 supports saving and restoring SPE registers, and turning on the
324 'spe enable' bit so user processes can execute SPE instructions.
326 This option is only useful if you have a processor that supports
327 SPE (e500, otherwise known as 85xx series), but does not have any
328 effect on a non-spe cpu (it does, however add code to the kernel).
330 If in doubt, say Y here.
334 depends on PPC_BOOK3S
336 config PPC_STD_MMU_32
338 depends on PPC_STD_MMU && PPC32
340 config PPC_STD_MMU_64
342 depends on PPC_STD_MMU && PPC64
345 bool "Radix MMU Support"
346 depends on PPC_BOOK3S_64
349 Enable support for the Power ISA 3.0 Radix style MMU. Currently this
350 is only implemented by IBM Power9 CPUs, if you don't have one of them
351 you can probably disable this.
353 config ARCH_ENABLE_HUGEPAGE_MIGRATION
355 depends on PPC_BOOK3S_64 && HUGETLB_PAGE && MIGRATION
358 config PPC_MMU_NOHASH
360 depends on !PPC_STD_MMU
362 config PPC_BOOK3E_MMU
364 depends on FSL_BOOKE || PPC_BOOK3E
368 default y if PPC_STD_MMU_64
371 config PPC_HAVE_PMU_SUPPORT
376 depends on PERF_EVENTS && PPC_HAVE_PMU_SUPPORT
378 This enables the powerpc-specific perf_event back-end.
381 # Allow platforms to force SMP=y by selecting this
387 depends on PPC_BOOK3S || PPC_BOOK3E || FSL_BOOKE || PPC_47x
388 select GENERIC_IRQ_MIGRATION
389 bool "Symmetric multi-processing support" if !FORCE_SMP
391 This enables support for systems with more than one CPU. If you have
392 a system with only one CPU, say N. If you have a system with more
393 than one CPU, say Y. Note that the kernel does not currently
394 support SMP machines with 603/603e/603ev or PPC750 ("G3") processors
395 since they have inadequate hardware support for multiprocessor
398 If you say N here, the kernel will run on single and multiprocessor
399 machines, but will use only one CPU of a multiprocessor machine. If
400 you say Y here, the kernel will run on single-processor machines.
401 On a single-processor machine, the kernel will run faster if you say
404 If you don't know what to do here, say N.
407 int "Maximum number of CPUs (2-8192)"
410 default "32" if PPC64
413 config NOT_COHERENT_CACHE
415 depends on 4xx || 8xx || E200 || PPC_MPC512x || GAMECUBE_COMMON
419 config CHECK_CACHE_COHERENCY
430 depends on PPC32 || CPU_BIG_ENDIAN
432 This symbol controls whether we build the 32-bit VDSO. We obviously
433 want to do that if we're building a 32-bit kernel. If we're building
434 a 64-bit kernel then we only want a 32-bit VDSO if we're building for
435 big endian. That is because the only little endian configuration we
436 support is ppc64le which is 64-bit only.
439 prompt "Endianness selection"
440 default CPU_BIG_ENDIAN
442 This option selects whether a big endian or little endian kernel will
445 config CPU_BIG_ENDIAN
446 bool "Build big endian kernel"
448 Build a big endian kernel.
450 If unsure, select this option.
452 config CPU_LITTLE_ENDIAN
453 bool "Build little endian kernel"
454 depends on PPC_BOOK3S_64
455 select PPC64_BOOT_WRAPPER
457 Build a little endian kernel.
459 Note that if cross compiling a little endian kernel,
460 CROSS_COMPILE must point to a toolchain capable of targeting
461 little endian powerpc.
465 config PPC64_BOOT_WRAPPER
467 depends on CPU_LITTLE_ENDIAN