1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Author: Andy Fleming <afleming@freescale.com>
4 * Kumar Gala <galak@kernel.crashing.org>
6 * Copyright 2006-2008, 2011-2012, 2015 Freescale Semiconductor Inc.
9 #include <linux/stddef.h>
10 #include <linux/kernel.h>
11 #include <linux/sched/hotplug.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
15 #include <linux/kexec.h>
16 #include <linux/highmem.h>
17 #include <linux/cpu.h>
18 #include <linux/fsl/guts.h>
20 #include <asm/machdep.h>
21 #include <asm/pgtable.h>
24 #include <asm/cacheflush.h>
25 #include <asm/dbell.h>
26 #include <asm/code-patching.h>
27 #include <asm/cputhreads.h>
28 #include <asm/fsl_pm.h>
30 #include <sysdev/fsl_soc.h>
31 #include <sysdev/mpic.h>
34 struct epapr_spin_table {
43 #ifdef CONFIG_HOTPLUG_CPU
48 static void mpc85xx_give_timebase(void)
52 local_irq_save(flags);
59 qoriq_pm_ops->freeze_time_base(true);
62 * e5500/e6500 have a workaround for erratum A-006958 in place
63 * that will reread the timebase until TBL is non-zero.
64 * That would be a bad thing when the timebase is frozen.
66 * Thus, we read it manually, and instead of checking that
67 * TBL is non-zero, we ensure that TB does not change. We don't
68 * do that for the main mftb implementation, because it requires
74 asm volatile("mfspr %0, %1" : "=r" (timebase) :
79 asm volatile("mfspr %0, %1" : "=r" (timebase) :
81 } while (prev != timebase);
92 qoriq_pm_ops->freeze_time_base(false);
94 local_irq_restore(flags);
97 static void mpc85xx_take_timebase(void)
101 local_irq_save(flags);
108 set_tb(timebase >> 32, timebase & 0xffffffff);
112 local_irq_restore(flags);
115 static void smp_85xx_mach_cpu_die(void)
117 unsigned int cpu = smp_processor_id();
121 /* mask all irqs to prevent cpu wakeup */
122 qoriq_pm_ops->irq_mask(cpu);
127 mtspr(SPRN_TSR, mfspr(SPRN_TSR));
129 generic_set_cpu_dead(cpu);
131 cur_cpu_spec->cpu_down_flush();
133 qoriq_pm_ops->cpu_die(cpu);
139 static void qoriq_cpu_kill(unsigned int cpu)
143 for (i = 0; i < 500; i++) {
144 if (is_cpu_dead(cpu)) {
146 paca_ptrs[cpu]->cpu_start = 0;
152 pr_err("CPU%d didn't die...\n", cpu);
157 * To keep it compatible with old boot program which uses
158 * cache-inhibit spin table, we need to flush the cache
159 * before accessing spin table to invalidate any staled data.
160 * We also need to flush the cache after writing to spin
161 * table to push data out.
163 static inline void flush_spin_table(void *spin_table)
165 flush_dcache_range((ulong)spin_table,
166 (ulong)spin_table + sizeof(struct epapr_spin_table));
169 static inline u32 read_spin_table_addr_l(void *spin_table)
171 flush_dcache_range((ulong)spin_table,
172 (ulong)spin_table + sizeof(struct epapr_spin_table));
173 return in_be32(&((struct epapr_spin_table *)spin_table)->addr_l);
177 static void wake_hw_thread(void *info)
179 void fsl_secondary_thread_init(void);
181 int cpu = *(const int *)info;
183 inia = *(unsigned long *)fsl_secondary_thread_init;
184 book3e_start_thread(cpu_thread_in_core(cpu), inia);
188 static int smp_85xx_start_cpu(int cpu)
191 struct device_node *np;
192 const u64 *cpu_rel_addr;
195 int hw_cpu = get_hard_smp_processor_id(cpu);
196 struct epapr_spin_table __iomem *spin_table;
198 np = of_get_cpu_node(cpu, NULL);
199 cpu_rel_addr = of_get_property(np, "cpu-release-addr", NULL);
201 pr_err("No cpu-release-addr for cpu %d\n", cpu);
206 * A secondary core could be in a spinloop in the bootpage
207 * (0xfffff000), somewhere in highmem, or somewhere in lowmem.
208 * The bootpage and highmem can be accessed via ioremap(), but
209 * we need to directly access the spinloop if its in lowmem.
211 ioremappable = *cpu_rel_addr > virt_to_phys(high_memory);
213 /* Map the spin table */
215 spin_table = ioremap_coherent(*cpu_rel_addr,
216 sizeof(struct epapr_spin_table));
218 spin_table = phys_to_virt(*cpu_rel_addr);
220 local_irq_save(flags);
224 qoriq_pm_ops->cpu_up_prepare(cpu);
226 /* if cpu is not spinning, reset it */
227 if (read_spin_table_addr_l(spin_table) != 1) {
229 * We don't set the BPTR register here since it already points
230 * to the boot page properly.
232 mpic_reset_core(cpu);
235 * wait until core is ready...
236 * We need to invalidate the stale data, in case the boot
237 * loader uses a cache-inhibited spin table.
239 if (!spin_event_timeout(
240 read_spin_table_addr_l(spin_table) == 1,
242 pr_err("timeout waiting for cpu %d to reset\n",
249 flush_spin_table(spin_table);
250 out_be32(&spin_table->pir, hw_cpu);
252 out_be64((u64 *)(&spin_table->addr_h),
253 __pa(ppc_function_entry(generic_secondary_smp_init)));
255 out_be32(&spin_table->addr_l, __pa(__early_start));
257 flush_spin_table(spin_table);
259 local_irq_restore(flags);
267 static int smp_85xx_kick_cpu(int nr)
274 WARN_ON(nr < 0 || nr >= num_possible_cpus());
276 pr_debug("kick CPU #%d\n", nr);
279 if (threads_per_core == 2) {
280 if (WARN_ON_ONCE(!cpu_has_feature(CPU_FTR_SMT)))
283 booting_thread_hwid = cpu_thread_in_core(nr);
284 primary = cpu_first_thread_sibling(nr);
287 qoriq_pm_ops->cpu_up_prepare(nr);
290 * If either thread in the core is online, use it to start
293 if (cpu_online(primary)) {
294 smp_call_function_single(primary,
295 wake_hw_thread, &nr, 1);
297 } else if (cpu_online(primary + 1)) {
298 smp_call_function_single(primary + 1,
299 wake_hw_thread, &nr, 1);
304 * If getting here, it means both threads in the core are
305 * offline. So start the primary thread, then it will start
306 * the thread specified in booting_thread_hwid, the one
307 * corresponding to nr.
310 } else if (threads_per_core == 1) {
312 * If one core has only one thread, set booting_thread_hwid to
315 booting_thread_hwid = INVALID_THREAD_HWID;
317 } else if (threads_per_core > 2) {
318 pr_err("Do not support more than 2 threads per CPU.");
322 ret = smp_85xx_start_cpu(primary);
327 paca_ptrs[nr]->cpu_start = 1;
328 generic_set_cpu_up(nr);
332 ret = smp_85xx_start_cpu(nr);
336 generic_set_cpu_up(nr);
342 struct smp_ops_t smp_85xx_ops = {
343 .cause_nmi_ipi = NULL,
344 .kick_cpu = smp_85xx_kick_cpu,
345 .cpu_bootable = smp_generic_cpu_bootable,
346 #ifdef CONFIG_HOTPLUG_CPU
347 .cpu_disable = generic_cpu_disable,
348 .cpu_die = generic_cpu_die,
350 #if defined(CONFIG_KEXEC_CORE) && !defined(CONFIG_PPC64)
351 .give_timebase = smp_generic_give_timebase,
352 .take_timebase = smp_generic_take_timebase,
356 #ifdef CONFIG_KEXEC_CORE
358 atomic_t kexec_down_cpus = ATOMIC_INIT(0);
360 void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
365 cur_cpu_spec->cpu_down_flush();
366 atomic_inc(&kexec_down_cpus);
372 static void mpc85xx_smp_kexec_down(void *arg)
374 if (ppc_md.kexec_cpu_down)
375 ppc_md.kexec_cpu_down(0,1);
378 void mpc85xx_smp_kexec_cpu_down(int crash_shutdown, int secondary)
380 int cpu = smp_processor_id();
381 int sibling = cpu_last_thread_sibling(cpu);
382 bool notified = false;
384 int disable_threadbit = 0;
390 mpic_teardown_this_cpu(secondary);
392 if (cpu == crashing_cpu && cpu_thread_in_core(cpu) != 0) {
394 * We enter the crash kernel on whatever cpu crashed,
395 * even if it's a secondary thread. If that's the case,
396 * disable the corresponding primary thread.
398 disable_threadbit = 1;
399 disable_cpu = cpu_first_thread_sibling(cpu);
400 } else if (sibling != crashing_cpu &&
401 cpu_thread_in_core(cpu) == 0 &&
402 cpu_thread_in_core(sibling) != 0) {
403 disable_threadbit = 2;
404 disable_cpu = sibling;
407 if (disable_threadbit) {
408 while (paca_ptrs[disable_cpu]->kexec_state < KEXEC_STATE_REAL_MODE) {
411 if (!notified && now - start > 1000000) {
412 pr_info("%s/%d: waiting for cpu %d to enter KEXEC_STATE_REAL_MODE (%d)\n",
413 __func__, smp_processor_id(),
415 paca_ptrs[disable_cpu]->kexec_state);
421 pr_info("%s: cpu %d done waiting\n",
422 __func__, disable_cpu);
425 mtspr(SPRN_TENC, disable_threadbit);
426 while (mfspr(SPRN_TENSR) & disable_threadbit)
432 static void mpc85xx_smp_machine_kexec(struct kimage *image)
435 int timeout = INT_MAX;
436 int i, num_cpus = num_present_cpus();
438 if (image->type == KEXEC_TYPE_DEFAULT)
439 smp_call_function(mpc85xx_smp_kexec_down, NULL, 0);
441 while ( (atomic_read(&kexec_down_cpus) != (num_cpus - 1)) &&
448 printk(KERN_ERR "Unable to bring down secondary cpu(s)");
450 for_each_online_cpu(i)
452 if ( i == smp_processor_id() ) continue;
457 default_machine_kexec(image);
459 #endif /* CONFIG_KEXEC_CORE */
461 static void smp_85xx_setup_cpu(int cpu_nr)
463 mpic_setup_this_cpu();
466 void __init mpc85xx_smp_init(void)
468 struct device_node *np;
471 np = of_find_node_by_type(NULL, "open-pic");
473 smp_85xx_ops.probe = smp_mpic_probe;
474 smp_85xx_ops.setup_cpu = smp_85xx_setup_cpu;
475 smp_85xx_ops.message_pass = smp_mpic_message_pass;
477 smp_85xx_ops.setup_cpu = NULL;
479 if (cpu_has_feature(CPU_FTR_DBELL)) {
481 * If left NULL, .message_pass defaults to
482 * smp_muxed_ipi_message_pass
484 smp_85xx_ops.message_pass = NULL;
485 smp_85xx_ops.cause_ipi = doorbell_global_ipi;
486 smp_85xx_ops.probe = NULL;
489 #ifdef CONFIG_HOTPLUG_CPU
490 #ifdef CONFIG_FSL_CORENET_RCPM
494 #ifdef CONFIG_FSL_PMC
498 smp_85xx_ops.give_timebase = mpc85xx_give_timebase;
499 smp_85xx_ops.take_timebase = mpc85xx_take_timebase;
500 ppc_md.cpu_die = smp_85xx_mach_cpu_die;
501 smp_85xx_ops.cpu_die = qoriq_cpu_kill;
504 smp_ops = &smp_85xx_ops;
506 #ifdef CONFIG_KEXEC_CORE
507 ppc_md.kexec_cpu_down = mpc85xx_smp_kexec_cpu_down;
508 ppc_md.machine_kexec = mpc85xx_smp_machine_kexec;