2 * Performance event support - powerpc architecture code
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/perf_event.h>
14 #include <linux/percpu.h>
15 #include <linux/hardirq.h>
16 #include <linux/uaccess.h>
19 #include <asm/machdep.h>
20 #include <asm/firmware.h>
21 #include <asm/ptrace.h>
22 #include <asm/code-patching.h>
24 #define BHRB_MAX_ENTRIES 32
25 #define BHRB_TARGET 0x0000000000000002
26 #define BHRB_PREDICTION 0x0000000000000001
27 #define BHRB_EA 0xFFFFFFFFFFFFFFFC
29 struct cpu_hw_events {
36 struct perf_event *event[MAX_HWEVENTS];
37 u64 events[MAX_HWEVENTS];
38 unsigned int flags[MAX_HWEVENTS];
39 unsigned long mmcr[3];
40 struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS];
41 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
42 u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
43 unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
44 unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
46 unsigned int group_flag;
50 u64 bhrb_filter; /* BHRB HW branch filter */
53 struct perf_branch_stack bhrb_stack;
54 struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES];
57 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
59 struct power_pmu *ppmu;
62 * Normally, to ignore kernel events we set the FCS (freeze counters
63 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
64 * hypervisor bit set in the MSR, or if we are running on a processor
65 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
66 * then we need to use the FCHV bit to ignore kernel events.
68 static unsigned int freeze_events_kernel = MMCR0_FCS;
71 * 32-bit doesn't have MMCRA but does have an MMCR2,
72 * and a few other names are different.
77 #define MMCR0_PMCjCE MMCR0_PMCnCE
82 #define MMCR0_PMCC_U6 0
84 #define SPRN_MMCRA SPRN_MMCR2
85 #define MMCRA_SAMPLE_ENABLE 0
87 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
91 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { }
92 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
96 static inline void perf_read_regs(struct pt_regs *regs)
100 static inline int perf_intr_is_nmi(struct pt_regs *regs)
105 static inline int siar_valid(struct pt_regs *regs)
110 static bool is_ebb_event(struct perf_event *event) { return false; }
111 static int ebb_event_check(struct perf_event *event) { return 0; }
112 static void ebb_event_add(struct perf_event *event) { }
113 static void ebb_switch_out(unsigned long mmcr0) { }
114 static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0)
119 static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
120 static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
121 void power_pmu_flush_branch_stack(void) {}
122 static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {}
123 #endif /* CONFIG_PPC32 */
125 static bool regs_use_siar(struct pt_regs *regs)
127 return !!regs->result;
131 * Things that are specific to 64-bit implementations.
135 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
137 unsigned long mmcra = regs->dsisr;
139 if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) {
140 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
142 return 4 * (slot - 1);
149 * The user wants a data address recorded.
150 * If we're not doing instruction sampling, give them the SDAR
151 * (sampled data address). If we are doing instruction sampling, then
152 * only give them the SDAR if it corresponds to the instruction
153 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the
154 * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER.
156 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
158 unsigned long mmcra = regs->dsisr;
161 if (ppmu->flags & PPMU_HAS_SIER)
162 sdar_valid = regs->dar & SIER_SDAR_VALID;
164 unsigned long sdsync;
166 if (ppmu->flags & PPMU_SIAR_VALID)
167 sdsync = POWER7P_MMCRA_SDAR_VALID;
168 else if (ppmu->flags & PPMU_ALT_SIPR)
169 sdsync = POWER6_MMCRA_SDSYNC;
171 sdsync = MMCRA_SDSYNC;
173 sdar_valid = mmcra & sdsync;
176 if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid)
177 *addrp = mfspr(SPRN_SDAR);
180 static bool regs_sihv(struct pt_regs *regs)
182 unsigned long sihv = MMCRA_SIHV;
184 if (ppmu->flags & PPMU_HAS_SIER)
185 return !!(regs->dar & SIER_SIHV);
187 if (ppmu->flags & PPMU_ALT_SIPR)
188 sihv = POWER6_MMCRA_SIHV;
190 return !!(regs->dsisr & sihv);
193 static bool regs_sipr(struct pt_regs *regs)
195 unsigned long sipr = MMCRA_SIPR;
197 if (ppmu->flags & PPMU_HAS_SIER)
198 return !!(regs->dar & SIER_SIPR);
200 if (ppmu->flags & PPMU_ALT_SIPR)
201 sipr = POWER6_MMCRA_SIPR;
203 return !!(regs->dsisr & sipr);
206 static inline u32 perf_flags_from_msr(struct pt_regs *regs)
208 if (regs->msr & MSR_PR)
209 return PERF_RECORD_MISC_USER;
210 if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV)
211 return PERF_RECORD_MISC_HYPERVISOR;
212 return PERF_RECORD_MISC_KERNEL;
215 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
217 bool use_siar = regs_use_siar(regs);
220 return perf_flags_from_msr(regs);
223 * If we don't have flags in MMCRA, rather than using
224 * the MSR, we intuit the flags from the address in
225 * SIAR which should give slightly more reliable
228 if (ppmu->flags & PPMU_NO_SIPR) {
229 unsigned long siar = mfspr(SPRN_SIAR);
230 if (siar >= PAGE_OFFSET)
231 return PERF_RECORD_MISC_KERNEL;
232 return PERF_RECORD_MISC_USER;
235 /* PR has priority over HV, so order below is important */
237 return PERF_RECORD_MISC_USER;
239 if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV))
240 return PERF_RECORD_MISC_HYPERVISOR;
242 return PERF_RECORD_MISC_KERNEL;
246 * Overload regs->dsisr to store MMCRA so we only need to read it once
248 * Overload regs->dar to store SIER if we have it.
249 * Overload regs->result to specify whether we should use the MSR (result
250 * is zero) or the SIAR (result is non zero).
252 static inline void perf_read_regs(struct pt_regs *regs)
254 unsigned long mmcra = mfspr(SPRN_MMCRA);
255 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
260 if (ppmu->flags & PPMU_HAS_SIER)
261 regs->dar = mfspr(SPRN_SIER);
264 * If this isn't a PMU exception (eg a software event) the SIAR is
265 * not valid. Use pt_regs.
267 * If it is a marked event use the SIAR.
269 * If the PMU doesn't update the SIAR for non marked events use
272 * If the PMU has HV/PR flags then check to see if they
273 * place the exception in userspace. If so, use pt_regs. In
274 * continuous sampling mode the SIAR and the PMU exception are
275 * not synchronised, so they may be many instructions apart.
276 * This can result in confusing backtraces. We still want
277 * hypervisor samples as well as samples in the kernel with
278 * interrupts off hence the userspace check.
280 if (TRAP(regs) != 0xf00)
284 else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING))
286 else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs))
291 regs->result = use_siar;
295 * If interrupts were soft-disabled when a PMU interrupt occurs, treat
298 static inline int perf_intr_is_nmi(struct pt_regs *regs)
304 * On processors like P7+ that have the SIAR-Valid bit, marked instructions
305 * must be sampled only if the SIAR-valid bit is set.
307 * For unmarked instructions and for processors that don't have the SIAR-Valid
308 * bit, assume that SIAR is valid.
310 static inline int siar_valid(struct pt_regs *regs)
312 unsigned long mmcra = regs->dsisr;
313 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
316 if (ppmu->flags & PPMU_HAS_SIER)
317 return regs->dar & SIER_SIAR_VALID;
319 if (ppmu->flags & PPMU_SIAR_VALID)
320 return mmcra & POWER7P_MMCRA_SIAR_VALID;
327 /* Reset all possible BHRB entries */
328 static void power_pmu_bhrb_reset(void)
330 asm volatile(PPC_CLRBHRB);
333 static void power_pmu_bhrb_enable(struct perf_event *event)
335 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
340 /* Clear BHRB if we changed task context to avoid data leaks */
341 if (event->ctx->task && cpuhw->bhrb_context != event->ctx) {
342 power_pmu_bhrb_reset();
343 cpuhw->bhrb_context = event->ctx;
348 static void power_pmu_bhrb_disable(struct perf_event *event)
350 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
356 WARN_ON_ONCE(cpuhw->bhrb_users < 0);
358 if (!cpuhw->disabled && !cpuhw->bhrb_users) {
359 /* BHRB cannot be turned off when other
360 * events are active on the PMU.
363 /* avoid stale pointer */
364 cpuhw->bhrb_context = NULL;
368 /* Called from ctxsw to prevent one process's branch entries to
369 * mingle with the other process's entries during context switch.
371 void power_pmu_flush_branch_stack(void)
374 power_pmu_bhrb_reset();
376 /* Calculate the to address for a branch */
377 static __u64 power_pmu_bhrb_to(u64 addr)
383 if (is_kernel_addr(addr))
384 return branch_target((unsigned int *)addr);
386 /* Userspace: need copy instruction here then translate it */
388 ret = __get_user_inatomic(instr, (unsigned int __user *)addr);
395 target = branch_target(&instr);
396 if ((!target) || (instr & BRANCH_ABSOLUTE))
399 /* Translate relative branch target from kernel to user address */
400 return target - (unsigned long)&instr + addr;
403 /* Processing BHRB entries */
404 void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw)
408 int r_index, u_index, pred;
412 while (r_index < ppmu->bhrb_nr) {
413 /* Assembly read function */
414 val = read_bhrb(r_index++);
416 /* Terminal marker: End of valid BHRB entries */
419 addr = val & BHRB_EA;
420 pred = val & BHRB_PREDICTION;
426 /* Branches are read most recent first (ie. mfbhrb 0 is
427 * the most recent branch).
428 * There are two types of valid entries:
429 * 1) a target entry which is the to address of a
430 * computed goto like a blr,bctr,btar. The next
431 * entry read from the bhrb will be branch
432 * corresponding to this target (ie. the actual
433 * blr/bctr/btar instruction).
434 * 2) a from address which is an actual branch. If a
435 * target entry proceeds this, then this is the
436 * matching branch for that target. If this is not
437 * following a target entry, then this is a branch
438 * where the target is given as an immediate field
439 * in the instruction (ie. an i or b form branch).
440 * In this case we need to read the instruction from
441 * memory to determine the target/to address.
444 if (val & BHRB_TARGET) {
445 /* Target branches use two entries
446 * (ie. computed gotos/XL form)
448 cpuhw->bhrb_entries[u_index].to = addr;
449 cpuhw->bhrb_entries[u_index].mispred = pred;
450 cpuhw->bhrb_entries[u_index].predicted = ~pred;
452 /* Get from address in next entry */
453 val = read_bhrb(r_index++);
454 addr = val & BHRB_EA;
455 if (val & BHRB_TARGET) {
456 /* Shouldn't have two targets in a
457 row.. Reset index and try again */
461 cpuhw->bhrb_entries[u_index].from = addr;
463 /* Branches to immediate field
465 cpuhw->bhrb_entries[u_index].from = addr;
466 cpuhw->bhrb_entries[u_index].to =
467 power_pmu_bhrb_to(addr);
468 cpuhw->bhrb_entries[u_index].mispred = pred;
469 cpuhw->bhrb_entries[u_index].predicted = ~pred;
475 cpuhw->bhrb_stack.nr = u_index;
479 static bool is_ebb_event(struct perf_event *event)
482 * This could be a per-PMU callback, but we'd rather avoid the cost. We
483 * check that the PMU supports EBB, meaning those that don't can still
484 * use bit 63 of the event code for something else if they wish.
486 return (ppmu->flags & PPMU_EBB) &&
487 ((event->attr.config >> EVENT_CONFIG_EBB_SHIFT) & 1);
490 static int ebb_event_check(struct perf_event *event)
492 struct perf_event *leader = event->group_leader;
494 /* Event and group leader must agree on EBB */
495 if (is_ebb_event(leader) != is_ebb_event(event))
498 if (is_ebb_event(event)) {
499 if (!(event->attach_state & PERF_ATTACH_TASK))
502 if (!leader->attr.pinned || !leader->attr.exclusive)
505 if (event->attr.inherit || event->attr.sample_period ||
506 event->attr.enable_on_exec || event->attr.freq)
513 static void ebb_event_add(struct perf_event *event)
515 if (!is_ebb_event(event) || current->thread.used_ebb)
519 * IFF this is the first time we've added an EBB event, set
520 * PMXE in the user MMCR0 so we can detect when it's cleared by
521 * userspace. We need this so that we can context switch while
522 * userspace is in the EBB handler (where PMXE is 0).
524 current->thread.used_ebb = 1;
525 current->thread.mmcr0 |= MMCR0_PMXE;
528 static void ebb_switch_out(unsigned long mmcr0)
530 if (!(mmcr0 & MMCR0_EBE))
533 current->thread.siar = mfspr(SPRN_SIAR);
534 current->thread.sier = mfspr(SPRN_SIER);
535 current->thread.sdar = mfspr(SPRN_SDAR);
536 current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK;
537 current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;
540 static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0)
545 /* Enable EBB and read/write to all 6 PMCs for userspace */
546 mmcr0 |= MMCR0_EBE | MMCR0_PMCC_U6;
548 /* Add any bits from the user reg, FC or PMAO */
549 mmcr0 |= current->thread.mmcr0;
551 /* Be careful not to set PMXE if userspace had it cleared */
552 if (!(current->thread.mmcr0 & MMCR0_PMXE))
553 mmcr0 &= ~MMCR0_PMXE;
555 mtspr(SPRN_SIAR, current->thread.siar);
556 mtspr(SPRN_SIER, current->thread.sier);
557 mtspr(SPRN_SDAR, current->thread.sdar);
558 mtspr(SPRN_MMCR2, current->thread.mmcr2);
562 #endif /* CONFIG_PPC64 */
564 static void perf_event_interrupt(struct pt_regs *regs);
566 void perf_event_print_debug(void)
571 * Read one performance monitor counter (PMC).
573 static unsigned long read_pmc(int idx)
579 val = mfspr(SPRN_PMC1);
582 val = mfspr(SPRN_PMC2);
585 val = mfspr(SPRN_PMC3);
588 val = mfspr(SPRN_PMC4);
591 val = mfspr(SPRN_PMC5);
594 val = mfspr(SPRN_PMC6);
598 val = mfspr(SPRN_PMC7);
601 val = mfspr(SPRN_PMC8);
603 #endif /* CONFIG_PPC64 */
605 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
614 static void write_pmc(int idx, unsigned long val)
618 mtspr(SPRN_PMC1, val);
621 mtspr(SPRN_PMC2, val);
624 mtspr(SPRN_PMC3, val);
627 mtspr(SPRN_PMC4, val);
630 mtspr(SPRN_PMC5, val);
633 mtspr(SPRN_PMC6, val);
637 mtspr(SPRN_PMC7, val);
640 mtspr(SPRN_PMC8, val);
642 #endif /* CONFIG_PPC64 */
644 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
649 * Check if a set of events can all go on the PMU at once.
650 * If they can't, this will look at alternative codes for the events
651 * and see if any combination of alternative codes is feasible.
652 * The feasible set is returned in event_id[].
654 static int power_check_constraints(struct cpu_hw_events *cpuhw,
655 u64 event_id[], unsigned int cflags[],
658 unsigned long mask, value, nv;
659 unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS];
660 int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS];
662 unsigned long addf = ppmu->add_fields;
663 unsigned long tadd = ppmu->test_adder;
665 if (n_ev > ppmu->n_counter)
668 /* First see if the events will go on as-is */
669 for (i = 0; i < n_ev; ++i) {
670 if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
671 && !ppmu->limited_pmc_event(event_id[i])) {
672 ppmu->get_alternatives(event_id[i], cflags[i],
673 cpuhw->alternatives[i]);
674 event_id[i] = cpuhw->alternatives[i][0];
676 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0],
677 &cpuhw->avalues[i][0]))
681 for (i = 0; i < n_ev; ++i) {
682 nv = (value | cpuhw->avalues[i][0]) +
683 (value & cpuhw->avalues[i][0] & addf);
684 if ((((nv + tadd) ^ value) & mask) != 0 ||
685 (((nv + tadd) ^ cpuhw->avalues[i][0]) &
686 cpuhw->amasks[i][0]) != 0)
689 mask |= cpuhw->amasks[i][0];
692 return 0; /* all OK */
694 /* doesn't work, gather alternatives... */
695 if (!ppmu->get_alternatives)
697 for (i = 0; i < n_ev; ++i) {
699 n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i],
700 cpuhw->alternatives[i]);
701 for (j = 1; j < n_alt[i]; ++j)
702 ppmu->get_constraint(cpuhw->alternatives[i][j],
703 &cpuhw->amasks[i][j],
704 &cpuhw->avalues[i][j]);
707 /* enumerate all possibilities and see if any will work */
710 value = mask = nv = 0;
713 /* we're backtracking, restore context */
719 * See if any alternative k for event_id i,
720 * where k > j, will satisfy the constraints.
722 while (++j < n_alt[i]) {
723 nv = (value | cpuhw->avalues[i][j]) +
724 (value & cpuhw->avalues[i][j] & addf);
725 if ((((nv + tadd) ^ value) & mask) == 0 &&
726 (((nv + tadd) ^ cpuhw->avalues[i][j])
727 & cpuhw->amasks[i][j]) == 0)
732 * No feasible alternative, backtrack
733 * to event_id i-1 and continue enumerating its
734 * alternatives from where we got up to.
740 * Found a feasible alternative for event_id i,
741 * remember where we got up to with this event_id,
742 * go on to the next event_id, and start with
743 * the first alternative for it.
749 mask |= cpuhw->amasks[i][j];
755 /* OK, we have a feasible combination, tell the caller the solution */
756 for (i = 0; i < n_ev; ++i)
757 event_id[i] = cpuhw->alternatives[i][choice[i]];
762 * Check if newly-added events have consistent settings for
763 * exclude_{user,kernel,hv} with each other and any previously
766 static int check_excludes(struct perf_event **ctrs, unsigned int cflags[],
767 int n_prev, int n_new)
769 int eu = 0, ek = 0, eh = 0;
771 struct perf_event *event;
778 for (i = 0; i < n; ++i) {
779 if (cflags[i] & PPMU_LIMITED_PMC_OK) {
780 cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
785 eu = event->attr.exclude_user;
786 ek = event->attr.exclude_kernel;
787 eh = event->attr.exclude_hv;
789 } else if (event->attr.exclude_user != eu ||
790 event->attr.exclude_kernel != ek ||
791 event->attr.exclude_hv != eh) {
797 for (i = 0; i < n; ++i)
798 if (cflags[i] & PPMU_LIMITED_PMC_OK)
799 cflags[i] |= PPMU_LIMITED_PMC_REQD;
804 static u64 check_and_compute_delta(u64 prev, u64 val)
806 u64 delta = (val - prev) & 0xfffffffful;
809 * POWER7 can roll back counter values, if the new value is smaller
810 * than the previous value it will cause the delta and the counter to
811 * have bogus values unless we rolled a counter over. If a coutner is
812 * rolled back, it will be smaller, but within 256, which is the maximum
813 * number of events to rollback at once. If we dectect a rollback
814 * return 0. This can lead to a small lack of precision in the
817 if (prev > val && (prev - val) < 256)
823 static void power_pmu_read(struct perf_event *event)
825 s64 val, delta, prev;
827 if (event->hw.state & PERF_HES_STOPPED)
833 if (is_ebb_event(event)) {
834 val = read_pmc(event->hw.idx);
835 local64_set(&event->hw.prev_count, val);
840 * Performance monitor interrupts come even when interrupts
841 * are soft-disabled, as long as interrupts are hard-enabled.
842 * Therefore we treat them like NMIs.
845 prev = local64_read(&event->hw.prev_count);
847 val = read_pmc(event->hw.idx);
848 delta = check_and_compute_delta(prev, val);
851 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
853 local64_add(delta, &event->count);
854 local64_sub(delta, &event->hw.period_left);
858 * On some machines, PMC5 and PMC6 can't be written, don't respect
859 * the freeze conditions, and don't generate interrupts. This tells
860 * us if `event' is using such a PMC.
862 static int is_limited_pmc(int pmcnum)
864 return (ppmu->flags & PPMU_LIMITED_PMC5_6)
865 && (pmcnum == 5 || pmcnum == 6);
868 static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
869 unsigned long pmc5, unsigned long pmc6)
871 struct perf_event *event;
872 u64 val, prev, delta;
875 for (i = 0; i < cpuhw->n_limited; ++i) {
876 event = cpuhw->limited_counter[i];
879 val = (event->hw.idx == 5) ? pmc5 : pmc6;
880 prev = local64_read(&event->hw.prev_count);
882 delta = check_and_compute_delta(prev, val);
884 local64_add(delta, &event->count);
888 static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
889 unsigned long pmc5, unsigned long pmc6)
891 struct perf_event *event;
895 for (i = 0; i < cpuhw->n_limited; ++i) {
896 event = cpuhw->limited_counter[i];
897 event->hw.idx = cpuhw->limited_hwidx[i];
898 val = (event->hw.idx == 5) ? pmc5 : pmc6;
899 prev = local64_read(&event->hw.prev_count);
900 if (check_and_compute_delta(prev, val))
901 local64_set(&event->hw.prev_count, val);
902 perf_event_update_userpage(event);
907 * Since limited events don't respect the freeze conditions, we
908 * have to read them immediately after freezing or unfreezing the
909 * other events. We try to keep the values from the limited
910 * events as consistent as possible by keeping the delay (in
911 * cycles and instructions) between freezing/unfreezing and reading
912 * the limited events as small and consistent as possible.
913 * Therefore, if any limited events are in use, we read them
914 * both, and always in the same order, to minimize variability,
915 * and do it inside the same asm that writes MMCR0.
917 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
919 unsigned long pmc5, pmc6;
921 if (!cpuhw->n_limited) {
922 mtspr(SPRN_MMCR0, mmcr0);
927 * Write MMCR0, then read PMC5 and PMC6 immediately.
928 * To ensure we don't get a performance monitor interrupt
929 * between writing MMCR0 and freezing/thawing the limited
930 * events, we first write MMCR0 with the event overflow
931 * interrupt enable bits turned off.
933 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
934 : "=&r" (pmc5), "=&r" (pmc6)
935 : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)),
937 "i" (SPRN_PMC5), "i" (SPRN_PMC6));
939 if (mmcr0 & MMCR0_FC)
940 freeze_limited_counters(cpuhw, pmc5, pmc6);
942 thaw_limited_counters(cpuhw, pmc5, pmc6);
945 * Write the full MMCR0 including the event overflow interrupt
946 * enable bits, if necessary.
948 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
949 mtspr(SPRN_MMCR0, mmcr0);
953 * Disable all events to prevent PMU interrupts and to allow
954 * events to be added or removed.
956 static void power_pmu_disable(struct pmu *pmu)
958 struct cpu_hw_events *cpuhw;
959 unsigned long flags, mmcr0, val;
963 local_irq_save(flags);
964 cpuhw = &__get_cpu_var(cpu_hw_events);
966 if (!cpuhw->disabled) {
968 * Check if we ever enabled the PMU on this cpu.
970 if (!cpuhw->pmcs_enabled) {
972 cpuhw->pmcs_enabled = 1;
976 * Set the 'freeze counters' bit, clear EBE/PMCC/PMAO/FC56.
978 val = mmcr0 = mfspr(SPRN_MMCR0);
980 val &= ~(MMCR0_EBE | MMCR0_PMCC | MMCR0_PMAO | MMCR0_FC56);
983 * The barrier is to make sure the mtspr has been
984 * executed and the PMU has frozen the events etc.
987 write_mmcr0(cpuhw, val);
991 * Disable instruction sampling if it was enabled
993 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
995 cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1002 ebb_switch_out(mmcr0);
1005 local_irq_restore(flags);
1009 * Re-enable all events if disable == 0.
1010 * If we were previously disabled and events were added, then
1011 * put the new config on the PMU.
1013 static void power_pmu_enable(struct pmu *pmu)
1015 struct perf_event *event;
1016 struct cpu_hw_events *cpuhw;
1017 unsigned long flags;
1019 unsigned long val, mmcr0;
1021 unsigned int hwc_index[MAX_HWEVENTS];
1028 local_irq_save(flags);
1030 cpuhw = &__get_cpu_var(cpu_hw_events);
1031 if (!cpuhw->disabled)
1034 if (cpuhw->n_events == 0) {
1035 ppc_set_pmu_inuse(0);
1039 cpuhw->disabled = 0;
1042 * EBB requires an exclusive group and all events must have the EBB
1043 * flag set, or not set, so we can just check a single event. Also we
1044 * know we have at least one event.
1046 ebb = is_ebb_event(cpuhw->event[0]);
1049 * If we didn't change anything, or only removed events,
1050 * no need to recalculate MMCR* settings and reset the PMCs.
1051 * Just reenable the PMU with the current MMCR* settings
1052 * (possibly updated for removal of events).
1054 if (!cpuhw->n_added) {
1055 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1056 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1061 * Compute MMCR* values for the new set of events
1063 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
1065 /* shouldn't ever get here */
1066 printk(KERN_ERR "oops compute_mmcr failed\n");
1071 * Add in MMCR0 freeze bits corresponding to the
1072 * attr.exclude_* bits for the first event.
1073 * We have already checked that all events have the
1074 * same values for these bits as the first event.
1076 event = cpuhw->event[0];
1077 if (event->attr.exclude_user)
1078 cpuhw->mmcr[0] |= MMCR0_FCP;
1079 if (event->attr.exclude_kernel)
1080 cpuhw->mmcr[0] |= freeze_events_kernel;
1081 if (event->attr.exclude_hv)
1082 cpuhw->mmcr[0] |= MMCR0_FCHV;
1085 * Write the new configuration to MMCR* with the freeze
1086 * bit set and set the hardware events to their initial values.
1087 * Then unfreeze the events.
1089 ppc_set_pmu_inuse(1);
1090 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1091 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1092 mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
1096 * Read off any pre-existing events that need to move
1099 for (i = 0; i < cpuhw->n_events; ++i) {
1100 event = cpuhw->event[i];
1101 if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) {
1102 power_pmu_read(event);
1103 write_pmc(event->hw.idx, 0);
1109 * Initialize the PMCs for all the new and moved events.
1111 cpuhw->n_limited = n_lim = 0;
1112 for (i = 0; i < cpuhw->n_events; ++i) {
1113 event = cpuhw->event[i];
1116 idx = hwc_index[i] + 1;
1117 if (is_limited_pmc(idx)) {
1118 cpuhw->limited_counter[n_lim] = event;
1119 cpuhw->limited_hwidx[n_lim] = idx;
1125 val = local64_read(&event->hw.prev_count);
1128 if (event->hw.sample_period) {
1129 left = local64_read(&event->hw.period_left);
1130 if (left < 0x80000000L)
1131 val = 0x80000000L - left;
1133 local64_set(&event->hw.prev_count, val);
1136 event->hw.idx = idx;
1137 if (event->hw.state & PERF_HES_STOPPED)
1139 write_pmc(idx, val);
1141 perf_event_update_userpage(event);
1143 cpuhw->n_limited = n_lim;
1144 cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
1147 mmcr0 = ebb_switch_in(ebb, cpuhw->mmcr[0]);
1150 write_mmcr0(cpuhw, mmcr0);
1153 * Enable instruction sampling if necessary
1155 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1157 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
1161 if (cpuhw->bhrb_users)
1162 ppmu->config_bhrb(cpuhw->bhrb_filter);
1164 local_irq_restore(flags);
1167 static int collect_events(struct perf_event *group, int max_count,
1168 struct perf_event *ctrs[], u64 *events,
1169 unsigned int *flags)
1172 struct perf_event *event;
1174 if (!is_software_event(group)) {
1178 flags[n] = group->hw.event_base;
1179 events[n++] = group->hw.config;
1181 list_for_each_entry(event, &group->sibling_list, group_entry) {
1182 if (!is_software_event(event) &&
1183 event->state != PERF_EVENT_STATE_OFF) {
1187 flags[n] = event->hw.event_base;
1188 events[n++] = event->hw.config;
1195 * Add a event to the PMU.
1196 * If all events are not already frozen, then we disable and
1197 * re-enable the PMU in order to get hw_perf_enable to do the
1198 * actual work of reconfiguring the PMU.
1200 static int power_pmu_add(struct perf_event *event, int ef_flags)
1202 struct cpu_hw_events *cpuhw;
1203 unsigned long flags;
1207 local_irq_save(flags);
1208 perf_pmu_disable(event->pmu);
1211 * Add the event to the list (if there is room)
1212 * and check whether the total set is still feasible.
1214 cpuhw = &__get_cpu_var(cpu_hw_events);
1215 n0 = cpuhw->n_events;
1216 if (n0 >= ppmu->n_counter)
1218 cpuhw->event[n0] = event;
1219 cpuhw->events[n0] = event->hw.config;
1220 cpuhw->flags[n0] = event->hw.event_base;
1223 * This event may have been disabled/stopped in record_and_restart()
1224 * because we exceeded the ->event_limit. If re-starting the event,
1225 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user
1226 * notification is re-enabled.
1228 if (!(ef_flags & PERF_EF_START))
1229 event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
1231 event->hw.state = 0;
1234 * If group events scheduling transaction was started,
1235 * skip the schedulability test here, it will be performed
1236 * at commit time(->commit_txn) as a whole
1238 if (cpuhw->group_flag & PERF_EVENT_TXN)
1241 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
1243 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
1245 event->hw.config = cpuhw->events[n0];
1248 ebb_event_add(event);
1255 if (has_branch_stack(event))
1256 power_pmu_bhrb_enable(event);
1258 perf_pmu_enable(event->pmu);
1259 local_irq_restore(flags);
1264 * Remove a event from the PMU.
1266 static void power_pmu_del(struct perf_event *event, int ef_flags)
1268 struct cpu_hw_events *cpuhw;
1270 unsigned long flags;
1272 local_irq_save(flags);
1273 perf_pmu_disable(event->pmu);
1275 power_pmu_read(event);
1277 cpuhw = &__get_cpu_var(cpu_hw_events);
1278 for (i = 0; i < cpuhw->n_events; ++i) {
1279 if (event == cpuhw->event[i]) {
1280 while (++i < cpuhw->n_events) {
1281 cpuhw->event[i-1] = cpuhw->event[i];
1282 cpuhw->events[i-1] = cpuhw->events[i];
1283 cpuhw->flags[i-1] = cpuhw->flags[i];
1286 ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr);
1287 if (event->hw.idx) {
1288 write_pmc(event->hw.idx, 0);
1291 perf_event_update_userpage(event);
1295 for (i = 0; i < cpuhw->n_limited; ++i)
1296 if (event == cpuhw->limited_counter[i])
1298 if (i < cpuhw->n_limited) {
1299 while (++i < cpuhw->n_limited) {
1300 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
1301 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
1305 if (cpuhw->n_events == 0) {
1306 /* disable exceptions if no events are running */
1307 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
1310 if (has_branch_stack(event))
1311 power_pmu_bhrb_disable(event);
1313 perf_pmu_enable(event->pmu);
1314 local_irq_restore(flags);
1318 * POWER-PMU does not support disabling individual counters, hence
1319 * program their cycle counter to their max value and ignore the interrupts.
1322 static void power_pmu_start(struct perf_event *event, int ef_flags)
1324 unsigned long flags;
1328 if (!event->hw.idx || !event->hw.sample_period)
1331 if (!(event->hw.state & PERF_HES_STOPPED))
1334 if (ef_flags & PERF_EF_RELOAD)
1335 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1337 local_irq_save(flags);
1338 perf_pmu_disable(event->pmu);
1340 event->hw.state = 0;
1341 left = local64_read(&event->hw.period_left);
1344 if (left < 0x80000000L)
1345 val = 0x80000000L - left;
1347 write_pmc(event->hw.idx, val);
1349 perf_event_update_userpage(event);
1350 perf_pmu_enable(event->pmu);
1351 local_irq_restore(flags);
1354 static void power_pmu_stop(struct perf_event *event, int ef_flags)
1356 unsigned long flags;
1358 if (!event->hw.idx || !event->hw.sample_period)
1361 if (event->hw.state & PERF_HES_STOPPED)
1364 local_irq_save(flags);
1365 perf_pmu_disable(event->pmu);
1367 power_pmu_read(event);
1368 event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
1369 write_pmc(event->hw.idx, 0);
1371 perf_event_update_userpage(event);
1372 perf_pmu_enable(event->pmu);
1373 local_irq_restore(flags);
1377 * Start group events scheduling transaction
1378 * Set the flag to make pmu::enable() not perform the
1379 * schedulability test, it will be performed at commit time
1381 void power_pmu_start_txn(struct pmu *pmu)
1383 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1385 perf_pmu_disable(pmu);
1386 cpuhw->group_flag |= PERF_EVENT_TXN;
1387 cpuhw->n_txn_start = cpuhw->n_events;
1391 * Stop group events scheduling transaction
1392 * Clear the flag and pmu::enable() will perform the
1393 * schedulability test.
1395 void power_pmu_cancel_txn(struct pmu *pmu)
1397 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1399 cpuhw->group_flag &= ~PERF_EVENT_TXN;
1400 perf_pmu_enable(pmu);
1404 * Commit group events scheduling transaction
1405 * Perform the group schedulability test as a whole
1406 * Return 0 if success
1408 int power_pmu_commit_txn(struct pmu *pmu)
1410 struct cpu_hw_events *cpuhw;
1415 cpuhw = &__get_cpu_var(cpu_hw_events);
1416 n = cpuhw->n_events;
1417 if (check_excludes(cpuhw->event, cpuhw->flags, 0, n))
1419 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n);
1423 for (i = cpuhw->n_txn_start; i < n; ++i)
1424 cpuhw->event[i]->hw.config = cpuhw->events[i];
1426 cpuhw->group_flag &= ~PERF_EVENT_TXN;
1427 perf_pmu_enable(pmu);
1432 * Return 1 if we might be able to put event on a limited PMC,
1434 * A event can only go on a limited PMC if it counts something
1435 * that a limited PMC can count, doesn't require interrupts, and
1436 * doesn't exclude any processor mode.
1438 static int can_go_on_limited_pmc(struct perf_event *event, u64 ev,
1442 u64 alt[MAX_EVENT_ALTERNATIVES];
1444 if (event->attr.exclude_user
1445 || event->attr.exclude_kernel
1446 || event->attr.exclude_hv
1447 || event->attr.sample_period)
1450 if (ppmu->limited_pmc_event(ev))
1454 * The requested event_id isn't on a limited PMC already;
1455 * see if any alternative code goes on a limited PMC.
1457 if (!ppmu->get_alternatives)
1460 flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
1461 n = ppmu->get_alternatives(ev, flags, alt);
1467 * Find an alternative event_id that goes on a normal PMC, if possible,
1468 * and return the event_id code, or 0 if there is no such alternative.
1469 * (Note: event_id code 0 is "don't count" on all machines.)
1471 static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
1473 u64 alt[MAX_EVENT_ALTERNATIVES];
1476 flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
1477 n = ppmu->get_alternatives(ev, flags, alt);
1483 /* Number of perf_events counting hardware events */
1484 static atomic_t num_events;
1485 /* Used to avoid races in calling reserve/release_pmc_hardware */
1486 static DEFINE_MUTEX(pmc_reserve_mutex);
1489 * Release the PMU if this is the last perf_event.
1491 static void hw_perf_event_destroy(struct perf_event *event)
1493 if (!atomic_add_unless(&num_events, -1, 1)) {
1494 mutex_lock(&pmc_reserve_mutex);
1495 if (atomic_dec_return(&num_events) == 0)
1496 release_pmc_hardware();
1497 mutex_unlock(&pmc_reserve_mutex);
1502 * Translate a generic cache event_id config to a raw event_id code.
1504 static int hw_perf_cache_event(u64 config, u64 *eventp)
1506 unsigned long type, op, result;
1509 if (!ppmu->cache_events)
1513 type = config & 0xff;
1514 op = (config >> 8) & 0xff;
1515 result = (config >> 16) & 0xff;
1517 if (type >= PERF_COUNT_HW_CACHE_MAX ||
1518 op >= PERF_COUNT_HW_CACHE_OP_MAX ||
1519 result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1522 ev = (*ppmu->cache_events)[type][op][result];
1531 static int power_pmu_event_init(struct perf_event *event)
1534 unsigned long flags;
1535 struct perf_event *ctrs[MAX_HWEVENTS];
1536 u64 events[MAX_HWEVENTS];
1537 unsigned int cflags[MAX_HWEVENTS];
1540 struct cpu_hw_events *cpuhw;
1545 if (has_branch_stack(event)) {
1546 /* PMU has BHRB enabled */
1547 if (!(ppmu->flags & PPMU_BHRB))
1551 switch (event->attr.type) {
1552 case PERF_TYPE_HARDWARE:
1553 ev = event->attr.config;
1554 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
1556 ev = ppmu->generic_events[ev];
1558 case PERF_TYPE_HW_CACHE:
1559 err = hw_perf_cache_event(event->attr.config, &ev);
1564 ev = event->attr.config;
1570 event->hw.config_base = ev;
1574 * If we are not running on a hypervisor, force the
1575 * exclude_hv bit to 0 so that we don't care what
1576 * the user set it to.
1578 if (!firmware_has_feature(FW_FEATURE_LPAR))
1579 event->attr.exclude_hv = 0;
1582 * If this is a per-task event, then we can use
1583 * PM_RUN_* events interchangeably with their non RUN_*
1584 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
1585 * XXX we should check if the task is an idle task.
1588 if (event->attach_state & PERF_ATTACH_TASK)
1589 flags |= PPMU_ONLY_COUNT_RUN;
1592 * If this machine has limited events, check whether this
1593 * event_id could go on a limited event.
1595 if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
1596 if (can_go_on_limited_pmc(event, ev, flags)) {
1597 flags |= PPMU_LIMITED_PMC_OK;
1598 } else if (ppmu->limited_pmc_event(ev)) {
1600 * The requested event_id is on a limited PMC,
1601 * but we can't use a limited PMC; see if any
1602 * alternative goes on a normal PMC.
1604 ev = normal_pmc_alternative(ev, flags);
1610 /* Extra checks for EBB */
1611 err = ebb_event_check(event);
1616 * If this is in a group, check if it can go on with all the
1617 * other hardware events in the group. We assume the event
1618 * hasn't been linked into its leader's sibling list at this point.
1621 if (event->group_leader != event) {
1622 n = collect_events(event->group_leader, ppmu->n_counter - 1,
1623 ctrs, events, cflags);
1630 if (check_excludes(ctrs, cflags, n, 1))
1633 cpuhw = &get_cpu_var(cpu_hw_events);
1634 err = power_check_constraints(cpuhw, events, cflags, n + 1);
1636 if (has_branch_stack(event)) {
1637 cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
1638 event->attr.branch_sample_type);
1640 if(cpuhw->bhrb_filter == -1)
1644 put_cpu_var(cpu_hw_events);
1648 event->hw.config = events[n];
1649 event->hw.event_base = cflags[n];
1650 event->hw.last_period = event->hw.sample_period;
1651 local64_set(&event->hw.period_left, event->hw.last_period);
1654 * For EBB events we just context switch the PMC value, we don't do any
1655 * of the sample_period logic. We use hw.prev_count for this.
1657 if (is_ebb_event(event))
1658 local64_set(&event->hw.prev_count, 0);
1661 * See if we need to reserve the PMU.
1662 * If no events are currently in use, then we have to take a
1663 * mutex to ensure that we don't race with another task doing
1664 * reserve_pmc_hardware or release_pmc_hardware.
1667 if (!atomic_inc_not_zero(&num_events)) {
1668 mutex_lock(&pmc_reserve_mutex);
1669 if (atomic_read(&num_events) == 0 &&
1670 reserve_pmc_hardware(perf_event_interrupt))
1673 atomic_inc(&num_events);
1674 mutex_unlock(&pmc_reserve_mutex);
1676 event->destroy = hw_perf_event_destroy;
1681 static int power_pmu_event_idx(struct perf_event *event)
1683 return event->hw.idx;
1686 ssize_t power_events_sysfs_show(struct device *dev,
1687 struct device_attribute *attr, char *page)
1689 struct perf_pmu_events_attr *pmu_attr;
1691 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
1693 return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
1696 struct pmu power_pmu = {
1697 .pmu_enable = power_pmu_enable,
1698 .pmu_disable = power_pmu_disable,
1699 .event_init = power_pmu_event_init,
1700 .add = power_pmu_add,
1701 .del = power_pmu_del,
1702 .start = power_pmu_start,
1703 .stop = power_pmu_stop,
1704 .read = power_pmu_read,
1705 .start_txn = power_pmu_start_txn,
1706 .cancel_txn = power_pmu_cancel_txn,
1707 .commit_txn = power_pmu_commit_txn,
1708 .event_idx = power_pmu_event_idx,
1709 .flush_branch_stack = power_pmu_flush_branch_stack,
1713 * A counter has overflowed; update its count and record
1714 * things if requested. Note that interrupts are hard-disabled
1715 * here so there is no possibility of being interrupted.
1717 static void record_and_restart(struct perf_event *event, unsigned long val,
1718 struct pt_regs *regs)
1720 u64 period = event->hw.sample_period;
1721 s64 prev, delta, left;
1724 if (event->hw.state & PERF_HES_STOPPED) {
1725 write_pmc(event->hw.idx, 0);
1729 /* we don't have to worry about interrupts here */
1730 prev = local64_read(&event->hw.prev_count);
1731 delta = check_and_compute_delta(prev, val);
1732 local64_add(delta, &event->count);
1735 * See if the total period for this event has expired,
1736 * and update for the next period.
1739 left = local64_read(&event->hw.period_left) - delta;
1747 record = siar_valid(regs);
1748 event->hw.last_period = event->hw.sample_period;
1750 if (left < 0x80000000LL)
1751 val = 0x80000000LL - left;
1754 write_pmc(event->hw.idx, val);
1755 local64_set(&event->hw.prev_count, val);
1756 local64_set(&event->hw.period_left, left);
1757 perf_event_update_userpage(event);
1760 * Finally record data if requested.
1763 struct perf_sample_data data;
1765 perf_sample_data_init(&data, ~0ULL, event->hw.last_period);
1767 if (event->attr.sample_type & PERF_SAMPLE_ADDR)
1768 perf_get_data_addr(regs, &data.addr);
1770 if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) {
1771 struct cpu_hw_events *cpuhw;
1772 cpuhw = &__get_cpu_var(cpu_hw_events);
1773 power_pmu_bhrb_read(cpuhw);
1774 data.br_stack = &cpuhw->bhrb_stack;
1777 if (perf_event_overflow(event, &data, regs))
1778 power_pmu_stop(event, 0);
1783 * Called from generic code to get the misc flags (i.e. processor mode)
1786 unsigned long perf_misc_flags(struct pt_regs *regs)
1788 u32 flags = perf_get_misc_flags(regs);
1792 return user_mode(regs) ? PERF_RECORD_MISC_USER :
1793 PERF_RECORD_MISC_KERNEL;
1797 * Called from generic code to get the instruction pointer
1800 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1802 bool use_siar = regs_use_siar(regs);
1804 if (use_siar && siar_valid(regs))
1805 return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
1807 return 0; // no valid instruction pointer
1812 static bool pmc_overflow_power7(unsigned long val)
1815 * Events on POWER7 can roll back if a speculative event doesn't
1816 * eventually complete. Unfortunately in some rare cases they will
1817 * raise a performance monitor exception. We need to catch this to
1818 * ensure we reset the PMC. In all cases the PMC will be 256 or less
1819 * cycles from overflow.
1821 * We only do this if the first pass fails to find any overflowing
1822 * PMCs because a user might set a period of less than 256 and we
1823 * don't want to mistakenly reset them.
1825 if ((0x80000000 - val) <= 256)
1831 static bool pmc_overflow(unsigned long val)
1840 * Performance monitor interrupt stuff
1842 static void perf_event_interrupt(struct pt_regs *regs)
1845 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1846 struct perf_event *event;
1847 unsigned long val[8];
1851 if (cpuhw->n_limited)
1852 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
1855 perf_read_regs(regs);
1857 nmi = perf_intr_is_nmi(regs);
1863 /* Read all the PMCs since we'll need them a bunch of times */
1864 for (i = 0; i < ppmu->n_counter; ++i)
1865 val[i] = read_pmc(i + 1);
1867 /* Try to find what caused the IRQ */
1869 for (i = 0; i < ppmu->n_counter; ++i) {
1870 if (!pmc_overflow(val[i]))
1872 if (is_limited_pmc(i + 1))
1873 continue; /* these won't generate IRQs */
1875 * We've found one that's overflowed. For active
1876 * counters we need to log this. For inactive
1877 * counters, we need to reset it anyway
1881 for (j = 0; j < cpuhw->n_events; ++j) {
1882 event = cpuhw->event[j];
1883 if (event->hw.idx == (i + 1)) {
1885 record_and_restart(event, val[i], regs);
1890 /* reset non active counters that have overflowed */
1891 write_pmc(i + 1, 0);
1893 if (!found && pvr_version_is(PVR_POWER7)) {
1894 /* check active counters for special buggy p7 overflow */
1895 for (i = 0; i < cpuhw->n_events; ++i) {
1896 event = cpuhw->event[i];
1897 if (!event->hw.idx || is_limited_pmc(event->hw.idx))
1899 if (pmc_overflow_power7(val[event->hw.idx - 1])) {
1900 /* event has overflowed in a buggy way*/
1902 record_and_restart(event,
1903 val[event->hw.idx - 1],
1908 if (!found && !nmi && printk_ratelimit())
1909 printk(KERN_WARNING "Can't find PMC that caused IRQ\n");
1912 * Reset MMCR0 to its normal value. This will set PMXE and
1913 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
1914 * and thus allow interrupts to occur again.
1915 * XXX might want to use MSR.PM to keep the events frozen until
1916 * we get back out of this interrupt.
1918 write_mmcr0(cpuhw, cpuhw->mmcr[0]);
1926 static void power_pmu_setup(int cpu)
1928 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
1932 memset(cpuhw, 0, sizeof(*cpuhw));
1933 cpuhw->mmcr[0] = MMCR0_FC;
1937 power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1939 unsigned int cpu = (long)hcpu;
1941 switch (action & ~CPU_TASKS_FROZEN) {
1942 case CPU_UP_PREPARE:
1943 power_pmu_setup(cpu);
1953 int register_power_pmu(struct power_pmu *pmu)
1956 return -EBUSY; /* something's already registered */
1959 pr_info("%s performance monitor hardware support registered\n",
1962 power_pmu.attr_groups = ppmu->attr_groups;
1966 * Use FCHV to ignore kernel events if MSR.HV is set.
1968 if (mfmsr() & MSR_HV)
1969 freeze_events_kernel = MMCR0_FCHV;
1970 #endif /* CONFIG_PPC64 */
1972 perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW);
1973 perf_cpu_notifier(power_pmu_notifier);