2 * Low-level SLB routines
4 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
6 * Based on earlier C version:
7 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
8 * Copyright (c) 2001 Dave Engebretsen
9 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <asm/processor.h>
18 #include <asm/ppc_asm.h>
19 #include <asm/asm-offsets.h>
20 #include <asm/cputable.h>
23 #include <asm/pgtable.h>
24 #include <asm/firmware.h>
27 * This macro generates asm code to compute the VSID scramble
28 * function. Used in slb_allocate() and do_stab_bolted. The function
29 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
31 * rt = register containing the proto-VSID and into which the
33 * rx = scratch register (clobbered)
36 * - rt and rx must be different registers
37 * - The answer will end up in the low VSID_BITS bits of rt. The higher
38 * bits may contain other garbage, so you may need to mask the
41 #define ASM_VSID_SCRAMBLE(rt, rx, rf, size) \
42 lis rx,VSID_MULTIPLIER_##size@h; \
43 ori rx,rx,VSID_MULTIPLIER_##size@l; \
44 mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
46 * powermac get slb fault before feature fixup, so make 65 bit part \
47 * the default part of feature fixup \
49 BEGIN_MMU_FTR_SECTION \
50 srdi rx,rt,VSID_BITS_65_##size; \
51 clrldi rt,rt,(64-VSID_BITS_65_##size); \
54 srdi rx,rx,VSID_BITS_65_##size; \
56 rldimi rf,rt,SLB_VSID_SHIFT_##size,(64 - (SLB_VSID_SHIFT_##size + VSID_BITS_65_##size)); \
57 MMU_FTR_SECTION_ELSE \
58 srdi rx,rt,VSID_BITS_##size; \
59 clrldi rt,rt,(64-VSID_BITS_##size); \
60 add rt,rt,rx; /* add high and low bits */ \
62 srdi rx,rx,VSID_BITS_##size; /* extract 2^VSID_BITS bit */ \
64 rldimi rf,rt,SLB_VSID_SHIFT_##size,(64 - (SLB_VSID_SHIFT_##size + VSID_BITS_##size)); \
65 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_68_BIT_VA)
68 /* void slb_allocate(unsigned long ea);
70 * Create an SLB entry for the given EA (user or kernel).
71 * r3 = faulting address, r13 = PACA
72 * r9, r10, r11 are clobbered by this function
74 * No other registers are examined or changed.
78 * check for bad kernel/user address
79 * (ea & ~REGION_MASK) >= PGTABLE_RANGE
81 rldicr. r9,r3,4,(63 - H_PGTABLE_EADDR_SIZE - 4)
84 srdi r9,r3,60 /* get region */
85 srdi r10,r3,SID_SHIFT /* get esid */
86 cmpldi cr7,r9,0xc /* cmp PAGE_OFFSET for later use */
88 /* r3 = address, r10 = esid, cr7 = <> PAGE_OFFSET */
89 blt cr7,0f /* user or kernel? */
91 /* Check if hitting the linear mapping or some other kernel space
95 /* Linear mapping encoding bits, the "li" instruction below will
96 * be patched by the kernel at boot
98 .globl slb_miss_kernel_load_linear
99 slb_miss_kernel_load_linear:
102 * context = (ea >> 60) - (0xc - 1)
105 subi r9,r9,KERNEL_REGION_CONTEXT_OFFSET
109 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
110 b .Lslb_finish_load_1T
113 #ifdef CONFIG_SPARSEMEM_VMEMMAP
116 /* Check virtual memmap region. To be patched at kernel boot */
117 .globl slb_miss_kernel_load_vmemmap
118 slb_miss_kernel_load_vmemmap:
122 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
124 /* vmalloc mapping gets the encoding from the PACA as the mapping
125 * can be demoted from 64K -> 4K dynamically on some machines
128 cmpldi r11,(H_VMALLOC_SIZE >> 28) - 1
130 lhz r11,PACAVMALLOCSLLP(r13)
134 .globl slb_miss_kernel_load_io
135 slb_miss_kernel_load_io:
139 * context = (ea >> 60) - (0xc - 1)
142 subi r9,r9,KERNEL_REGION_CONTEXT_OFFSET
146 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
147 b .Lslb_finish_load_1T
150 * For userspace addresses, make sure this is region 0.
155 * user space make sure we are within the allowed limit
157 ld r11,PACA_ADDR_LIMIT(r13)
161 /* when using slices, we extract the psize off the slice bitmaps
162 * and then we need to get the sllp encoding off the mmu_psize_defs
165 * XXX This is a bit inefficient especially for the normal case,
166 * so we should try to implement a fast path for the standard page
167 * size using the old sllp value so we avoid the array. We cannot
168 * really do dynamic patching unfortunately as processes might flip
169 * between 4k and 64k standard page size
171 #ifdef CONFIG_PPC_MM_SLICES
174 /* below SLICE_LOW_TOP */
178 * r9 is get_paca()->context.high_slices_psize[index], r11 is mask_index
180 srdi r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT + 1) /* index */
181 addi r9,r11,PACAHIGHSLICEPSIZE
182 lbzx r9,r13,r9 /* r9 is hpsizes[r11] */
183 /* r11 = (r10 >> (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)) & 0x1 */
184 rldicl r11,r10,(64 - (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)),63
190 * r9 is get_paca()->context.low_slices_psize, r11 is index
192 ld r9,PACALOWSLICESPSIZE(r13)
195 sldi r11,r11,2 /* index * 4 */
196 /* Extract the psize and multiply to get an array offset */
199 mulli r9,r9,MMUPSIZEDEFSIZE
201 /* Now get to the array and obtain the sllp
204 ld r11,mmu_psize_defs@got(r11)
206 ld r11,MMUPSIZESLLP(r11)
207 ori r11,r11,SLB_VSID_USER
209 /* paca context sllp already contains the SLB_VSID_USER bits */
210 lhz r11,PACACONTEXTSLLP(r13)
211 #endif /* CONFIG_PPC_MM_SLICES */
213 ld r9,PACACONTEXTID(r13)
216 bge .Lslb_finish_load_1T
217 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
220 8: /* invalid EA - return an error indication */
221 crset 4*cr0+eq /* indicate failure */
225 * Finish loading of an SLB entry and return
227 * r3 = EA, r9 = context, r10 = ESID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET
230 rldimi r10,r9,ESID_BITS,0
231 ASM_VSID_SCRAMBLE(r10,r9,r11,256M)
232 /* r3 = EA, r11 = VSID data */
234 * Find a slot, round robin. Previously we tried to find a
235 * free slot first but that took too long. Unfortunately we
236 * dont have any LRU information to help us choose a slot.
241 /* slb_finish_load_1T continues here. r9=EA with non-ESID bits clear */
242 7: ld r10,PACASTABRR(r13)
244 /* This gets soft patched on boot. */
245 .globl slb_compare_rr_to_size
246 slb_compare_rr_to_size:
250 li r10,SLB_NUM_BOLTED
253 std r10,PACASTABRR(r13)
256 rldimi r9,r10,0,36 /* r9 = EA[0:35] | entry */
257 oris r10,r9,SLB_ESID_V@h /* r10 = r9 | SLB_ESID_V */
259 /* r9 = ESID data, r11 = VSID data */
262 * No need for an isync before or after this slbmte. The exception
263 * we enter with and the rfid we exit with are context synchronizing.
267 /* we're done for kernel addresses */
268 crclr 4*cr0+eq /* set result to "success" */
271 /* Update the slb cache */
272 lhz r9,PACASLBCACHEPTR(r13) /* offset = paca->slb_cache_ptr */
273 cmpldi r9,SLB_CACHE_ENTRIES
276 /* still room in the slb cache */
277 sldi r11,r9,2 /* r11 = offset * sizeof(u32) */
278 srdi r10,r10,28 /* get the 36 bits of the ESID */
279 add r11,r11,r13 /* r11 = (u32 *)paca + offset */
280 stw r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
281 addi r9,r9,1 /* offset++ */
283 1: /* offset >= SLB_CACHE_ENTRIES */
284 li r9,SLB_CACHE_ENTRIES+1
286 sth r9,PACASLBCACHEPTR(r13) /* paca->slb_cache_ptr = offset */
287 crclr 4*cr0+eq /* set result to "success" */
291 * Finish loading of a 1T SLB entry (for the kernel linear mapping) and return.
293 * r3 = EA, r9 = context, r10 = ESID(256MB), r11 = flags, clobbers r9
295 .Lslb_finish_load_1T:
296 srdi r10,r10,(SID_SHIFT_1T - SID_SHIFT) /* get 1T ESID */
297 rldimi r10,r9,ESID_BITS_1T,0
298 ASM_VSID_SCRAMBLE(r10,r9,r11,1T)
300 * bits above VSID_BITS_1T need to be ignored from r10
301 * also combine VSID and flags
304 li r10,MMU_SEGSIZE_1T
305 rldimi r11,r10,SLB_VSID_SSIZE_SHIFT,0 /* insert segment size */
307 /* r3 = EA, r11 = VSID data */
308 clrrdi r9,r3,SID_SHIFT_1T /* clear out non-ESID bits */
312 _ASM_NOKPROBE_SYMBOL(slb_allocate)
313 _ASM_NOKPROBE_SYMBOL(slb_miss_kernel_load_linear)
314 _ASM_NOKPROBE_SYMBOL(slb_miss_kernel_load_io)
315 _ASM_NOKPROBE_SYMBOL(slb_compare_rr_to_size)
316 #ifdef CONFIG_SPARSEMEM_VMEMMAP
317 _ASM_NOKPROBE_SYMBOL(slb_miss_kernel_load_vmemmap)