2 * This file contains the routines for handling the MMU on those
3 * PowerPC implementations where the MMU substantially follows the
4 * architecture specification. This includes the 6xx, 7xx, 7xxx,
5 * and 8260 implementations but excludes the 8xx and 4xx.
8 * Derived from arch/ppc/mm/init.c:
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
12 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
13 * Copyright (C) 1996 Paul Mackerras
15 * Derived from "arch/i386/mm/init.c"
16 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
25 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/highmem.h>
29 #include <linux/memblock.h>
33 #include <asm/machdep.h>
34 #include <asm/code-patching.h>
35 #include <asm/sections.h>
39 struct hash_pte *Hash, *Hash_end;
40 unsigned long Hash_size, Hash_mask;
43 struct ppc_bat BATS[8][2]; /* 8 pairs of IBAT, DBAT */
45 struct batrange { /* stores address ranges mapped by BATs */
52 * Return PA for this VA if it is mapped by a BAT, or 0
54 phys_addr_t v_block_mapped(unsigned long va)
57 for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)
58 if (va >= bat_addrs[b].start && va < bat_addrs[b].limit)
59 return bat_addrs[b].phys + (va - bat_addrs[b].start);
64 * Return VA for a given PA or 0 if not mapped
66 unsigned long p_block_mapped(phys_addr_t pa)
69 for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)
70 if (pa >= bat_addrs[b].phys
71 && pa < (bat_addrs[b].limit-bat_addrs[b].start)
73 return bat_addrs[b].start+(pa-bat_addrs[b].phys);
77 static int find_free_bat(void)
81 if (cpu_has_feature(CPU_FTR_601)) {
82 for (b = 0; b < 4; b++) {
83 struct ppc_bat *bat = BATS[b];
85 if (!(bat[0].batl & 0x40))
89 int n = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
91 for (b = 0; b < n; b++) {
92 struct ppc_bat *bat = BATS[b];
94 if (!(bat[1].batu & 3))
101 static unsigned int block_size(unsigned long base, unsigned long top)
103 unsigned int max_size = (cpu_has_feature(CPU_FTR_601) ? 8 : 256) << 20;
104 unsigned int base_shift = (fls(base) - 1) & 31;
105 unsigned int block_shift = (fls(top - base) - 1) & 31;
107 return min3(max_size, 1U << base_shift, 1U << block_shift);
111 * Set up one of the IBAT (block address translation) register pairs.
112 * The parameters are not checked; in particular size must be a power
113 * of 2 between 128k and 256M.
116 static void setibat(int index, unsigned long virt, phys_addr_t phys,
117 unsigned int size, pgprot_t prot)
119 unsigned int bl = (size >> 17) - 1;
121 struct ppc_bat *bat = BATS[index];
122 unsigned long flags = pgprot_val(prot);
124 if (!cpu_has_feature(CPU_FTR_NEED_COHERENT))
125 flags &= ~_PAGE_COHERENT;
127 wimgxpp = (flags & _PAGE_COHERENT) | (_PAGE_EXEC ? BPP_RX : BPP_XX);
128 bat[0].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
129 bat[0].batl = BAT_PHYS_ADDR(phys) | wimgxpp;
130 if (flags & _PAGE_USER)
131 bat[0].batu |= 1; /* Vp = 1 */
134 static void clearibat(int index)
136 struct ppc_bat *bat = BATS[index];
142 static unsigned long __init __mmu_mapin_ram(unsigned long base, unsigned long top)
146 while ((idx = find_free_bat()) != -1 && base != top) {
147 unsigned int size = block_size(base, top);
149 if (size < 128 << 10)
151 setbat(idx, PAGE_OFFSET + base, base, size, PAGE_KERNEL_X);
158 unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
161 unsigned long border = (unsigned long)__init_begin - PAGE_OFFSET;
163 if (__map_without_bats) {
164 pr_debug("RAM mapped without BATs\n");
168 if (!strict_kernel_rwx_enabled() || base >= border || top <= border)
169 return __mmu_mapin_ram(base, top);
171 done = __mmu_mapin_ram(base, border);
172 if (done != border - base)
175 return done + __mmu_mapin_ram(border, top);
178 void mmu_mark_initmem_nx(void)
180 int nb = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
182 unsigned long base = (unsigned long)_stext - PAGE_OFFSET;
183 unsigned long top = (unsigned long)_etext - PAGE_OFFSET;
186 if (cpu_has_feature(CPU_FTR_601))
189 for (i = 0; i < nb - 1 && base < top && top - base > (128 << 10);) {
190 size = block_size(base, top);
191 setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT);
195 size = block_size(base, top);
196 size = max(size, 128UL << 10);
197 if ((top - base) > size) {
198 if (strict_kernel_rwx_enabled())
199 pr_warn("Kernel _etext not properly aligned\n");
202 setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT);
210 for (i = TASK_SIZE >> 28; i < 16; i++) {
211 /* Do not set NX on VM space for modules */
212 if (IS_ENABLED(CONFIG_MODULES) &&
213 (VMALLOC_START & 0xf0000000) == i << 28)
215 mtsrin(mfsrin(i << 28) | 0x10000000, i << 28);
219 void mmu_mark_rodata_ro(void)
221 int nb = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
224 if (cpu_has_feature(CPU_FTR_601))
227 for (i = 0; i < nb; i++) {
228 struct ppc_bat *bat = BATS[i];
230 if (bat_addrs[i].start < (unsigned long)__init_begin)
231 bat[1].batl = (bat[1].batl & ~BPP_RW) | BPP_RX;
238 * Set up one of the I/D BAT (block address translation) register pairs.
239 * The parameters are not checked; in particular size must be a power
240 * of 2 between 128k and 256M.
241 * On 603+, only set IBAT when _PAGE_EXEC is set
243 void __init setbat(int index, unsigned long virt, phys_addr_t phys,
244 unsigned int size, pgprot_t prot)
248 struct ppc_bat *bat = BATS[index];
249 unsigned long flags = pgprot_val(prot);
251 if ((flags & _PAGE_NO_CACHE) ||
252 (cpu_has_feature(CPU_FTR_NEED_COHERENT) == 0))
253 flags &= ~_PAGE_COHERENT;
255 bl = (size >> 17) - 1;
256 if (PVR_VER(mfspr(SPRN_PVR)) != 1) {
259 wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
260 | _PAGE_COHERENT | _PAGE_GUARDED);
261 wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
262 bat[1].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
263 bat[1].batl = BAT_PHYS_ADDR(phys) | wimgxpp;
264 if (flags & _PAGE_USER)
265 bat[1].batu |= 1; /* Vp = 1 */
266 if (flags & _PAGE_GUARDED) {
267 /* G bit must be zero in IBATs */
268 flags &= ~_PAGE_EXEC;
270 if (flags & _PAGE_EXEC)
273 bat[0].batu = bat[0].batl = 0;
278 wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
280 wimgxpp |= (flags & _PAGE_RW)?
281 ((flags & _PAGE_USER)? PP_RWRW: PP_RWXX): PP_RXRX;
282 bat->batu = virt | wimgxpp | 4; /* Ks=0, Ku=1 */
283 bat->batl = phys | bl | 0x40; /* V=1 */
286 bat_addrs[index].start = virt;
287 bat_addrs[index].limit = virt + ((bl + 1) << 17) - 1;
288 bat_addrs[index].phys = phys;
292 * Preload a translation in the hash table
294 void hash_preload(struct mm_struct *mm, unsigned long ea,
295 bool is_exec, unsigned long trap)
301 pmd = pmd_offset(pud_offset(pgd_offset(mm, ea), ea), ea);
303 add_hash_page(mm->context.id, ea, pmd_val(*pmd));
307 * Initialize the hash table and patch the instructions in hashtable.S.
309 void __init MMU_init_hw(void)
311 unsigned int hmask, mb, mb2;
312 unsigned int n_hpteg, lg_n_hpteg;
314 if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
317 if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);
319 #define LG_HPTEG_SIZE 6 /* 64 bytes per HPTEG */
320 #define SDR1_LOW_BITS ((n_hpteg - 1) >> 10)
321 #define MIN_N_HPTEG 1024 /* min 64kB hash table */
324 * Allow 1 HPTE (1/8 HPTEG) for each page of memory.
325 * This is less than the recommended amount, but then
328 n_hpteg = total_memory / (PAGE_SIZE * 8);
329 if (n_hpteg < MIN_N_HPTEG)
330 n_hpteg = MIN_N_HPTEG;
331 lg_n_hpteg = __ilog2(n_hpteg);
332 if (n_hpteg & (n_hpteg - 1)) {
333 ++lg_n_hpteg; /* round up if not power of 2 */
334 n_hpteg = 1 << lg_n_hpteg;
336 Hash_size = n_hpteg << LG_HPTEG_SIZE;
339 * Find some memory for the hash table.
341 if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);
342 Hash = memblock_alloc(Hash_size, Hash_size);
344 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
345 __func__, Hash_size, Hash_size);
346 _SDR1 = __pa(Hash) | SDR1_LOW_BITS;
348 Hash_end = (struct hash_pte *) ((unsigned long)Hash + Hash_size);
350 printk("Total memory = %lldMB; using %ldkB for hash table (at %p)\n",
351 (unsigned long long)(total_memory >> 20), Hash_size >> 10, Hash);
355 * Patch up the instructions in hashtable.S:create_hpte
357 if ( ppc_md.progress ) ppc_md.progress("hash:patch", 0x345);
358 Hash_mask = n_hpteg - 1;
359 hmask = Hash_mask >> (16 - LG_HPTEG_SIZE);
360 mb2 = mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg;
362 mb2 = 16 - LG_HPTEG_SIZE;
364 modify_instruction_site(&patch__hash_page_A0, 0xffff,
365 ((unsigned int)Hash - PAGE_OFFSET) >> 16);
366 modify_instruction_site(&patch__hash_page_A1, 0x7c0, mb << 6);
367 modify_instruction_site(&patch__hash_page_A2, 0x7c0, mb2 << 6);
368 modify_instruction_site(&patch__hash_page_B, 0xffff, hmask);
369 modify_instruction_site(&patch__hash_page_C, 0xffff, hmask);
372 * Patch up the instructions in hashtable.S:flush_hash_page
374 modify_instruction_site(&patch__flush_hash_A0, 0xffff,
375 ((unsigned int)Hash - PAGE_OFFSET) >> 16);
376 modify_instruction_site(&patch__flush_hash_A1, 0x7c0, mb << 6);
377 modify_instruction_site(&patch__flush_hash_A2, 0x7c0, mb2 << 6);
378 modify_instruction_site(&patch__flush_hash_B, 0xffff, hmask);
380 if ( ppc_md.progress ) ppc_md.progress("hash:done", 0x205);
383 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
384 phys_addr_t first_memblock_size)
386 /* We don't currently support the first MEMBLOCK not mapping 0
387 * physical on those processors
389 BUG_ON(first_memblock_base != 0);
391 /* 601 can only access 16MB at the moment */
392 if (PVR_VER(mfspr(SPRN_PVR)) == 1)
393 memblock_set_current_limit(min_t(u64, first_memblock_size, 0x01000000));
394 else /* Anything else has 256M mapped */
395 memblock_set_current_limit(min_t(u64, first_memblock_size, 0x10000000));