2 * This file contains common routines for dealing with free of page tables
3 * Along with common page table handling code
5 * Derived from arch/powerpc/mm/tlb_64.c:
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
9 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
10 * Copyright (C) 1996 Paul Mackerras
12 * Derived from "arch/i386/mm/init.c"
13 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
15 * Dave Engebretsen <engebret@us.ibm.com>
16 * Rework for PPC64 port.
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version
21 * 2 of the License, or (at your option) any later version.
24 #include <linux/kernel.h>
25 #include <linux/gfp.h>
27 #include <linux/percpu.h>
28 #include <linux/hardirq.h>
29 #include <linux/hugetlb.h>
30 #include <asm/pgalloc.h>
31 #include <asm/tlbflush.h>
34 static inline int is_exec_fault(void)
36 return current->thread.regs && TRAP(current->thread.regs) == 0x400;
39 /* We only try to do i/d cache coherency on stuff that looks like
40 * reasonably "normal" PTEs. We currently require a PTE to be present
41 * and we avoid _PAGE_SPECIAL and cache inhibited pte. We also only do that
44 static inline int pte_looks_normal(pte_t pte)
47 #if defined(CONFIG_PPC_BOOK3S_64)
48 if ((pte_val(pte) & (_PAGE_PRESENT | _PAGE_SPECIAL)) == _PAGE_PRESENT) {
56 return (pte_val(pte) &
57 (_PAGE_PRESENT | _PAGE_SPECIAL | _PAGE_NO_CACHE | _PAGE_USER |
59 (_PAGE_PRESENT | _PAGE_USER);
63 static struct page *maybe_pte_to_page(pte_t pte)
65 unsigned long pfn = pte_pfn(pte);
68 if (unlikely(!pfn_valid(pfn)))
70 page = pfn_to_page(pfn);
71 if (PageReserved(page))
76 #if defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0
78 /* Server-style MMU handles coherency when hashing if HW exec permission
79 * is supposed per page (currently 64-bit only). If not, then, we always
80 * flush the cache for valid PTEs in set_pte. Embedded CPU without HW exec
81 * support falls into the same category.
84 static pte_t set_pte_filter(pte_t pte)
89 pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
90 if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
91 cpu_has_feature(CPU_FTR_NOEXECUTE))) {
92 struct page *pg = maybe_pte_to_page(pte);
95 if (!test_bit(PG_arch_1, &pg->flags)) {
96 flush_dcache_icache_page(pg);
97 set_bit(PG_arch_1, &pg->flags);
103 static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
109 #else /* defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0 */
111 /* Embedded type MMU with HW exec support. This is a bit more complicated
112 * as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so
113 * instead we "filter out" the exec permission for non clean pages.
115 static pte_t set_pte_filter(pte_t pte)
119 /* No exec permission in the first place, move on */
120 if (!(pte_val(pte) & _PAGE_EXEC) || !pte_looks_normal(pte))
123 /* If you set _PAGE_EXEC on weird pages you're on your own */
124 pg = maybe_pte_to_page(pte);
128 /* If the page clean, we move on */
129 if (test_bit(PG_arch_1, &pg->flags))
132 /* If it's an exec fault, we flush the cache and make it clean */
133 if (is_exec_fault()) {
134 flush_dcache_icache_page(pg);
135 set_bit(PG_arch_1, &pg->flags);
139 /* Else, we filter out _PAGE_EXEC */
140 return __pte(pte_val(pte) & ~_PAGE_EXEC);
143 static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
148 /* So here, we only care about exec faults, as we use them
149 * to recover lost _PAGE_EXEC and perform I$/D$ coherency
150 * if necessary. Also if _PAGE_EXEC is already set, same deal,
153 if (dirty || (pte_val(pte) & _PAGE_EXEC) || !is_exec_fault())
156 #ifdef CONFIG_DEBUG_VM
157 /* So this is an exec fault, _PAGE_EXEC is not set. If it was
158 * an error we would have bailed out earlier in do_page_fault()
159 * but let's make sure of it
161 if (WARN_ON(!(vma->vm_flags & VM_EXEC)))
163 #endif /* CONFIG_DEBUG_VM */
165 /* If you set _PAGE_EXEC on weird pages you're on your own */
166 pg = maybe_pte_to_page(pte);
170 /* If the page is already clean, we move on */
171 if (test_bit(PG_arch_1, &pg->flags))
174 /* Clean the page and set PG_arch_1 */
175 flush_dcache_icache_page(pg);
176 set_bit(PG_arch_1, &pg->flags);
179 return __pte(pte_val(pte) | _PAGE_EXEC);
182 #endif /* !(defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0) */
185 * set_pte stores a linux PTE into the linux page table.
187 void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
191 * Make sure hardware valid bit is not set. We don't do
192 * tlb flush for this update.
194 VM_WARN_ON(pte_val(*ptep) & _PAGE_PRESENT);
196 /* Add the pte bit when trying to set a pte */
197 pte = __pte(pte_val(pte) | _PAGE_PTE);
199 /* Note: mm->context.id might not yet have been assigned as
200 * this context might not have been activated yet when this
203 pte = set_pte_filter(pte);
205 /* Perform the setting of the PTE */
206 __set_pte_at(mm, addr, ptep, pte, 0);
210 * This is called when relaxing access to a PTE. It's also called in the page
211 * fault path when we don't hit any of the major fault cases, ie, a minor
212 * update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have
213 * handled those two for us, we additionally deal with missing execute
214 * permission here on some processors
216 int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
217 pte_t *ptep, pte_t entry, int dirty)
220 entry = set_access_flags_filter(entry, vma, dirty);
221 changed = !pte_same(*(ptep), entry);
223 assert_pte_locked(vma->vm_mm, address);
224 __ptep_set_access_flags(vma, ptep, entry,
225 address, mmu_virtual_psize);
230 #ifdef CONFIG_HUGETLB_PAGE
231 extern int huge_ptep_set_access_flags(struct vm_area_struct *vma,
232 unsigned long addr, pte_t *ptep,
233 pte_t pte, int dirty)
235 #ifdef HUGETLB_NEED_PRELOAD
237 * The "return 1" forces a call of update_mmu_cache, which will write a
238 * TLB entry. Without this, platforms that don't do a write of the TLB
239 * entry in the TLB miss handler asm will fault ad infinitum.
241 ptep_set_access_flags(vma, addr, ptep, pte, dirty);
246 pte = set_access_flags_filter(pte, vma, dirty);
247 changed = !pte_same(*(ptep), pte);
250 #ifdef CONFIG_PPC_BOOK3S_64
251 struct hstate *h = hstate_vma(vma);
253 psize = hstate_get_psize(h);
254 #ifdef CONFIG_DEBUG_VM
255 assert_spin_locked(huge_pte_lockptr(h, vma->vm_mm, ptep));
260 * Not used on non book3s64 platforms. But 8xx
261 * can possibly use tsize derived from hstate.
265 __ptep_set_access_flags(vma, ptep, pte, addr, psize);
270 #endif /* CONFIG_HUGETLB_PAGE */
272 #ifdef CONFIG_DEBUG_VM
273 void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
281 pgd = mm->pgd + pgd_index(addr);
282 BUG_ON(pgd_none(*pgd));
283 pud = pud_offset(pgd, addr);
284 BUG_ON(pud_none(*pud));
285 pmd = pmd_offset(pud, addr);
287 * khugepaged to collapse normal pages to hugepage, first set
288 * pmd to none to force page fault/gup to take mmap_sem. After
289 * pmd is set to none, we do a pte_clear which does this assertion
290 * so if we find pmd none, return.
294 BUG_ON(!pmd_present(*pmd));
295 assert_spin_locked(pte_lockptr(mm, pmd));
297 #endif /* CONFIG_DEBUG_VM */
299 unsigned long vmalloc_to_phys(void *va)
301 unsigned long pfn = vmalloc_to_pfn(va);
304 return __pa(pfn_to_kaddr(pfn)) + offset_in_page(va);
306 EXPORT_SYMBOL_GPL(vmalloc_to_phys);