2 * Page table handling routines for radix page table.
4 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #define pr_fmt(fmt) "radix-mmu: " fmt
14 #include <linux/kernel.h>
15 #include <linux/sched/mm.h>
16 #include <linux/memblock.h>
17 #include <linux/of_fdt.h>
19 #include <linux/string_helpers.h>
20 #include <linux/stop_machine.h>
22 #include <asm/pgtable.h>
23 #include <asm/pgalloc.h>
24 #include <asm/mmu_context.h>
26 #include <asm/machdep.h>
28 #include <asm/firmware.h>
29 #include <asm/powernv.h>
30 #include <asm/sections.h>
31 #include <asm/trace.h>
33 #include <trace/events/thp.h>
35 unsigned int mmu_pid_bits;
36 unsigned int mmu_base_pid;
38 static int native_register_process_table(unsigned long base, unsigned long pg_sz,
39 unsigned long table_size)
41 unsigned long patb0, patb1;
43 patb0 = be64_to_cpu(partition_tb[0].patb0);
44 patb1 = base | table_size | PATB_GR;
46 mmu_partition_table_set_entry(0, patb0, patb1);
51 static __ref void *early_alloc_pgtable(unsigned long size, int nid,
52 unsigned long region_start, unsigned long region_end)
54 phys_addr_t min_addr = MEMBLOCK_LOW_LIMIT;
55 phys_addr_t max_addr = MEMBLOCK_ALLOC_ANYWHERE;
59 min_addr = region_start;
61 max_addr = region_end;
63 ptr = memblock_alloc_try_nid(size, size, min_addr, max_addr, nid);
66 panic("%s: Failed to allocate %lu bytes align=0x%lx nid=%d from=%pa max_addr=%pa\n",
67 __func__, size, size, nid, &min_addr, &max_addr);
72 static int early_map_kernel_page(unsigned long ea, unsigned long pa,
74 unsigned int map_page_size,
76 unsigned long region_start, unsigned long region_end)
78 unsigned long pfn = pa >> PAGE_SHIFT;
84 pgdp = pgd_offset_k(ea);
85 if (pgd_none(*pgdp)) {
86 pudp = early_alloc_pgtable(PUD_TABLE_SIZE, nid,
87 region_start, region_end);
88 pgd_populate(&init_mm, pgdp, pudp);
90 pudp = pud_offset(pgdp, ea);
91 if (map_page_size == PUD_SIZE) {
95 if (pud_none(*pudp)) {
96 pmdp = early_alloc_pgtable(PMD_TABLE_SIZE, nid,
97 region_start, region_end);
98 pud_populate(&init_mm, pudp, pmdp);
100 pmdp = pmd_offset(pudp, ea);
101 if (map_page_size == PMD_SIZE) {
102 ptep = pmdp_ptep(pmdp);
105 if (!pmd_present(*pmdp)) {
106 ptep = early_alloc_pgtable(PAGE_SIZE, nid,
107 region_start, region_end);
108 pmd_populate_kernel(&init_mm, pmdp, ptep);
110 ptep = pte_offset_kernel(pmdp, ea);
113 set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
119 * nid, region_start, and region_end are hints to try to place the page
120 * table memory in the same node or region.
122 static int __map_kernel_page(unsigned long ea, unsigned long pa,
124 unsigned int map_page_size,
126 unsigned long region_start, unsigned long region_end)
128 unsigned long pfn = pa >> PAGE_SHIFT;
134 * Make sure task size is correct as per the max adddr
136 BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
138 if (unlikely(!slab_is_available()))
139 return early_map_kernel_page(ea, pa, flags, map_page_size,
140 nid, region_start, region_end);
143 * Should make page table allocation functions be able to take a
144 * node, so we can place kernel page tables on the right nodes after
147 pgdp = pgd_offset_k(ea);
148 pudp = pud_alloc(&init_mm, pgdp, ea);
151 if (map_page_size == PUD_SIZE) {
152 ptep = (pte_t *)pudp;
155 pmdp = pmd_alloc(&init_mm, pudp, ea);
158 if (map_page_size == PMD_SIZE) {
159 ptep = pmdp_ptep(pmdp);
162 ptep = pte_alloc_kernel(pmdp, ea);
167 set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
172 int radix__map_kernel_page(unsigned long ea, unsigned long pa,
174 unsigned int map_page_size)
176 return __map_kernel_page(ea, pa, flags, map_page_size, -1, 0, 0);
179 #ifdef CONFIG_STRICT_KERNEL_RWX
180 void radix__change_memory_range(unsigned long start, unsigned long end,
189 start = ALIGN_DOWN(start, PAGE_SIZE);
190 end = PAGE_ALIGN(end); // aligns up
192 pr_debug("Changing flags on range %lx-%lx removing 0x%lx\n",
195 for (idx = start; idx < end; idx += PAGE_SIZE) {
196 pgdp = pgd_offset_k(idx);
197 pudp = pud_alloc(&init_mm, pgdp, idx);
200 if (pud_huge(*pudp)) {
201 ptep = (pte_t *)pudp;
204 pmdp = pmd_alloc(&init_mm, pudp, idx);
207 if (pmd_huge(*pmdp)) {
208 ptep = pmdp_ptep(pmdp);
211 ptep = pte_alloc_kernel(pmdp, idx);
215 radix__pte_update(&init_mm, idx, ptep, clear, 0, 0);
218 radix__flush_tlb_kernel_range(start, end);
221 void radix__mark_rodata_ro(void)
223 unsigned long start, end;
225 start = (unsigned long)_stext;
226 end = (unsigned long)__init_begin;
228 radix__change_memory_range(start, end, _PAGE_WRITE);
231 void radix__mark_initmem_nx(void)
233 unsigned long start = (unsigned long)__init_begin;
234 unsigned long end = (unsigned long)__init_end;
236 radix__change_memory_range(start, end, _PAGE_EXEC);
238 #endif /* CONFIG_STRICT_KERNEL_RWX */
240 static inline void __meminit
241 print_mapping(unsigned long start, unsigned long end, unsigned long size, bool exec)
248 string_get_size(size, 1, STRING_UNITS_2, buf, sizeof(buf));
250 pr_info("Mapped 0x%016lx-0x%016lx with %s pages%s\n", start, end, buf,
251 exec ? " (exec)" : "");
254 static unsigned long next_boundary(unsigned long addr, unsigned long end)
256 #ifdef CONFIG_STRICT_KERNEL_RWX
257 if (addr < __pa_symbol(__init_begin))
258 return __pa_symbol(__init_begin);
263 static int __meminit create_physical_mapping(unsigned long start,
267 unsigned long vaddr, addr, mapping_size = 0;
268 bool prev_exec, exec = false;
272 start = _ALIGN_UP(start, PAGE_SIZE);
273 for (addr = start; addr < end; addr += mapping_size) {
274 unsigned long gap, previous_size;
277 gap = next_boundary(addr, end) - addr;
278 previous_size = mapping_size;
281 if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE &&
282 mmu_psize_defs[MMU_PAGE_1G].shift) {
283 mapping_size = PUD_SIZE;
285 } else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE &&
286 mmu_psize_defs[MMU_PAGE_2M].shift) {
287 mapping_size = PMD_SIZE;
290 mapping_size = PAGE_SIZE;
291 psize = mmu_virtual_psize;
294 vaddr = (unsigned long)__va(addr);
296 if (overlaps_kernel_text(vaddr, vaddr + mapping_size) ||
297 overlaps_interrupt_vector_text(vaddr, vaddr + mapping_size)) {
298 prot = PAGE_KERNEL_X;
305 if (mapping_size != previous_size || exec != prev_exec) {
306 print_mapping(start, addr, previous_size, prev_exec);
310 rc = __map_kernel_page(vaddr, addr, prot, mapping_size, nid, start, end);
314 update_page_count(psize, 1);
317 print_mapping(start, addr, mapping_size, exec);
321 void __init radix_init_pgtable(void)
323 unsigned long rts_field;
324 struct memblock_region *reg;
326 /* We don't support slb for radix */
329 * Create the linear mapping, using standard page size for now
331 for_each_memblock(memory, reg) {
333 * The memblock allocator is up at this point, so the
334 * page tables will be allocated within the range. No
335 * need or a node (which we don't have yet).
337 WARN_ON(create_physical_mapping(reg->base,
338 reg->base + reg->size,
342 /* Find out how many PID bits are supported */
343 if (cpu_has_feature(CPU_FTR_HVMODE)) {
346 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
348 * When KVM is possible, we only use the top half of the
349 * PID space to avoid collisions between host and guest PIDs
350 * which can cause problems due to prefetch when exiting the
353 mmu_base_pid = 1 << (mmu_pid_bits - 1);
358 /* The guest uses the bottom half of the PID space */
365 * Allocate Partition table and process table for the
368 BUG_ON(PRTB_SIZE_SHIFT > 36);
369 process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT, -1, 0, 0);
371 * Fill in the process table.
373 rts_field = radix__get_tree_size();
374 process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE);
376 * Fill in the partition table. We are suppose to use effective address
377 * of process table here. But our linear mapping also enable us to use
378 * physical address here.
380 register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12);
381 pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
382 asm volatile("ptesync" : : : "memory");
383 asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
384 "r" (TLBIEL_INVAL_SET_LPID), "r" (0));
385 asm volatile("eieio; tlbsync; ptesync" : : : "memory");
386 trace_tlbie(0, 0, TLBIEL_INVAL_SET_LPID, 0, 2, 1, 1);
389 * The init_mm context is given the first available (non-zero) PID,
390 * which is the "guard PID" and contains no page table. PIDR should
391 * never be set to zero because that duplicates the kernel address
392 * space at the 0x0... offset (quadrant 0)!
394 * An arbitrary PID that may later be allocated by the PID allocator
395 * for userspace processes must not be used either, because that
396 * would cause stale user mappings for that PID on CPUs outside of
397 * the TLB invalidation scheme (because it won't be in mm_cpumask).
399 * So permanently carve out one PID for the purpose of a guard PID.
401 init_mm.context.id = mmu_base_pid;
405 static void __init radix_init_partition_table(void)
407 unsigned long rts_field, dw0;
409 mmu_partition_table_init();
410 rts_field = radix__get_tree_size();
411 dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR;
412 mmu_partition_table_set_entry(0, dw0, 0);
414 pr_info("Initializing Radix MMU\n");
415 pr_info("Partition table %p\n", partition_tb);
418 void __init radix_init_native(void)
420 register_process_table = native_register_process_table;
423 static int __init get_idx_from_shift(unsigned int shift)
444 static int __init radix_dt_scan_page_sizes(unsigned long node,
445 const char *uname, int depth,
452 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
454 /* We are scanning "cpu" nodes only */
455 if (type == NULL || strcmp(type, "cpu") != 0)
458 /* Find MMU PID size */
459 prop = of_get_flat_dt_prop(node, "ibm,mmu-pid-bits", &size);
460 if (prop && size == 4)
461 mmu_pid_bits = be32_to_cpup(prop);
463 /* Grab page size encodings */
464 prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
468 pr_info("Page sizes from device-tree:\n");
469 for (; size >= 4; size -= 4, ++prop) {
471 struct mmu_psize_def *def;
473 /* top 3 bit is AP encoding */
474 shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
475 ap = be32_to_cpu(prop[0]) >> 29;
476 pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
478 idx = get_idx_from_shift(shift);
482 def = &mmu_psize_defs[idx];
488 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
492 void __init radix__early_init_devtree(void)
497 * Try to find the available page sizes in the device-tree
499 rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
500 if (rc != 0) /* Found */
503 * let's assume we have page 4k and 64k support
505 mmu_psize_defs[MMU_PAGE_4K].shift = 12;
506 mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;
508 mmu_psize_defs[MMU_PAGE_64K].shift = 16;
509 mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
511 #ifdef CONFIG_SPARSEMEM_VMEMMAP
512 if (mmu_psize_defs[MMU_PAGE_2M].shift) {
514 * map vmemmap using 2M if available
516 mmu_vmemmap_psize = MMU_PAGE_2M;
518 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
522 static void radix_init_amor(void)
525 * In HV mode, we init AMOR (Authority Mask Override Register) so that
526 * the hypervisor and guest can setup IAMR (Instruction Authority Mask
527 * Register), enable key 0 and set it to 1.
529 * AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)
531 mtspr(SPRN_AMOR, (3ul << 62));
534 static void radix_init_iamr(void)
537 * Radix always uses key0 of the IAMR to determine if an access is
538 * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction
541 mtspr(SPRN_IAMR, (1ul << 62));
544 void __init radix__early_init_mmu(void)
548 #ifdef CONFIG_PPC_64K_PAGES
549 /* PAGE_SIZE mappings */
550 mmu_virtual_psize = MMU_PAGE_64K;
552 mmu_virtual_psize = MMU_PAGE_4K;
555 #ifdef CONFIG_SPARSEMEM_VMEMMAP
556 /* vmemmap mapping */
557 mmu_vmemmap_psize = mmu_virtual_psize;
560 * initialize page table size
562 __pte_index_size = RADIX_PTE_INDEX_SIZE;
563 __pmd_index_size = RADIX_PMD_INDEX_SIZE;
564 __pud_index_size = RADIX_PUD_INDEX_SIZE;
565 __pgd_index_size = RADIX_PGD_INDEX_SIZE;
566 __pud_cache_index = RADIX_PUD_INDEX_SIZE;
567 __pte_table_size = RADIX_PTE_TABLE_SIZE;
568 __pmd_table_size = RADIX_PMD_TABLE_SIZE;
569 __pud_table_size = RADIX_PUD_TABLE_SIZE;
570 __pgd_table_size = RADIX_PGD_TABLE_SIZE;
572 __pmd_val_bits = RADIX_PMD_VAL_BITS;
573 __pud_val_bits = RADIX_PUD_VAL_BITS;
574 __pgd_val_bits = RADIX_PGD_VAL_BITS;
576 __kernel_virt_start = RADIX_KERN_VIRT_START;
577 __kernel_virt_size = RADIX_KERN_VIRT_SIZE;
578 __vmalloc_start = RADIX_VMALLOC_START;
579 __vmalloc_end = RADIX_VMALLOC_END;
580 __kernel_io_start = RADIX_KERN_IO_START;
581 vmemmap = (struct page *)RADIX_VMEMMAP_BASE;
582 ioremap_bot = IOREMAP_BASE;
585 pci_io_base = ISA_IO_BASE;
587 __pte_frag_nr = RADIX_PTE_FRAG_NR;
588 __pte_frag_size_shift = RADIX_PTE_FRAG_SIZE_SHIFT;
589 __pmd_frag_nr = RADIX_PMD_FRAG_NR;
590 __pmd_frag_size_shift = RADIX_PMD_FRAG_SIZE_SHIFT;
592 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
594 lpcr = mfspr(SPRN_LPCR);
595 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
596 radix_init_partition_table();
599 radix_init_pseries();
602 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
605 radix_init_pgtable();
606 /* Switch to the guard PID before turning on MMU */
607 radix__switch_mmu_context(NULL, &init_mm);
608 if (cpu_has_feature(CPU_FTR_HVMODE))
612 void radix__early_init_mmu_secondary(void)
616 * update partition table control register and UPRT
618 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
619 lpcr = mfspr(SPRN_LPCR);
620 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
623 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
628 radix__switch_mmu_context(NULL, &init_mm);
629 if (cpu_has_feature(CPU_FTR_HVMODE))
633 void radix__mmu_cleanup_all(void)
637 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
638 lpcr = mfspr(SPRN_LPCR);
639 mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
641 powernv_set_nmmu_ptcr(0);
642 radix__flush_tlb_all();
646 void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
647 phys_addr_t first_memblock_size)
649 /* We don't currently support the first MEMBLOCK not mapping 0
650 * physical on those processors
652 BUG_ON(first_memblock_base != 0);
655 * Radix mode is not limited by RMA / VRMA addressing.
657 ppc64_rma_size = ULONG_MAX;
660 #ifdef CONFIG_MEMORY_HOTPLUG
661 static void free_pte_table(pte_t *pte_start, pmd_t *pmd)
666 for (i = 0; i < PTRS_PER_PTE; i++) {
672 pte_free_kernel(&init_mm, pte_start);
676 static void free_pmd_table(pmd_t *pmd_start, pud_t *pud)
681 for (i = 0; i < PTRS_PER_PMD; i++) {
687 pmd_free(&init_mm, pmd_start);
691 struct change_mapping_params {
695 unsigned long aligned_start;
696 unsigned long aligned_end;
699 static int __meminit stop_machine_change_mapping(void *data)
701 struct change_mapping_params *params =
702 (struct change_mapping_params *)data;
707 spin_unlock(&init_mm.page_table_lock);
708 pte_clear(&init_mm, params->aligned_start, params->pte);
709 create_physical_mapping(params->aligned_start, params->start, -1);
710 create_physical_mapping(params->end, params->aligned_end, -1);
711 spin_lock(&init_mm.page_table_lock);
715 static void remove_pte_table(pte_t *pte_start, unsigned long addr,
721 pte = pte_start + pte_index(addr);
722 for (; addr < end; addr = next, pte++) {
723 next = (addr + PAGE_SIZE) & PAGE_MASK;
727 if (!pte_present(*pte))
730 if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(next)) {
732 * The vmemmap_free() and remove_section_mapping()
733 * codepaths call us with aligned addresses.
735 WARN_ONCE(1, "%s: unaligned range\n", __func__);
739 pte_clear(&init_mm, addr, pte);
744 * clear the pte and potentially split the mapping helper
746 static void __meminit split_kernel_mapping(unsigned long addr, unsigned long end,
747 unsigned long size, pte_t *pte)
749 unsigned long mask = ~(size - 1);
750 unsigned long aligned_start = addr & mask;
751 unsigned long aligned_end = addr + size;
752 struct change_mapping_params params;
753 bool split_region = false;
755 if ((end - addr) < size) {
757 * We're going to clear the PTE, but not flushed
758 * the mapping, time to remap and flush. The
759 * effects if visible outside the processor or
760 * if we are running in code close to the
761 * mapping we cleared, we are in trouble.
763 if (overlaps_kernel_text(aligned_start, addr) ||
764 overlaps_kernel_text(end, aligned_end)) {
766 * Hack, just return, don't pte_clear
768 WARN_ONCE(1, "Linear mapping %lx->%lx overlaps kernel "
769 "text, not splitting\n", addr, end);
779 params.aligned_start = addr & ~(size - 1);
780 params.aligned_end = min_t(unsigned long, aligned_end,
781 (unsigned long)__va(memblock_end_of_DRAM()));
782 stop_machine(stop_machine_change_mapping, ¶ms, NULL);
786 pte_clear(&init_mm, addr, pte);
789 static void remove_pmd_table(pmd_t *pmd_start, unsigned long addr,
796 pmd = pmd_start + pmd_index(addr);
797 for (; addr < end; addr = next, pmd++) {
798 next = pmd_addr_end(addr, end);
800 if (!pmd_present(*pmd))
803 if (pmd_huge(*pmd)) {
804 split_kernel_mapping(addr, end, PMD_SIZE, (pte_t *)pmd);
808 pte_base = (pte_t *)pmd_page_vaddr(*pmd);
809 remove_pte_table(pte_base, addr, next);
810 free_pte_table(pte_base, pmd);
814 static void remove_pud_table(pud_t *pud_start, unsigned long addr,
821 pud = pud_start + pud_index(addr);
822 for (; addr < end; addr = next, pud++) {
823 next = pud_addr_end(addr, end);
825 if (!pud_present(*pud))
828 if (pud_huge(*pud)) {
829 split_kernel_mapping(addr, end, PUD_SIZE, (pte_t *)pud);
833 pmd_base = (pmd_t *)pud_page_vaddr(*pud);
834 remove_pmd_table(pmd_base, addr, next);
835 free_pmd_table(pmd_base, pud);
839 static void __meminit remove_pagetable(unsigned long start, unsigned long end)
841 unsigned long addr, next;
845 spin_lock(&init_mm.page_table_lock);
847 for (addr = start; addr < end; addr = next) {
848 next = pgd_addr_end(addr, end);
850 pgd = pgd_offset_k(addr);
851 if (!pgd_present(*pgd))
854 if (pgd_huge(*pgd)) {
855 split_kernel_mapping(addr, end, PGDIR_SIZE, (pte_t *)pgd);
859 pud_base = (pud_t *)pgd_page_vaddr(*pgd);
860 remove_pud_table(pud_base, addr, next);
863 spin_unlock(&init_mm.page_table_lock);
864 radix__flush_tlb_kernel_range(start, end);
867 int __meminit radix__create_section_mapping(unsigned long start, unsigned long end, int nid)
869 return create_physical_mapping(start, end, nid);
872 int __meminit radix__remove_section_mapping(unsigned long start, unsigned long end)
874 remove_pagetable(start, end);
877 #endif /* CONFIG_MEMORY_HOTPLUG */
879 #ifdef CONFIG_SPARSEMEM_VMEMMAP
880 static int __map_kernel_page_nid(unsigned long ea, unsigned long pa,
881 pgprot_t flags, unsigned int map_page_size,
884 return __map_kernel_page(ea, pa, flags, map_page_size, nid, 0, 0);
887 int __meminit radix__vmemmap_create_mapping(unsigned long start,
888 unsigned long page_size,
891 /* Create a PTE encoding */
892 unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW;
893 int nid = early_pfn_to_nid(phys >> PAGE_SHIFT);
896 ret = __map_kernel_page_nid(start, phys, __pgprot(flags), page_size, nid);
902 #ifdef CONFIG_MEMORY_HOTPLUG
903 void __meminit radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
905 remove_pagetable(start, start + page_size);
910 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
912 unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
913 pmd_t *pmdp, unsigned long clr,
918 #ifdef CONFIG_DEBUG_VM
919 WARN_ON(!radix__pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp));
920 assert_spin_locked(pmd_lockptr(mm, pmdp));
923 old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
924 trace_hugepage_update(addr, old, clr, set);
929 pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
935 VM_BUG_ON(address & ~HPAGE_PMD_MASK);
936 VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
937 VM_BUG_ON(pmd_devmap(*pmdp));
939 * khugepaged calls this for normal pmd
944 /*FIXME!! Verify whether we need this kick below */
945 serialize_against_pte_lookup(vma->vm_mm);
947 radix__flush_tlb_collapsed_pmd(vma->vm_mm, address);
953 * For us pgtable_t is pte_t *. Inorder to save the deposisted
954 * page table, we consider the allocated page table as a list
955 * head. On withdraw we need to make sure we zero out the used
956 * list_head memory area.
958 void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
961 struct list_head *lh = (struct list_head *) pgtable;
963 assert_spin_locked(pmd_lockptr(mm, pmdp));
966 if (!pmd_huge_pte(mm, pmdp))
969 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
970 pmd_huge_pte(mm, pmdp) = pgtable;
973 pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
977 struct list_head *lh;
979 assert_spin_locked(pmd_lockptr(mm, pmdp));
982 pgtable = pmd_huge_pte(mm, pmdp);
983 lh = (struct list_head *) pgtable;
985 pmd_huge_pte(mm, pmdp) = NULL;
987 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
990 ptep = (pte_t *) pgtable;
998 pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
999 unsigned long addr, pmd_t *pmdp)
1004 old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
1005 old_pmd = __pmd(old);
1007 * Serialize against find_current_mm_pte which does lock-less
1008 * lookup in page tables with local interrupts disabled. For huge pages
1009 * it casts pmd_t to pte_t. Since format of pte_t is different from
1010 * pmd_t we want to prevent transit from pmd pointing to page table
1011 * to pmd pointing to huge page (and back) while interrupts are disabled.
1012 * We clear pmd to possibly replace it with page table pointer in
1013 * different code paths. So make sure we wait for the parallel
1014 * find_current_mm_pte to finish.
1016 serialize_against_pte_lookup(mm);
1020 int radix__has_transparent_hugepage(void)
1022 /* For radix 2M at PMD level means thp */
1023 if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
1027 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1029 void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep,
1030 pte_t entry, unsigned long address, int psize)
1032 struct mm_struct *mm = vma->vm_mm;
1033 unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED |
1034 _PAGE_RW | _PAGE_EXEC);
1036 unsigned long change = pte_val(entry) ^ pte_val(*ptep);
1038 * To avoid NMMU hang while relaxing access, we need mark
1039 * the pte invalid in between.
1041 if ((change & _PAGE_RW) && atomic_read(&mm->context.copros) > 0) {
1042 unsigned long old_pte, new_pte;
1044 old_pte = __radix_pte_update(ptep, _PAGE_PRESENT, _PAGE_INVALID);
1048 new_pte = old_pte | set;
1049 radix__flush_tlb_page_psize(mm, address, psize);
1050 __radix_pte_update(ptep, _PAGE_INVALID, new_pte);
1052 __radix_pte_update(ptep, 0, set);
1054 * Book3S does not require a TLB flush when relaxing access
1055 * restrictions when the address space is not attached to a
1056 * NMMU, because the core MMU will reload the pte after taking
1057 * an access fault, which is defined by the architectue.
1060 /* See ptesync comment in radix__set_pte_at */
1063 void radix__ptep_modify_prot_commit(struct vm_area_struct *vma,
1064 unsigned long addr, pte_t *ptep,
1065 pte_t old_pte, pte_t pte)
1067 struct mm_struct *mm = vma->vm_mm;
1070 * To avoid NMMU hang while relaxing access we need to flush the tlb before
1071 * we set the new value. We need to do this only for radix, because hash
1072 * translation does flush when updating the linux pte.
1074 if (is_pte_rw_upgrade(pte_val(old_pte), pte_val(pte)) &&
1075 (atomic_read(&mm->context.copros) > 0))
1076 radix__flush_tlb_page(vma, addr);
1078 set_pte_at(mm, addr, ptep, pte);