2 * Page table handling routines for radix page table.
4 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #define pr_fmt(fmt) "radix-mmu: " fmt
14 #include <linux/kernel.h>
15 #include <linux/sched/mm.h>
16 #include <linux/memblock.h>
17 #include <linux/of_fdt.h>
19 #include <linux/string_helpers.h>
20 #include <linux/stop_machine.h>
22 #include <asm/pgtable.h>
23 #include <asm/pgalloc.h>
24 #include <asm/mmu_context.h>
26 #include <asm/machdep.h>
28 #include <asm/firmware.h>
29 #include <asm/powernv.h>
30 #include <asm/sections.h>
31 #include <asm/trace.h>
32 #include <asm/uaccess.h>
34 #include <trace/events/thp.h>
36 unsigned int mmu_pid_bits;
37 unsigned int mmu_base_pid;
39 static int native_register_process_table(unsigned long base, unsigned long pg_sz,
40 unsigned long table_size)
42 unsigned long patb0, patb1;
44 patb0 = be64_to_cpu(partition_tb[0].patb0);
45 patb1 = base | table_size | PATB_GR;
47 mmu_partition_table_set_entry(0, patb0, patb1);
52 static __ref void *early_alloc_pgtable(unsigned long size, int nid,
53 unsigned long region_start, unsigned long region_end)
55 phys_addr_t min_addr = MEMBLOCK_LOW_LIMIT;
56 phys_addr_t max_addr = MEMBLOCK_ALLOC_ANYWHERE;
60 min_addr = region_start;
62 max_addr = region_end;
64 ptr = memblock_alloc_try_nid(size, size, min_addr, max_addr, nid);
67 panic("%s: Failed to allocate %lu bytes align=0x%lx nid=%d from=%pa max_addr=%pa\n",
68 __func__, size, size, nid, &min_addr, &max_addr);
73 static int early_map_kernel_page(unsigned long ea, unsigned long pa,
75 unsigned int map_page_size,
77 unsigned long region_start, unsigned long region_end)
79 unsigned long pfn = pa >> PAGE_SHIFT;
85 pgdp = pgd_offset_k(ea);
86 if (pgd_none(*pgdp)) {
87 pudp = early_alloc_pgtable(PUD_TABLE_SIZE, nid,
88 region_start, region_end);
89 pgd_populate(&init_mm, pgdp, pudp);
91 pudp = pud_offset(pgdp, ea);
92 if (map_page_size == PUD_SIZE) {
96 if (pud_none(*pudp)) {
97 pmdp = early_alloc_pgtable(PMD_TABLE_SIZE, nid,
98 region_start, region_end);
99 pud_populate(&init_mm, pudp, pmdp);
101 pmdp = pmd_offset(pudp, ea);
102 if (map_page_size == PMD_SIZE) {
103 ptep = pmdp_ptep(pmdp);
106 if (!pmd_present(*pmdp)) {
107 ptep = early_alloc_pgtable(PAGE_SIZE, nid,
108 region_start, region_end);
109 pmd_populate_kernel(&init_mm, pmdp, ptep);
111 ptep = pte_offset_kernel(pmdp, ea);
114 set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
120 * nid, region_start, and region_end are hints to try to place the page
121 * table memory in the same node or region.
123 static int __map_kernel_page(unsigned long ea, unsigned long pa,
125 unsigned int map_page_size,
127 unsigned long region_start, unsigned long region_end)
129 unsigned long pfn = pa >> PAGE_SHIFT;
135 * Make sure task size is correct as per the max adddr
137 BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
139 #ifdef CONFIG_PPC_64K_PAGES
140 BUILD_BUG_ON(RADIX_KERN_MAP_SIZE != (1UL << MAX_EA_BITS_PER_CONTEXT));
143 if (unlikely(!slab_is_available()))
144 return early_map_kernel_page(ea, pa, flags, map_page_size,
145 nid, region_start, region_end);
148 * Should make page table allocation functions be able to take a
149 * node, so we can place kernel page tables on the right nodes after
152 pgdp = pgd_offset_k(ea);
153 pudp = pud_alloc(&init_mm, pgdp, ea);
156 if (map_page_size == PUD_SIZE) {
157 ptep = (pte_t *)pudp;
160 pmdp = pmd_alloc(&init_mm, pudp, ea);
163 if (map_page_size == PMD_SIZE) {
164 ptep = pmdp_ptep(pmdp);
167 ptep = pte_alloc_kernel(pmdp, ea);
172 set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
177 int radix__map_kernel_page(unsigned long ea, unsigned long pa,
179 unsigned int map_page_size)
181 return __map_kernel_page(ea, pa, flags, map_page_size, -1, 0, 0);
184 #ifdef CONFIG_STRICT_KERNEL_RWX
185 void radix__change_memory_range(unsigned long start, unsigned long end,
194 start = ALIGN_DOWN(start, PAGE_SIZE);
195 end = PAGE_ALIGN(end); // aligns up
197 pr_debug("Changing flags on range %lx-%lx removing 0x%lx\n",
200 for (idx = start; idx < end; idx += PAGE_SIZE) {
201 pgdp = pgd_offset_k(idx);
202 pudp = pud_alloc(&init_mm, pgdp, idx);
205 if (pud_huge(*pudp)) {
206 ptep = (pte_t *)pudp;
209 pmdp = pmd_alloc(&init_mm, pudp, idx);
212 if (pmd_huge(*pmdp)) {
213 ptep = pmdp_ptep(pmdp);
216 ptep = pte_alloc_kernel(pmdp, idx);
220 radix__pte_update(&init_mm, idx, ptep, clear, 0, 0);
223 radix__flush_tlb_kernel_range(start, end);
226 void radix__mark_rodata_ro(void)
228 unsigned long start, end;
230 start = (unsigned long)_stext;
231 end = (unsigned long)__init_begin;
233 radix__change_memory_range(start, end, _PAGE_WRITE);
236 void radix__mark_initmem_nx(void)
238 unsigned long start = (unsigned long)__init_begin;
239 unsigned long end = (unsigned long)__init_end;
241 radix__change_memory_range(start, end, _PAGE_EXEC);
243 #endif /* CONFIG_STRICT_KERNEL_RWX */
245 static inline void __meminit
246 print_mapping(unsigned long start, unsigned long end, unsigned long size, bool exec)
253 string_get_size(size, 1, STRING_UNITS_2, buf, sizeof(buf));
255 pr_info("Mapped 0x%016lx-0x%016lx with %s pages%s\n", start, end, buf,
256 exec ? " (exec)" : "");
259 static unsigned long next_boundary(unsigned long addr, unsigned long end)
261 #ifdef CONFIG_STRICT_KERNEL_RWX
262 if (addr < __pa_symbol(__init_begin))
263 return __pa_symbol(__init_begin);
268 static int __meminit create_physical_mapping(unsigned long start,
272 unsigned long vaddr, addr, mapping_size = 0;
273 bool prev_exec, exec = false;
277 start = _ALIGN_UP(start, PAGE_SIZE);
278 for (addr = start; addr < end; addr += mapping_size) {
279 unsigned long gap, previous_size;
282 gap = next_boundary(addr, end) - addr;
283 previous_size = mapping_size;
286 if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE &&
287 mmu_psize_defs[MMU_PAGE_1G].shift) {
288 mapping_size = PUD_SIZE;
290 } else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE &&
291 mmu_psize_defs[MMU_PAGE_2M].shift) {
292 mapping_size = PMD_SIZE;
295 mapping_size = PAGE_SIZE;
296 psize = mmu_virtual_psize;
299 vaddr = (unsigned long)__va(addr);
301 if (overlaps_kernel_text(vaddr, vaddr + mapping_size) ||
302 overlaps_interrupt_vector_text(vaddr, vaddr + mapping_size)) {
303 prot = PAGE_KERNEL_X;
310 if (mapping_size != previous_size || exec != prev_exec) {
311 print_mapping(start, addr, previous_size, prev_exec);
315 rc = __map_kernel_page(vaddr, addr, prot, mapping_size, nid, start, end);
319 update_page_count(psize, 1);
322 print_mapping(start, addr, mapping_size, exec);
326 void __init radix_init_pgtable(void)
328 unsigned long rts_field;
329 struct memblock_region *reg;
331 /* We don't support slb for radix */
334 * Create the linear mapping, using standard page size for now
336 for_each_memblock(memory, reg) {
338 * The memblock allocator is up at this point, so the
339 * page tables will be allocated within the range. No
340 * need or a node (which we don't have yet).
342 WARN_ON(create_physical_mapping(reg->base,
343 reg->base + reg->size,
347 /* Find out how many PID bits are supported */
348 if (cpu_has_feature(CPU_FTR_HVMODE)) {
351 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
353 * When KVM is possible, we only use the top half of the
354 * PID space to avoid collisions between host and guest PIDs
355 * which can cause problems due to prefetch when exiting the
358 mmu_base_pid = 1 << (mmu_pid_bits - 1);
363 /* The guest uses the bottom half of the PID space */
370 * Allocate Partition table and process table for the
373 BUG_ON(PRTB_SIZE_SHIFT > 36);
374 process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT, -1, 0, 0);
376 * Fill in the process table.
378 rts_field = radix__get_tree_size();
379 process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE);
381 * Fill in the partition table. We are suppose to use effective address
382 * of process table here. But our linear mapping also enable us to use
383 * physical address here.
385 register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12);
386 pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
387 asm volatile("ptesync" : : : "memory");
388 asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
389 "r" (TLBIEL_INVAL_SET_LPID), "r" (0));
390 asm volatile("eieio; tlbsync; ptesync" : : : "memory");
391 trace_tlbie(0, 0, TLBIEL_INVAL_SET_LPID, 0, 2, 1, 1);
394 * The init_mm context is given the first available (non-zero) PID,
395 * which is the "guard PID" and contains no page table. PIDR should
396 * never be set to zero because that duplicates the kernel address
397 * space at the 0x0... offset (quadrant 0)!
399 * An arbitrary PID that may later be allocated by the PID allocator
400 * for userspace processes must not be used either, because that
401 * would cause stale user mappings for that PID on CPUs outside of
402 * the TLB invalidation scheme (because it won't be in mm_cpumask).
404 * So permanently carve out one PID for the purpose of a guard PID.
406 init_mm.context.id = mmu_base_pid;
410 static void __init radix_init_partition_table(void)
412 unsigned long rts_field, dw0;
414 mmu_partition_table_init();
415 rts_field = radix__get_tree_size();
416 dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR;
417 mmu_partition_table_set_entry(0, dw0, 0);
419 pr_info("Initializing Radix MMU\n");
420 pr_info("Partition table %p\n", partition_tb);
423 void __init radix_init_native(void)
425 register_process_table = native_register_process_table;
428 static int __init get_idx_from_shift(unsigned int shift)
449 static int __init radix_dt_scan_page_sizes(unsigned long node,
450 const char *uname, int depth,
457 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
459 /* We are scanning "cpu" nodes only */
460 if (type == NULL || strcmp(type, "cpu") != 0)
463 /* Find MMU PID size */
464 prop = of_get_flat_dt_prop(node, "ibm,mmu-pid-bits", &size);
465 if (prop && size == 4)
466 mmu_pid_bits = be32_to_cpup(prop);
468 /* Grab page size encodings */
469 prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
473 pr_info("Page sizes from device-tree:\n");
474 for (; size >= 4; size -= 4, ++prop) {
476 struct mmu_psize_def *def;
478 /* top 3 bit is AP encoding */
479 shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
480 ap = be32_to_cpu(prop[0]) >> 29;
481 pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
483 idx = get_idx_from_shift(shift);
487 def = &mmu_psize_defs[idx];
493 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
497 void __init radix__early_init_devtree(void)
502 * Try to find the available page sizes in the device-tree
504 rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
505 if (rc != 0) /* Found */
508 * let's assume we have page 4k and 64k support
510 mmu_psize_defs[MMU_PAGE_4K].shift = 12;
511 mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;
513 mmu_psize_defs[MMU_PAGE_64K].shift = 16;
514 mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
516 #ifdef CONFIG_SPARSEMEM_VMEMMAP
517 if (mmu_psize_defs[MMU_PAGE_2M].shift) {
519 * map vmemmap using 2M if available
521 mmu_vmemmap_psize = MMU_PAGE_2M;
523 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
527 static void radix_init_amor(void)
530 * In HV mode, we init AMOR (Authority Mask Override Register) so that
531 * the hypervisor and guest can setup IAMR (Instruction Authority Mask
532 * Register), enable key 0 and set it to 1.
534 * AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)
536 mtspr(SPRN_AMOR, (3ul << 62));
539 #ifdef CONFIG_PPC_KUEP
540 void setup_kuep(bool disabled)
542 if (disabled || !early_radix_enabled())
545 if (smp_processor_id() == boot_cpuid)
546 pr_info("Activating Kernel Userspace Execution Prevention\n");
549 * Radix always uses key0 of the IAMR to determine if an access is
550 * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction
553 mtspr(SPRN_IAMR, (1ul << 62));
557 #ifdef CONFIG_PPC_KUAP
558 void setup_kuap(bool disabled)
560 if (disabled || !early_radix_enabled())
563 if (smp_processor_id() == boot_cpuid) {
564 pr_info("Activating Kernel Userspace Access Prevention\n");
565 cur_cpu_spec->mmu_features |= MMU_FTR_RADIX_KUAP;
568 /* Make sure userspace can't change the AMR */
569 mtspr(SPRN_UAMOR, 0);
570 mtspr(SPRN_AMR, AMR_KUAP_BLOCKED);
575 void __init radix__early_init_mmu(void)
579 #ifdef CONFIG_PPC_64K_PAGES
580 /* PAGE_SIZE mappings */
581 mmu_virtual_psize = MMU_PAGE_64K;
583 mmu_virtual_psize = MMU_PAGE_4K;
586 #ifdef CONFIG_SPARSEMEM_VMEMMAP
587 /* vmemmap mapping */
588 mmu_vmemmap_psize = mmu_virtual_psize;
591 * initialize page table size
593 __pte_index_size = RADIX_PTE_INDEX_SIZE;
594 __pmd_index_size = RADIX_PMD_INDEX_SIZE;
595 __pud_index_size = RADIX_PUD_INDEX_SIZE;
596 __pgd_index_size = RADIX_PGD_INDEX_SIZE;
597 __pud_cache_index = RADIX_PUD_INDEX_SIZE;
598 __pte_table_size = RADIX_PTE_TABLE_SIZE;
599 __pmd_table_size = RADIX_PMD_TABLE_SIZE;
600 __pud_table_size = RADIX_PUD_TABLE_SIZE;
601 __pgd_table_size = RADIX_PGD_TABLE_SIZE;
603 __pmd_val_bits = RADIX_PMD_VAL_BITS;
604 __pud_val_bits = RADIX_PUD_VAL_BITS;
605 __pgd_val_bits = RADIX_PGD_VAL_BITS;
607 __kernel_virt_start = RADIX_KERN_VIRT_START;
608 __vmalloc_start = RADIX_VMALLOC_START;
609 __vmalloc_end = RADIX_VMALLOC_END;
610 __kernel_io_start = RADIX_KERN_IO_START;
611 __kernel_io_end = RADIX_KERN_IO_END;
612 vmemmap = (struct page *)RADIX_VMEMMAP_START;
613 ioremap_bot = IOREMAP_BASE;
616 pci_io_base = ISA_IO_BASE;
618 __pte_frag_nr = RADIX_PTE_FRAG_NR;
619 __pte_frag_size_shift = RADIX_PTE_FRAG_SIZE_SHIFT;
620 __pmd_frag_nr = RADIX_PMD_FRAG_NR;
621 __pmd_frag_size_shift = RADIX_PMD_FRAG_SIZE_SHIFT;
623 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
625 lpcr = mfspr(SPRN_LPCR);
626 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
627 radix_init_partition_table();
630 radix_init_pseries();
633 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
635 radix_init_pgtable();
636 /* Switch to the guard PID before turning on MMU */
637 radix__switch_mmu_context(NULL, &init_mm);
638 if (cpu_has_feature(CPU_FTR_HVMODE))
642 void radix__early_init_mmu_secondary(void)
646 * update partition table control register and UPRT
648 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
649 lpcr = mfspr(SPRN_LPCR);
650 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
653 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
657 radix__switch_mmu_context(NULL, &init_mm);
658 if (cpu_has_feature(CPU_FTR_HVMODE))
662 void radix__mmu_cleanup_all(void)
666 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
667 lpcr = mfspr(SPRN_LPCR);
668 mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
670 powernv_set_nmmu_ptcr(0);
671 radix__flush_tlb_all();
675 void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
676 phys_addr_t first_memblock_size)
678 /* We don't currently support the first MEMBLOCK not mapping 0
679 * physical on those processors
681 BUG_ON(first_memblock_base != 0);
684 * Radix mode is not limited by RMA / VRMA addressing.
686 ppc64_rma_size = ULONG_MAX;
689 #ifdef CONFIG_MEMORY_HOTPLUG
690 static void free_pte_table(pte_t *pte_start, pmd_t *pmd)
695 for (i = 0; i < PTRS_PER_PTE; i++) {
701 pte_free_kernel(&init_mm, pte_start);
705 static void free_pmd_table(pmd_t *pmd_start, pud_t *pud)
710 for (i = 0; i < PTRS_PER_PMD; i++) {
716 pmd_free(&init_mm, pmd_start);
720 struct change_mapping_params {
724 unsigned long aligned_start;
725 unsigned long aligned_end;
728 static int __meminit stop_machine_change_mapping(void *data)
730 struct change_mapping_params *params =
731 (struct change_mapping_params *)data;
736 spin_unlock(&init_mm.page_table_lock);
737 pte_clear(&init_mm, params->aligned_start, params->pte);
738 create_physical_mapping(params->aligned_start, params->start, -1);
739 create_physical_mapping(params->end, params->aligned_end, -1);
740 spin_lock(&init_mm.page_table_lock);
744 static void remove_pte_table(pte_t *pte_start, unsigned long addr,
750 pte = pte_start + pte_index(addr);
751 for (; addr < end; addr = next, pte++) {
752 next = (addr + PAGE_SIZE) & PAGE_MASK;
756 if (!pte_present(*pte))
759 if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(next)) {
761 * The vmemmap_free() and remove_section_mapping()
762 * codepaths call us with aligned addresses.
764 WARN_ONCE(1, "%s: unaligned range\n", __func__);
768 pte_clear(&init_mm, addr, pte);
773 * clear the pte and potentially split the mapping helper
775 static void __meminit split_kernel_mapping(unsigned long addr, unsigned long end,
776 unsigned long size, pte_t *pte)
778 unsigned long mask = ~(size - 1);
779 unsigned long aligned_start = addr & mask;
780 unsigned long aligned_end = addr + size;
781 struct change_mapping_params params;
782 bool split_region = false;
784 if ((end - addr) < size) {
786 * We're going to clear the PTE, but not flushed
787 * the mapping, time to remap and flush. The
788 * effects if visible outside the processor or
789 * if we are running in code close to the
790 * mapping we cleared, we are in trouble.
792 if (overlaps_kernel_text(aligned_start, addr) ||
793 overlaps_kernel_text(end, aligned_end)) {
795 * Hack, just return, don't pte_clear
797 WARN_ONCE(1, "Linear mapping %lx->%lx overlaps kernel "
798 "text, not splitting\n", addr, end);
808 params.aligned_start = addr & ~(size - 1);
809 params.aligned_end = min_t(unsigned long, aligned_end,
810 (unsigned long)__va(memblock_end_of_DRAM()));
811 stop_machine(stop_machine_change_mapping, ¶ms, NULL);
815 pte_clear(&init_mm, addr, pte);
818 static void remove_pmd_table(pmd_t *pmd_start, unsigned long addr,
825 pmd = pmd_start + pmd_index(addr);
826 for (; addr < end; addr = next, pmd++) {
827 next = pmd_addr_end(addr, end);
829 if (!pmd_present(*pmd))
832 if (pmd_huge(*pmd)) {
833 split_kernel_mapping(addr, end, PMD_SIZE, (pte_t *)pmd);
837 pte_base = (pte_t *)pmd_page_vaddr(*pmd);
838 remove_pte_table(pte_base, addr, next);
839 free_pte_table(pte_base, pmd);
843 static void remove_pud_table(pud_t *pud_start, unsigned long addr,
850 pud = pud_start + pud_index(addr);
851 for (; addr < end; addr = next, pud++) {
852 next = pud_addr_end(addr, end);
854 if (!pud_present(*pud))
857 if (pud_huge(*pud)) {
858 split_kernel_mapping(addr, end, PUD_SIZE, (pte_t *)pud);
862 pmd_base = (pmd_t *)pud_page_vaddr(*pud);
863 remove_pmd_table(pmd_base, addr, next);
864 free_pmd_table(pmd_base, pud);
868 static void __meminit remove_pagetable(unsigned long start, unsigned long end)
870 unsigned long addr, next;
874 spin_lock(&init_mm.page_table_lock);
876 for (addr = start; addr < end; addr = next) {
877 next = pgd_addr_end(addr, end);
879 pgd = pgd_offset_k(addr);
880 if (!pgd_present(*pgd))
883 if (pgd_huge(*pgd)) {
884 split_kernel_mapping(addr, end, PGDIR_SIZE, (pte_t *)pgd);
888 pud_base = (pud_t *)pgd_page_vaddr(*pgd);
889 remove_pud_table(pud_base, addr, next);
892 spin_unlock(&init_mm.page_table_lock);
893 radix__flush_tlb_kernel_range(start, end);
896 int __meminit radix__create_section_mapping(unsigned long start, unsigned long end, int nid)
898 return create_physical_mapping(start, end, nid);
901 int __meminit radix__remove_section_mapping(unsigned long start, unsigned long end)
903 remove_pagetable(start, end);
906 #endif /* CONFIG_MEMORY_HOTPLUG */
908 #ifdef CONFIG_SPARSEMEM_VMEMMAP
909 static int __map_kernel_page_nid(unsigned long ea, unsigned long pa,
910 pgprot_t flags, unsigned int map_page_size,
913 return __map_kernel_page(ea, pa, flags, map_page_size, nid, 0, 0);
916 int __meminit radix__vmemmap_create_mapping(unsigned long start,
917 unsigned long page_size,
920 /* Create a PTE encoding */
921 unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW;
922 int nid = early_pfn_to_nid(phys >> PAGE_SHIFT);
925 ret = __map_kernel_page_nid(start, phys, __pgprot(flags), page_size, nid);
931 #ifdef CONFIG_MEMORY_HOTPLUG
932 void __meminit radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
934 remove_pagetable(start, start + page_size);
939 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
941 unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
942 pmd_t *pmdp, unsigned long clr,
947 #ifdef CONFIG_DEBUG_VM
948 WARN_ON(!radix__pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp));
949 assert_spin_locked(pmd_lockptr(mm, pmdp));
952 old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
953 trace_hugepage_update(addr, old, clr, set);
958 pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
964 VM_BUG_ON(address & ~HPAGE_PMD_MASK);
965 VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
966 VM_BUG_ON(pmd_devmap(*pmdp));
968 * khugepaged calls this for normal pmd
973 /*FIXME!! Verify whether we need this kick below */
974 serialize_against_pte_lookup(vma->vm_mm);
976 radix__flush_tlb_collapsed_pmd(vma->vm_mm, address);
982 * For us pgtable_t is pte_t *. Inorder to save the deposisted
983 * page table, we consider the allocated page table as a list
984 * head. On withdraw we need to make sure we zero out the used
985 * list_head memory area.
987 void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
990 struct list_head *lh = (struct list_head *) pgtable;
992 assert_spin_locked(pmd_lockptr(mm, pmdp));
995 if (!pmd_huge_pte(mm, pmdp))
998 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
999 pmd_huge_pte(mm, pmdp) = pgtable;
1002 pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
1006 struct list_head *lh;
1008 assert_spin_locked(pmd_lockptr(mm, pmdp));
1011 pgtable = pmd_huge_pte(mm, pmdp);
1012 lh = (struct list_head *) pgtable;
1014 pmd_huge_pte(mm, pmdp) = NULL;
1016 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
1019 ptep = (pte_t *) pgtable;
1027 pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
1028 unsigned long addr, pmd_t *pmdp)
1033 old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
1034 old_pmd = __pmd(old);
1036 * Serialize against find_current_mm_pte which does lock-less
1037 * lookup in page tables with local interrupts disabled. For huge pages
1038 * it casts pmd_t to pte_t. Since format of pte_t is different from
1039 * pmd_t we want to prevent transit from pmd pointing to page table
1040 * to pmd pointing to huge page (and back) while interrupts are disabled.
1041 * We clear pmd to possibly replace it with page table pointer in
1042 * different code paths. So make sure we wait for the parallel
1043 * find_current_mm_pte to finish.
1045 serialize_against_pte_lookup(mm);
1049 int radix__has_transparent_hugepage(void)
1051 /* For radix 2M at PMD level means thp */
1052 if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
1056 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1058 void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep,
1059 pte_t entry, unsigned long address, int psize)
1061 struct mm_struct *mm = vma->vm_mm;
1062 unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED |
1063 _PAGE_RW | _PAGE_EXEC);
1065 unsigned long change = pte_val(entry) ^ pte_val(*ptep);
1067 * To avoid NMMU hang while relaxing access, we need mark
1068 * the pte invalid in between.
1070 if ((change & _PAGE_RW) && atomic_read(&mm->context.copros) > 0) {
1071 unsigned long old_pte, new_pte;
1073 old_pte = __radix_pte_update(ptep, _PAGE_PRESENT, _PAGE_INVALID);
1077 new_pte = old_pte | set;
1078 radix__flush_tlb_page_psize(mm, address, psize);
1079 __radix_pte_update(ptep, _PAGE_INVALID, new_pte);
1081 __radix_pte_update(ptep, 0, set);
1083 * Book3S does not require a TLB flush when relaxing access
1084 * restrictions when the address space is not attached to a
1085 * NMMU, because the core MMU will reload the pte after taking
1086 * an access fault, which is defined by the architectue.
1089 /* See ptesync comment in radix__set_pte_at */
1092 void radix__ptep_modify_prot_commit(struct vm_area_struct *vma,
1093 unsigned long addr, pte_t *ptep,
1094 pte_t old_pte, pte_t pte)
1096 struct mm_struct *mm = vma->vm_mm;
1099 * To avoid NMMU hang while relaxing access we need to flush the tlb before
1100 * we set the new value. We need to do this only for radix, because hash
1101 * translation does flush when updating the linux pte.
1103 if (is_pte_rw_upgrade(pte_val(old_pte), pte_val(pte)) &&
1104 (atomic_read(&mm->context.copros) > 0))
1105 radix__flush_tlb_page(vma, addr);
1107 set_pte_at(mm, addr, ptep, pte);