2 * Page table handling routines for radix page table.
4 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #define pr_fmt(fmt) "radix-mmu: " fmt
14 #include <linux/kernel.h>
15 #include <linux/sched/mm.h>
16 #include <linux/memblock.h>
17 #include <linux/of_fdt.h>
19 #include <linux/string_helpers.h>
20 #include <linux/stop_machine.h>
22 #include <asm/pgtable.h>
23 #include <asm/pgalloc.h>
24 #include <asm/mmu_context.h>
26 #include <asm/machdep.h>
28 #include <asm/firmware.h>
29 #include <asm/powernv.h>
30 #include <asm/sections.h>
31 #include <asm/trace.h>
33 #include <trace/events/thp.h>
35 unsigned int mmu_pid_bits;
36 unsigned int mmu_base_pid;
38 static int native_register_process_table(unsigned long base, unsigned long pg_sz,
39 unsigned long table_size)
41 unsigned long patb0, patb1;
43 patb0 = be64_to_cpu(partition_tb[0].patb0);
44 patb1 = base | table_size | PATB_GR;
46 mmu_partition_table_set_entry(0, patb0, patb1);
51 static __ref void *early_alloc_pgtable(unsigned long size)
55 pt = __va(memblock_alloc_base(size, size, MEMBLOCK_ALLOC_ANYWHERE));
61 int radix__map_kernel_page(unsigned long ea, unsigned long pa,
63 unsigned int map_page_size)
70 * Make sure task size is correct as per the max adddr
72 BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
73 if (slab_is_available()) {
74 pgdp = pgd_offset_k(ea);
75 pudp = pud_alloc(&init_mm, pgdp, ea);
78 if (map_page_size == PUD_SIZE) {
82 pmdp = pmd_alloc(&init_mm, pudp, ea);
85 if (map_page_size == PMD_SIZE) {
86 ptep = pmdp_ptep(pmdp);
89 ptep = pte_alloc_kernel(pmdp, ea);
93 pgdp = pgd_offset_k(ea);
94 if (pgd_none(*pgdp)) {
95 pudp = early_alloc_pgtable(PUD_TABLE_SIZE);
97 pgd_populate(&init_mm, pgdp, pudp);
99 pudp = pud_offset(pgdp, ea);
100 if (map_page_size == PUD_SIZE) {
101 ptep = (pte_t *)pudp;
104 if (pud_none(*pudp)) {
105 pmdp = early_alloc_pgtable(PMD_TABLE_SIZE);
106 BUG_ON(pmdp == NULL);
107 pud_populate(&init_mm, pudp, pmdp);
109 pmdp = pmd_offset(pudp, ea);
110 if (map_page_size == PMD_SIZE) {
111 ptep = pmdp_ptep(pmdp);
114 if (!pmd_present(*pmdp)) {
115 ptep = early_alloc_pgtable(PAGE_SIZE);
116 BUG_ON(ptep == NULL);
117 pmd_populate_kernel(&init_mm, pmdp, ptep);
119 ptep = pte_offset_kernel(pmdp, ea);
123 set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT, flags));
128 #ifdef CONFIG_STRICT_KERNEL_RWX
129 void radix__change_memory_range(unsigned long start, unsigned long end,
138 start = ALIGN_DOWN(start, PAGE_SIZE);
139 end = PAGE_ALIGN(end); // aligns up
141 pr_debug("Changing flags on range %lx-%lx removing 0x%lx\n",
144 for (idx = start; idx < end; idx += PAGE_SIZE) {
145 pgdp = pgd_offset_k(idx);
146 pudp = pud_alloc(&init_mm, pgdp, idx);
149 if (pud_huge(*pudp)) {
150 ptep = (pte_t *)pudp;
153 pmdp = pmd_alloc(&init_mm, pudp, idx);
156 if (pmd_huge(*pmdp)) {
157 ptep = pmdp_ptep(pmdp);
160 ptep = pte_alloc_kernel(pmdp, idx);
164 radix__pte_update(&init_mm, idx, ptep, clear, 0, 0);
167 radix__flush_tlb_kernel_range(start, end);
170 void radix__mark_rodata_ro(void)
172 unsigned long start, end;
175 * mark_rodata_ro() will mark itself as !writable at some point.
176 * Due to DD1 workaround in radix__pte_update(), we'll end up with
177 * an invalid pte and the system will crash quite severly.
179 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
180 pr_warn("Warning: Unable to mark rodata read only on P9 DD1\n");
184 start = (unsigned long)_stext;
185 end = (unsigned long)__init_begin;
187 radix__change_memory_range(start, end, _PAGE_WRITE);
190 void radix__mark_initmem_nx(void)
192 unsigned long start = (unsigned long)__init_begin;
193 unsigned long end = (unsigned long)__init_end;
195 radix__change_memory_range(start, end, _PAGE_EXEC);
197 #endif /* CONFIG_STRICT_KERNEL_RWX */
199 static inline void __meminit print_mapping(unsigned long start,
208 string_get_size(size, 1, STRING_UNITS_2, buf, sizeof(buf));
210 pr_info("Mapped 0x%016lx-0x%016lx with %s pages\n", start, end, buf);
213 static int __meminit create_physical_mapping(unsigned long start,
216 unsigned long vaddr, addr, mapping_size = 0;
218 unsigned long max_mapping_size;
219 #ifdef CONFIG_STRICT_KERNEL_RWX
220 int split_text_mapping = 1;
222 int split_text_mapping = 0;
225 start = _ALIGN_UP(start, PAGE_SIZE);
226 for (addr = start; addr < end; addr += mapping_size) {
227 unsigned long gap, previous_size;
231 previous_size = mapping_size;
232 max_mapping_size = PUD_SIZE;
235 if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE &&
236 mmu_psize_defs[MMU_PAGE_1G].shift &&
237 PUD_SIZE <= max_mapping_size)
238 mapping_size = PUD_SIZE;
239 else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE &&
240 mmu_psize_defs[MMU_PAGE_2M].shift)
241 mapping_size = PMD_SIZE;
243 mapping_size = PAGE_SIZE;
245 if (split_text_mapping && (mapping_size == PUD_SIZE) &&
246 (addr <= __pa_symbol(__init_begin)) &&
247 (addr + mapping_size) >= __pa_symbol(_stext)) {
248 max_mapping_size = PMD_SIZE;
252 if (split_text_mapping && (mapping_size == PMD_SIZE) &&
253 (addr <= __pa_symbol(__init_begin)) &&
254 (addr + mapping_size) >= __pa_symbol(_stext))
255 mapping_size = PAGE_SIZE;
257 if (mapping_size != previous_size) {
258 print_mapping(start, addr, previous_size);
262 vaddr = (unsigned long)__va(addr);
264 if (overlaps_kernel_text(vaddr, vaddr + mapping_size) ||
265 overlaps_interrupt_vector_text(vaddr, vaddr + mapping_size))
266 prot = PAGE_KERNEL_X;
270 rc = radix__map_kernel_page(vaddr, addr, prot, mapping_size);
275 print_mapping(start, addr, mapping_size);
279 static void __init radix_init_pgtable(void)
281 unsigned long rts_field;
282 struct memblock_region *reg;
284 /* We don't support slb for radix */
287 * Create the linear mapping, using standard page size for now
289 for_each_memblock(memory, reg)
290 WARN_ON(create_physical_mapping(reg->base,
291 reg->base + reg->size));
293 /* Find out how many PID bits are supported */
294 if (cpu_has_feature(CPU_FTR_HVMODE)) {
297 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
299 * When KVM is possible, we only use the top half of the
300 * PID space to avoid collisions between host and guest PIDs
301 * which can cause problems due to prefetch when exiting the
304 mmu_base_pid = 1 << (mmu_pid_bits - 1);
309 /* The guest uses the bottom half of the PID space */
316 * Allocate Partition table and process table for the
319 BUG_ON(PRTB_SIZE_SHIFT > 36);
320 process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT);
322 * Fill in the process table.
324 rts_field = radix__get_tree_size();
325 process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE);
327 * Fill in the partition table. We are suppose to use effective address
328 * of process table here. But our linear mapping also enable us to use
329 * physical address here.
331 register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12);
332 pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
333 asm volatile("ptesync" : : : "memory");
334 asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
335 "r" (TLBIEL_INVAL_SET_LPID), "r" (0));
336 asm volatile("eieio; tlbsync; ptesync" : : : "memory");
337 trace_tlbie(0, 0, TLBIEL_INVAL_SET_LPID, 0, 2, 1, 1);
340 * The init_mm context is given the first available (non-zero) PID,
341 * which is the "guard PID" and contains no page table. PIDR should
342 * never be set to zero because that duplicates the kernel address
343 * space at the 0x0... offset (quadrant 0)!
345 * An arbitrary PID that may later be allocated by the PID allocator
346 * for userspace processes must not be used either, because that
347 * would cause stale user mappings for that PID on CPUs outside of
348 * the TLB invalidation scheme (because it won't be in mm_cpumask).
350 * So permanently carve out one PID for the purpose of a guard PID.
352 init_mm.context.id = mmu_base_pid;
356 static void __init radix_init_partition_table(void)
358 unsigned long rts_field, dw0;
360 mmu_partition_table_init();
361 rts_field = radix__get_tree_size();
362 dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR;
363 mmu_partition_table_set_entry(0, dw0, 0);
365 pr_info("Initializing Radix MMU\n");
366 pr_info("Partition table %p\n", partition_tb);
369 void __init radix_init_native(void)
371 register_process_table = native_register_process_table;
374 static int __init get_idx_from_shift(unsigned int shift)
395 static int __init radix_dt_scan_page_sizes(unsigned long node,
396 const char *uname, int depth,
403 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
405 /* We are scanning "cpu" nodes only */
406 if (type == NULL || strcmp(type, "cpu") != 0)
409 /* Find MMU PID size */
410 prop = of_get_flat_dt_prop(node, "ibm,mmu-pid-bits", &size);
411 if (prop && size == 4)
412 mmu_pid_bits = be32_to_cpup(prop);
414 /* Grab page size encodings */
415 prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
419 pr_info("Page sizes from device-tree:\n");
420 for (; size >= 4; size -= 4, ++prop) {
422 struct mmu_psize_def *def;
424 /* top 3 bit is AP encoding */
425 shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
426 ap = be32_to_cpu(prop[0]) >> 29;
427 pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
429 idx = get_idx_from_shift(shift);
433 def = &mmu_psize_defs[idx];
439 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
443 void __init radix__early_init_devtree(void)
448 * Try to find the available page sizes in the device-tree
450 rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
451 if (rc != 0) /* Found */
454 * let's assume we have page 4k and 64k support
456 mmu_psize_defs[MMU_PAGE_4K].shift = 12;
457 mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;
459 mmu_psize_defs[MMU_PAGE_64K].shift = 16;
460 mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
462 #ifdef CONFIG_SPARSEMEM_VMEMMAP
463 if (mmu_psize_defs[MMU_PAGE_2M].shift) {
465 * map vmemmap using 2M if available
467 mmu_vmemmap_psize = MMU_PAGE_2M;
469 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
473 static void update_hid_for_radix(void)
476 unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
478 asm volatile("ptesync": : :"memory");
479 /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
480 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
481 : : "r"(rb), "i"(1), "i"(0), "i"(2), "r"(0) : "memory");
482 /* prs = 1, ric = 2, rs = 0, r = 1 is = 3 */
483 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
484 : : "r"(rb), "i"(1), "i"(1), "i"(2), "r"(0) : "memory");
485 asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
486 trace_tlbie(0, 0, rb, 0, 2, 0, 1);
487 trace_tlbie(0, 0, rb, 0, 2, 1, 1);
492 hid0 = mfspr(SPRN_HID0);
493 hid0 |= HID0_POWER9_RADIX;
494 mtspr(SPRN_HID0, hid0);
495 asm volatile("isync": : :"memory");
497 /* Wait for it to happen */
498 while (!(mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
502 static void radix_init_amor(void)
505 * In HV mode, we init AMOR (Authority Mask Override Register) so that
506 * the hypervisor and guest can setup IAMR (Instruction Authority Mask
507 * Register), enable key 0 and set it to 1.
509 * AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)
511 mtspr(SPRN_AMOR, (3ul << 62));
514 static void radix_init_iamr(void)
519 * The IAMR should set to 0 on DD1.
521 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
527 * Radix always uses key0 of the IAMR to determine if an access is
528 * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction
531 mtspr(SPRN_IAMR, iamr);
534 void __init radix__early_init_mmu(void)
538 #ifdef CONFIG_PPC_64K_PAGES
539 /* PAGE_SIZE mappings */
540 mmu_virtual_psize = MMU_PAGE_64K;
542 mmu_virtual_psize = MMU_PAGE_4K;
545 #ifdef CONFIG_SPARSEMEM_VMEMMAP
546 /* vmemmap mapping */
547 mmu_vmemmap_psize = mmu_virtual_psize;
550 * initialize page table size
552 __pte_index_size = RADIX_PTE_INDEX_SIZE;
553 __pmd_index_size = RADIX_PMD_INDEX_SIZE;
554 __pud_index_size = RADIX_PUD_INDEX_SIZE;
555 __pgd_index_size = RADIX_PGD_INDEX_SIZE;
556 __pmd_cache_index = RADIX_PMD_INDEX_SIZE;
557 __pte_table_size = RADIX_PTE_TABLE_SIZE;
558 __pmd_table_size = RADIX_PMD_TABLE_SIZE;
559 __pud_table_size = RADIX_PUD_TABLE_SIZE;
560 __pgd_table_size = RADIX_PGD_TABLE_SIZE;
562 __pmd_val_bits = RADIX_PMD_VAL_BITS;
563 __pud_val_bits = RADIX_PUD_VAL_BITS;
564 __pgd_val_bits = RADIX_PGD_VAL_BITS;
566 __kernel_virt_start = RADIX_KERN_VIRT_START;
567 __kernel_virt_size = RADIX_KERN_VIRT_SIZE;
568 __vmalloc_start = RADIX_VMALLOC_START;
569 __vmalloc_end = RADIX_VMALLOC_END;
570 __kernel_io_start = RADIX_KERN_IO_START;
571 vmemmap = (struct page *)RADIX_VMEMMAP_BASE;
572 ioremap_bot = IOREMAP_BASE;
575 pci_io_base = ISA_IO_BASE;
579 * For now radix also use the same frag size
581 __pte_frag_nr = H_PTE_FRAG_NR;
582 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
584 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
586 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
587 update_hid_for_radix();
588 lpcr = mfspr(SPRN_LPCR);
589 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
590 radix_init_partition_table();
593 radix_init_pseries();
596 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
599 radix_init_pgtable();
600 /* Switch to the guard PID before turning on MMU */
601 radix__switch_mmu_context(NULL, &init_mm);
602 if (cpu_has_feature(CPU_FTR_HVMODE))
606 void radix__early_init_mmu_secondary(void)
610 * update partition table control register and UPRT
612 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
614 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
615 update_hid_for_radix();
617 lpcr = mfspr(SPRN_LPCR);
618 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
621 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
626 radix__switch_mmu_context(NULL, &init_mm);
627 if (cpu_has_feature(CPU_FTR_HVMODE))
631 void radix__mmu_cleanup_all(void)
635 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
636 lpcr = mfspr(SPRN_LPCR);
637 mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
639 powernv_set_nmmu_ptcr(0);
640 radix__flush_tlb_all();
644 void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
645 phys_addr_t first_memblock_size)
647 /* We don't currently support the first MEMBLOCK not mapping 0
648 * physical on those processors
650 BUG_ON(first_memblock_base != 0);
653 * Radix mode is not limited by RMA / VRMA addressing.
655 ppc64_rma_size = ULONG_MAX;
658 #ifdef CONFIG_MEMORY_HOTPLUG
659 static void free_pte_table(pte_t *pte_start, pmd_t *pmd)
664 for (i = 0; i < PTRS_PER_PTE; i++) {
670 pte_free_kernel(&init_mm, pte_start);
674 static void free_pmd_table(pmd_t *pmd_start, pud_t *pud)
679 for (i = 0; i < PTRS_PER_PMD; i++) {
685 pmd_free(&init_mm, pmd_start);
689 struct change_mapping_params {
693 unsigned long aligned_start;
694 unsigned long aligned_end;
697 static int stop_machine_change_mapping(void *data)
699 struct change_mapping_params *params =
700 (struct change_mapping_params *)data;
705 spin_unlock(&init_mm.page_table_lock);
706 pte_clear(&init_mm, params->aligned_start, params->pte);
707 create_physical_mapping(params->aligned_start, params->start);
708 create_physical_mapping(params->end, params->aligned_end);
709 spin_lock(&init_mm.page_table_lock);
713 static void remove_pte_table(pte_t *pte_start, unsigned long addr,
719 pte = pte_start + pte_index(addr);
720 for (; addr < end; addr = next, pte++) {
721 next = (addr + PAGE_SIZE) & PAGE_MASK;
725 if (!pte_present(*pte))
728 if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(next)) {
730 * The vmemmap_free() and remove_section_mapping()
731 * codepaths call us with aligned addresses.
733 WARN_ONCE(1, "%s: unaligned range\n", __func__);
737 pte_clear(&init_mm, addr, pte);
742 * clear the pte and potentially split the mapping helper
744 static void split_kernel_mapping(unsigned long addr, unsigned long end,
745 unsigned long size, pte_t *pte)
747 unsigned long mask = ~(size - 1);
748 unsigned long aligned_start = addr & mask;
749 unsigned long aligned_end = addr + size;
750 struct change_mapping_params params;
751 bool split_region = false;
753 if ((end - addr) < size) {
755 * We're going to clear the PTE, but not flushed
756 * the mapping, time to remap and flush. The
757 * effects if visible outside the processor or
758 * if we are running in code close to the
759 * mapping we cleared, we are in trouble.
761 if (overlaps_kernel_text(aligned_start, addr) ||
762 overlaps_kernel_text(end, aligned_end)) {
764 * Hack, just return, don't pte_clear
766 WARN_ONCE(1, "Linear mapping %lx->%lx overlaps kernel "
767 "text, not splitting\n", addr, end);
777 params.aligned_start = addr & ~(size - 1);
778 params.aligned_end = min_t(unsigned long, aligned_end,
779 (unsigned long)__va(memblock_end_of_DRAM()));
780 stop_machine(stop_machine_change_mapping, ¶ms, NULL);
784 pte_clear(&init_mm, addr, pte);
787 static void remove_pmd_table(pmd_t *pmd_start, unsigned long addr,
794 pmd = pmd_start + pmd_index(addr);
795 for (; addr < end; addr = next, pmd++) {
796 next = pmd_addr_end(addr, end);
798 if (!pmd_present(*pmd))
801 if (pmd_huge(*pmd)) {
802 split_kernel_mapping(addr, end, PMD_SIZE, (pte_t *)pmd);
806 pte_base = (pte_t *)pmd_page_vaddr(*pmd);
807 remove_pte_table(pte_base, addr, next);
808 free_pte_table(pte_base, pmd);
812 static void remove_pud_table(pud_t *pud_start, unsigned long addr,
819 pud = pud_start + pud_index(addr);
820 for (; addr < end; addr = next, pud++) {
821 next = pud_addr_end(addr, end);
823 if (!pud_present(*pud))
826 if (pud_huge(*pud)) {
827 split_kernel_mapping(addr, end, PUD_SIZE, (pte_t *)pud);
831 pmd_base = (pmd_t *)pud_page_vaddr(*pud);
832 remove_pmd_table(pmd_base, addr, next);
833 free_pmd_table(pmd_base, pud);
837 static void remove_pagetable(unsigned long start, unsigned long end)
839 unsigned long addr, next;
843 spin_lock(&init_mm.page_table_lock);
845 for (addr = start; addr < end; addr = next) {
846 next = pgd_addr_end(addr, end);
848 pgd = pgd_offset_k(addr);
849 if (!pgd_present(*pgd))
852 if (pgd_huge(*pgd)) {
853 split_kernel_mapping(addr, end, PGDIR_SIZE, (pte_t *)pgd);
857 pud_base = (pud_t *)pgd_page_vaddr(*pgd);
858 remove_pud_table(pud_base, addr, next);
861 spin_unlock(&init_mm.page_table_lock);
862 radix__flush_tlb_kernel_range(start, end);
865 int __ref radix__create_section_mapping(unsigned long start, unsigned long end)
867 return create_physical_mapping(start, end);
870 int radix__remove_section_mapping(unsigned long start, unsigned long end)
872 remove_pagetable(start, end);
875 #endif /* CONFIG_MEMORY_HOTPLUG */
877 #ifdef CONFIG_SPARSEMEM_VMEMMAP
878 int __meminit radix__vmemmap_create_mapping(unsigned long start,
879 unsigned long page_size,
882 /* Create a PTE encoding */
883 unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW;
885 BUG_ON(radix__map_kernel_page(start, phys, __pgprot(flags), page_size));
889 #ifdef CONFIG_MEMORY_HOTPLUG
890 void radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
892 remove_pagetable(start, start + page_size);
897 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
899 unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
900 pmd_t *pmdp, unsigned long clr,
905 #ifdef CONFIG_DEBUG_VM
906 WARN_ON(!radix__pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp));
907 assert_spin_locked(&mm->page_table_lock);
910 old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
911 trace_hugepage_update(addr, old, clr, set);
916 pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
922 VM_BUG_ON(address & ~HPAGE_PMD_MASK);
923 VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
924 VM_BUG_ON(pmd_devmap(*pmdp));
926 * khugepaged calls this for normal pmd
931 /*FIXME!! Verify whether we need this kick below */
932 serialize_against_pte_lookup(vma->vm_mm);
934 radix__flush_tlb_collapsed_pmd(vma->vm_mm, address);
940 * For us pgtable_t is pte_t *. Inorder to save the deposisted
941 * page table, we consider the allocated page table as a list
942 * head. On withdraw we need to make sure we zero out the used
943 * list_head memory area.
945 void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
948 struct list_head *lh = (struct list_head *) pgtable;
950 assert_spin_locked(pmd_lockptr(mm, pmdp));
953 if (!pmd_huge_pte(mm, pmdp))
956 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
957 pmd_huge_pte(mm, pmdp) = pgtable;
960 pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
964 struct list_head *lh;
966 assert_spin_locked(pmd_lockptr(mm, pmdp));
969 pgtable = pmd_huge_pte(mm, pmdp);
970 lh = (struct list_head *) pgtable;
972 pmd_huge_pte(mm, pmdp) = NULL;
974 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
977 ptep = (pte_t *) pgtable;
985 pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
986 unsigned long addr, pmd_t *pmdp)
991 old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
992 old_pmd = __pmd(old);
994 * Serialize against find_current_mm_pte which does lock-less
995 * lookup in page tables with local interrupts disabled. For huge pages
996 * it casts pmd_t to pte_t. Since format of pte_t is different from
997 * pmd_t we want to prevent transit from pmd pointing to page table
998 * to pmd pointing to huge page (and back) while interrupts are disabled.
999 * We clear pmd to possibly replace it with page table pointer in
1000 * different code paths. So make sure we wait for the parallel
1001 * find_current_mm_pte to finish.
1003 serialize_against_pte_lookup(mm);
1007 int radix__has_transparent_hugepage(void)
1009 /* For radix 2M at PMD level means thp */
1010 if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
1014 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */