3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
6 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
7 * Copyright (C) 1996 Paul Mackerras
8 * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
9 * PPC44x/36-bit changes by Matt Porter (mporter@mvista.com)
11 * Derived from "arch/i386/mm/init.c"
12 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
21 #include <linux/config.h>
22 #include <linux/module.h>
23 #include <linux/sched.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
27 #include <linux/types.h>
29 #include <linux/stddef.h>
30 #include <linux/init.h>
31 #include <linux/bootmem.h>
32 #include <linux/highmem.h>
33 #include <linux/initrd.h>
34 #include <linux/pagemap.h>
36 #include <asm/pgalloc.h>
39 #include <asm/mmu_context.h>
40 #include <asm/pgtable.h>
43 #include <asm/machdep.h>
44 #include <asm/btext.h>
46 #include <asm/bootinfo.h>
49 #include "mem_pieces.h"
52 #ifndef CPU_FTR_COHERENT_ICACHE
53 #define CPU_FTR_COHERENT_ICACHE 0 /* XXX for now */
54 #define CPU_FTR_NOEXECUTE 0
58 * This is called by /dev/mem to know if a given address has to
59 * be mapped non-cacheable or not
61 int page_is_ram(unsigned long pfn)
63 unsigned long paddr = (pfn << PAGE_SHIFT);
65 #ifndef CONFIG_PPC64 /* XXX for now */
66 return paddr < __pa(high_memory);
69 for (i=0; i < lmb.memory.cnt; i++) {
72 base = lmb.memory.region[i].base;
74 if ((paddr >= base) &&
75 (paddr < (base + lmb.memory.region[i].size))) {
83 EXPORT_SYMBOL(page_is_ram);
85 pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr,
86 unsigned long size, pgprot_t vma_prot)
88 if (ppc_md.phys_mem_access_prot)
89 return ppc_md.phys_mem_access_prot(file, addr, size, vma_prot);
91 if (!page_is_ram(addr >> PAGE_SHIFT))
92 vma_prot = __pgprot(pgprot_val(vma_prot)
93 | _PAGE_GUARDED | _PAGE_NO_CACHE);
96 EXPORT_SYMBOL(phys_mem_access_prot);
100 unsigned long total = 0, reserved = 0;
101 unsigned long shared = 0, cached = 0;
102 unsigned long highmem = 0;
107 printk("Mem-info:\n");
109 printk("Free swap: %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10));
110 for_each_pgdat(pgdat) {
111 for (i = 0; i < pgdat->node_spanned_pages; i++) {
112 page = pgdat_page_nr(pgdat, i);
114 if (PageHighMem(page))
116 if (PageReserved(page))
118 else if (PageSwapCache(page))
120 else if (page_count(page))
121 shared += page_count(page) - 1;
124 printk("%ld pages of RAM\n", total);
125 #ifdef CONFIG_HIGHMEM
126 printk("%ld pages of HIGHMEM\n", highmem);
128 printk("%ld reserved pages\n", reserved);
129 printk("%ld pages shared\n", shared);
130 printk("%ld pages swap cached\n", cached);
134 * This is called when a page has been modified by the kernel.
135 * It just marks the page as not i-cache clean. We do the i-cache
136 * flush later when the page is given to a user process, if necessary.
138 void flush_dcache_page(struct page *page)
140 if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
142 /* avoid an atomic op if possible */
143 if (test_bit(PG_arch_1, &page->flags))
144 clear_bit(PG_arch_1, &page->flags);
146 EXPORT_SYMBOL(flush_dcache_page);
148 void flush_dcache_icache_page(struct page *page)
151 void *start = kmap_atomic(page, KM_PPC_SYNC_ICACHE);
152 __flush_dcache_icache(start);
153 kunmap_atomic(start, KM_PPC_SYNC_ICACHE);
154 #elif defined(CONFIG_8xx)
155 /* On 8xx there is no need to kmap since highmem is not supported */
156 __flush_dcache_icache(page_address(page));
158 __flush_dcache_icache_phys(page_to_pfn(page) << PAGE_SHIFT);
162 void clear_user_page(void *page, unsigned long vaddr, struct page *pg)
166 if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
169 * We shouldnt have to do this, but some versions of glibc
170 * require it (ld.so assumes zero filled pages are icache clean)
174 /* avoid an atomic op if possible */
175 if (test_bit(PG_arch_1, &pg->flags))
176 clear_bit(PG_arch_1, &pg->flags);
178 EXPORT_SYMBOL(clear_user_page);
180 void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
183 copy_page(vto, vfrom);
186 * We should be able to use the following optimisation, however
187 * there are two problems.
188 * Firstly a bug in some versions of binutils meant PLT sections
189 * were not marked executable.
190 * Secondly the first word in the GOT section is blrl, used
191 * to establish the GOT address. Until recently the GOT was
192 * not marked executable.
196 if (!vma->vm_file && ((vma->vm_flags & VM_EXEC) == 0))
200 if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
203 /* avoid an atomic op if possible */
204 if (test_bit(PG_arch_1, &pg->flags))
205 clear_bit(PG_arch_1, &pg->flags);
208 void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
209 unsigned long addr, int len)
213 maddr = (unsigned long) kmap(page) + (addr & ~PAGE_MASK);
214 flush_icache_range(maddr, maddr + len);
217 EXPORT_SYMBOL(flush_icache_user_range);
220 * This is called at the end of handling a user page fault, when the
221 * fault has been handled by updating a PTE in the linux page tables.
222 * We use it to preload an HPTE into the hash table corresponding to
223 * the updated linux PTE.
225 * This must always be called with the mm->page_table_lock held
227 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
230 /* handle i-cache coherency */
231 unsigned long pfn = pte_pfn(pte);
243 /* handle i-cache coherency */
244 if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE) &&
245 !cpu_has_feature(CPU_FTR_NOEXECUTE) &&
247 struct page *page = pfn_to_page(pfn);
248 if (!PageReserved(page)
249 && !test_bit(PG_arch_1, &page->flags)) {
250 if (vma->vm_mm == current->active_mm) {
252 /* On 8xx, cache control instructions (particularly
253 * "dcbst" from flush_dcache_icache) fault as write
254 * operation if there is an unpopulated TLB entry
255 * for the address in question. To workaround that,
256 * we invalidate the TLB here, thus avoiding dcbst
261 __flush_dcache_icache((void *) address);
263 flush_dcache_icache_page(page);
264 set_bit(PG_arch_1, &page->flags);
268 #ifdef CONFIG_PPC_STD_MMU
269 /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
270 if (!pte_young(pte) || address >= TASK_SIZE)
275 pmd = pmd_offset(pgd_offset(vma->vm_mm, address), address);
277 add_hash_page(vma->vm_mm->context, address, pmd_val(*pmd));
279 pgdir = vma->vm_mm->pgd;
283 ptep = find_linux_pte(pgdir, ea);
287 vsid = get_vsid(vma->vm_mm->context.id, ea);
289 local_irq_save(flags);
290 tmp = cpumask_of_cpu(smp_processor_id());
291 if (cpus_equal(vma->vm_mm->cpu_vm_mask, tmp))
294 __hash_page(ea, pte_val(pte) & (_PAGE_USER|_PAGE_RW), vsid, ptep,
296 local_irq_restore(flags);