2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #define pr_fmt(fmt) "hash-mmu: " fmt
25 #include <linux/spinlock.h>
26 #include <linux/errno.h>
27 #include <linux/sched/mm.h>
28 #include <linux/proc_fs.h>
29 #include <linux/stat.h>
30 #include <linux/sysctl.h>
31 #include <linux/export.h>
32 #include <linux/ctype.h>
33 #include <linux/cache.h>
34 #include <linux/init.h>
35 #include <linux/signal.h>
36 #include <linux/memblock.h>
37 #include <linux/context_tracking.h>
38 #include <linux/libfdt.h>
39 #include <linux/pkeys.h>
41 #include <asm/debugfs.h>
42 #include <asm/processor.h>
43 #include <asm/pgtable.h>
45 #include <asm/mmu_context.h>
47 #include <asm/types.h>
48 #include <linux/uaccess.h>
49 #include <asm/machdep.h>
54 #include <asm/cacheflush.h>
55 #include <asm/cputable.h>
56 #include <asm/sections.h>
57 #include <asm/copro.h>
59 #include <asm/code-patching.h>
60 #include <asm/fadump.h>
61 #include <asm/firmware.h>
63 #include <asm/trace.h>
65 #include <asm/pte-walk.h>
66 #include <asm/asm-prototypes.h>
69 #define DBG(fmt...) udbg_printf(fmt)
75 #define DBG_LOW(fmt...) udbg_printf(fmt)
77 #define DBG_LOW(fmt...)
85 * Note: pte --> Linux PTE
86 * HPTE --> PowerPC Hashed Page Table Entry
89 * htab_initialize is called with the MMU off (of course), but
90 * the kernel has been copied down to zero so it can directly
91 * reference global data. At this point it is very difficult
92 * to print debug info.
96 static unsigned long _SDR1;
97 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
98 EXPORT_SYMBOL_GPL(mmu_psize_defs);
100 u8 hpte_page_sizes[1 << LP_BITS];
101 EXPORT_SYMBOL_GPL(hpte_page_sizes);
103 struct hash_pte *htab_address;
104 unsigned long htab_size_bytes;
105 unsigned long htab_hash_mask;
106 EXPORT_SYMBOL_GPL(htab_hash_mask);
107 int mmu_linear_psize = MMU_PAGE_4K;
108 EXPORT_SYMBOL_GPL(mmu_linear_psize);
109 int mmu_virtual_psize = MMU_PAGE_4K;
110 int mmu_vmalloc_psize = MMU_PAGE_4K;
111 #ifdef CONFIG_SPARSEMEM_VMEMMAP
112 int mmu_vmemmap_psize = MMU_PAGE_4K;
114 int mmu_io_psize = MMU_PAGE_4K;
115 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
116 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
117 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
118 u16 mmu_slb_size = 64;
119 EXPORT_SYMBOL_GPL(mmu_slb_size);
120 #ifdef CONFIG_PPC_64K_PAGES
121 int mmu_ci_restrictions;
123 #ifdef CONFIG_DEBUG_PAGEALLOC
124 static u8 *linear_map_hash_slots;
125 static unsigned long linear_map_hash_count;
126 static DEFINE_SPINLOCK(linear_map_hash_lock);
127 #endif /* CONFIG_DEBUG_PAGEALLOC */
128 struct mmu_hash_ops mmu_hash_ops;
129 EXPORT_SYMBOL(mmu_hash_ops);
131 /* There are definitions of page sizes arrays to be used when none
132 * is provided by the firmware.
136 * Fallback (4k pages only)
138 static struct mmu_psize_def mmu_psize_defaults[] = {
142 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
148 /* POWER4, GPUL, POWER5
150 * Support for 16Mb large pages
152 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
156 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
163 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
164 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
171 * 'R' and 'C' update notes:
172 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
173 * create writeable HPTEs without C set, because the hcall H_PROTECT
174 * that we use in that case will not update C
175 * - The above is however not a problem, because we also don't do that
176 * fancy "no flush" variant of eviction and we use H_REMOVE which will
177 * do the right thing and thus we don't have the race I described earlier
179 * - Under bare metal, we do have the race, so we need R and C set
180 * - We make sure R is always set and never lost
181 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
183 unsigned long htab_convert_pte_flags(unsigned long pteflags)
185 unsigned long rflags = 0;
187 /* _PAGE_EXEC -> NOEXEC */
188 if ((pteflags & _PAGE_EXEC) == 0)
192 * Linux uses slb key 0 for kernel and 1 for user.
193 * kernel RW areas are mapped with PPP=0b000
194 * User area is mapped with PPP=0b010 for read/write
195 * or PPP=0b011 for read-only (including writeable but clean pages).
197 if (pteflags & _PAGE_PRIVILEGED) {
199 * Kernel read only mapped with ppp bits 0b110
201 if (!(pteflags & _PAGE_WRITE)) {
202 if (mmu_has_feature(MMU_FTR_KERNEL_RO))
203 rflags |= (HPTE_R_PP0 | 0x2);
208 if (pteflags & _PAGE_RWX)
210 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
214 * We can't allow hardware to update hpte bits. Hence always
215 * set 'R' bit and set 'C' if it is a write fault
219 if (pteflags & _PAGE_DIRTY)
225 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
227 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
228 rflags |= (HPTE_R_I | HPTE_R_G);
229 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
230 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
233 * Add memory coherence if cache inhibited is not set
237 rflags |= pte_to_hpte_pkey_bits(pteflags);
241 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
242 unsigned long pstart, unsigned long prot,
243 int psize, int ssize)
245 unsigned long vaddr, paddr;
246 unsigned int step, shift;
249 shift = mmu_psize_defs[psize].shift;
252 prot = htab_convert_pte_flags(prot);
254 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
255 vstart, vend, pstart, prot, psize, ssize);
257 for (vaddr = vstart, paddr = pstart; vaddr < vend;
258 vaddr += step, paddr += step) {
259 unsigned long hash, hpteg;
260 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
261 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
262 unsigned long tprot = prot;
265 * If we hit a bad address return error.
269 /* Make kernel text executable */
270 if (overlaps_kernel_text(vaddr, vaddr + step))
273 /* Make kvm guest trampolines executable */
274 if (overlaps_kvm_tmp(vaddr, vaddr + step))
278 * If relocatable, check if it overlaps interrupt vectors that
279 * are copied down to real 0. For relocatable kernel
280 * (e.g. kdump case) we copy interrupt vectors down to real
281 * address 0. Mark that region as executable. This is
282 * because on p8 system with relocation on exception feature
283 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
284 * in order to execute the interrupt handlers in virtual
285 * mode the vector region need to be marked as executable.
287 if ((PHYSICAL_START > MEMORY_START) &&
288 overlaps_interrupt_vector_text(vaddr, vaddr + step))
291 hash = hpt_hash(vpn, shift, ssize);
292 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
294 BUG_ON(!mmu_hash_ops.hpte_insert);
295 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
296 HPTE_V_BOLTED, psize, psize,
302 #ifdef CONFIG_DEBUG_PAGEALLOC
303 if (debug_pagealloc_enabled() &&
304 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
305 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
306 #endif /* CONFIG_DEBUG_PAGEALLOC */
308 return ret < 0 ? ret : 0;
311 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
312 int psize, int ssize)
315 unsigned int step, shift;
319 shift = mmu_psize_defs[psize].shift;
322 if (!mmu_hash_ops.hpte_removebolted)
325 for (vaddr = vstart; vaddr < vend; vaddr += step) {
326 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
338 static bool disable_1tb_segments = false;
340 static int __init parse_disable_1tb_segments(char *p)
342 disable_1tb_segments = true;
345 early_param("disable_1tb_segments", parse_disable_1tb_segments);
347 static int __init htab_dt_scan_seg_sizes(unsigned long node,
348 const char *uname, int depth,
351 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
355 /* We are scanning "cpu" nodes only */
356 if (type == NULL || strcmp(type, "cpu") != 0)
359 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
362 for (; size >= 4; size -= 4, ++prop) {
363 if (be32_to_cpu(prop[0]) == 40) {
364 DBG("1T segment support detected\n");
366 if (disable_1tb_segments) {
367 DBG("1T segments disabled by command line\n");
371 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
375 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
379 static int __init get_idx_from_shift(unsigned int shift)
403 static int __init htab_dt_scan_page_sizes(unsigned long node,
404 const char *uname, int depth,
407 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
411 /* We are scanning "cpu" nodes only */
412 if (type == NULL || strcmp(type, "cpu") != 0)
415 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
419 pr_info("Page sizes from device-tree:\n");
421 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
423 unsigned int base_shift = be32_to_cpu(prop[0]);
424 unsigned int slbenc = be32_to_cpu(prop[1]);
425 unsigned int lpnum = be32_to_cpu(prop[2]);
426 struct mmu_psize_def *def;
429 size -= 3; prop += 3;
430 base_idx = get_idx_from_shift(base_shift);
432 /* skip the pte encoding also */
433 prop += lpnum * 2; size -= lpnum * 2;
436 def = &mmu_psize_defs[base_idx];
437 if (base_idx == MMU_PAGE_16M)
438 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
440 def->shift = base_shift;
441 if (base_shift <= 23)
444 def->avpnm = (1 << (base_shift - 23)) - 1;
447 * We don't know for sure what's up with tlbiel, so
448 * for now we only set it for 4K and 64K pages
450 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
455 while (size > 0 && lpnum) {
456 unsigned int shift = be32_to_cpu(prop[0]);
457 int penc = be32_to_cpu(prop[1]);
459 prop += 2; size -= 2;
462 idx = get_idx_from_shift(shift);
467 pr_err("Invalid penc for base_shift=%d "
468 "shift=%d\n", base_shift, shift);
470 def->penc[idx] = penc;
471 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
472 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
473 base_shift, shift, def->sllp,
474 def->avpnm, def->tlbiel, def->penc[idx]);
481 #ifdef CONFIG_HUGETLB_PAGE
482 /* Scan for 16G memory blocks that have been set aside for huge pages
483 * and reserve those blocks for 16G huge pages.
485 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
486 const char *uname, int depth,
488 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
489 const __be64 *addr_prop;
490 const __be32 *page_count_prop;
491 unsigned int expected_pages;
492 long unsigned int phys_addr;
493 long unsigned int block_size;
495 /* We are scanning "memory" nodes only */
496 if (type == NULL || strcmp(type, "memory") != 0)
499 /* This property is the log base 2 of the number of virtual pages that
500 * will represent this memory block. */
501 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
502 if (page_count_prop == NULL)
504 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
505 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
506 if (addr_prop == NULL)
508 phys_addr = be64_to_cpu(addr_prop[0]);
509 block_size = be64_to_cpu(addr_prop[1]);
510 if (block_size != (16 * GB))
512 printk(KERN_INFO "Huge page(16GB) memory: "
513 "addr = 0x%lX size = 0x%lX pages = %d\n",
514 phys_addr, block_size, expected_pages);
515 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
516 memblock_reserve(phys_addr, block_size * expected_pages);
517 pseries_add_gpage(phys_addr, block_size, expected_pages);
521 #endif /* CONFIG_HUGETLB_PAGE */
523 static void mmu_psize_set_default_penc(void)
526 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
527 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
528 mmu_psize_defs[bpsize].penc[apsize] = -1;
531 #ifdef CONFIG_PPC_64K_PAGES
533 static bool might_have_hea(void)
536 * The HEA ethernet adapter requires awareness of the
537 * GX bus. Without that awareness we can easily assume
538 * we will never see an HEA ethernet device.
540 #ifdef CONFIG_IBMEBUS
541 return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
542 firmware_has_feature(FW_FEATURE_SPLPAR);
548 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
550 static void __init htab_scan_page_sizes(void)
554 /* se the invalid penc to -1 */
555 mmu_psize_set_default_penc();
557 /* Default to 4K pages only */
558 memcpy(mmu_psize_defs, mmu_psize_defaults,
559 sizeof(mmu_psize_defaults));
562 * Try to find the available page sizes in the device-tree
564 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
565 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
567 * Nothing in the device-tree, but the CPU supports 16M pages,
568 * so let's fallback on a known size list for 16M capable CPUs.
570 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
571 sizeof(mmu_psize_defaults_gp));
574 #ifdef CONFIG_HUGETLB_PAGE
575 if (!hugetlb_disabled) {
576 /* Reserve 16G huge page memory sections for huge pages */
577 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
579 #endif /* CONFIG_HUGETLB_PAGE */
583 * Fill in the hpte_page_sizes[] array.
584 * We go through the mmu_psize_defs[] array looking for all the
585 * supported base/actual page size combinations. Each combination
586 * has a unique pagesize encoding (penc) value in the low bits of
587 * the LP field of the HPTE. For actual page sizes less than 1MB,
588 * some of the upper LP bits are used for RPN bits, meaning that
589 * we need to fill in several entries in hpte_page_sizes[].
591 * In diagrammatic form, with r = RPN bits and z = page size bits:
592 * PTE LP actual page size
599 * The zzzz bits are implementation-specific but are chosen so that
600 * no encoding for a larger page size uses the same value in its
601 * low-order N bits as the encoding for the 2^(12+N) byte page size
604 static void init_hpte_page_sizes(void)
607 long int shift, penc;
609 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
610 if (!mmu_psize_defs[bp].shift)
611 continue; /* not a supported page size */
612 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
613 penc = mmu_psize_defs[bp].penc[ap];
614 if (penc == -1 || !mmu_psize_defs[ap].shift)
616 shift = mmu_psize_defs[ap].shift - LP_SHIFT;
618 continue; /* should never happen */
620 * For page sizes less than 1MB, this loop
621 * replicates the entry for all possible values
624 while (penc < (1 << LP_BITS)) {
625 hpte_page_sizes[penc] = (ap << 4) | bp;
632 static void __init htab_init_page_sizes(void)
634 init_hpte_page_sizes();
636 if (!debug_pagealloc_enabled()) {
638 * Pick a size for the linear mapping. Currently, we only
639 * support 16M, 1M and 4K which is the default
641 if (mmu_psize_defs[MMU_PAGE_16M].shift)
642 mmu_linear_psize = MMU_PAGE_16M;
643 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
644 mmu_linear_psize = MMU_PAGE_1M;
647 #ifdef CONFIG_PPC_64K_PAGES
649 * Pick a size for the ordinary pages. Default is 4K, we support
650 * 64K for user mappings and vmalloc if supported by the processor.
651 * We only use 64k for ioremap if the processor
652 * (and firmware) support cache-inhibited large pages.
653 * If not, we use 4k and set mmu_ci_restrictions so that
654 * hash_page knows to switch processes that use cache-inhibited
655 * mappings to 4k pages.
657 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
658 mmu_virtual_psize = MMU_PAGE_64K;
659 mmu_vmalloc_psize = MMU_PAGE_64K;
660 if (mmu_linear_psize == MMU_PAGE_4K)
661 mmu_linear_psize = MMU_PAGE_64K;
662 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
664 * When running on pSeries using 64k pages for ioremap
665 * would stop us accessing the HEA ethernet. So if we
666 * have the chance of ever seeing one, stay at 4k.
668 if (!might_have_hea())
669 mmu_io_psize = MMU_PAGE_64K;
671 mmu_ci_restrictions = 1;
673 #endif /* CONFIG_PPC_64K_PAGES */
675 #ifdef CONFIG_SPARSEMEM_VMEMMAP
676 /* We try to use 16M pages for vmemmap if that is supported
677 * and we have at least 1G of RAM at boot
679 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
680 memblock_phys_mem_size() >= 0x40000000)
681 mmu_vmemmap_psize = MMU_PAGE_16M;
682 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
683 mmu_vmemmap_psize = MMU_PAGE_64K;
685 mmu_vmemmap_psize = MMU_PAGE_4K;
686 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
688 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
689 "virtual = %d, io = %d"
690 #ifdef CONFIG_SPARSEMEM_VMEMMAP
694 mmu_psize_defs[mmu_linear_psize].shift,
695 mmu_psize_defs[mmu_virtual_psize].shift,
696 mmu_psize_defs[mmu_io_psize].shift
697 #ifdef CONFIG_SPARSEMEM_VMEMMAP
698 ,mmu_psize_defs[mmu_vmemmap_psize].shift
703 static int __init htab_dt_scan_pftsize(unsigned long node,
704 const char *uname, int depth,
707 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
710 /* We are scanning "cpu" nodes only */
711 if (type == NULL || strcmp(type, "cpu") != 0)
714 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
716 /* pft_size[0] is the NUMA CEC cookie */
717 ppc64_pft_size = be32_to_cpu(prop[1]);
723 unsigned htab_shift_for_mem_size(unsigned long mem_size)
725 unsigned memshift = __ilog2(mem_size);
726 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
729 /* round mem_size up to next power of 2 */
730 if ((1UL << memshift) < mem_size)
733 /* aim for 2 pages / pteg */
734 pteg_shift = memshift - (pshift + 1);
737 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
738 * size permitted by the architecture.
740 return max(pteg_shift + 7, 18U);
743 static unsigned long __init htab_get_table_size(void)
745 /* If hash size isn't already provided by the platform, we try to
746 * retrieve it from the device-tree. If it's not there neither, we
747 * calculate it now based on the total RAM size
749 if (ppc64_pft_size == 0)
750 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
752 return 1UL << ppc64_pft_size;
754 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
757 #ifdef CONFIG_MEMORY_HOTPLUG
758 void resize_hpt_for_hotplug(unsigned long new_mem_size)
760 unsigned target_hpt_shift;
762 if (!mmu_hash_ops.resize_hpt)
765 target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
768 * To avoid lots of HPT resizes if memory size is fluctuating
769 * across a boundary, we deliberately have some hysterisis
770 * here: we immediately increase the HPT size if the target
771 * shift exceeds the current shift, but we won't attempt to
772 * reduce unless the target shift is at least 2 below the
775 if ((target_hpt_shift > ppc64_pft_size)
776 || (target_hpt_shift < (ppc64_pft_size - 1))) {
779 rc = mmu_hash_ops.resize_hpt(target_hpt_shift);
780 if (rc && (rc != -ENODEV))
782 "Unable to resize hash page table to target order %d: %d\n",
783 target_hpt_shift, rc);
787 int hash__create_section_mapping(unsigned long start, unsigned long end, int nid)
789 int rc = htab_bolt_mapping(start, end, __pa(start),
790 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
794 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
796 BUG_ON(rc2 && (rc2 != -ENOENT));
801 int hash__remove_section_mapping(unsigned long start, unsigned long end)
803 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
808 #endif /* CONFIG_MEMORY_HOTPLUG */
810 static void __init hash_init_partition_table(phys_addr_t hash_table,
811 unsigned long htab_size)
813 mmu_partition_table_init();
816 * PS field (VRMA page size) is not used for LPID 0, hence set to 0.
817 * For now, UPRT is 0 and we have no segment table.
819 htab_size = __ilog2(htab_size) - 18;
820 mmu_partition_table_set_entry(0, hash_table | htab_size, 0);
821 pr_info("Partition table %p\n", partition_tb);
824 static void __init htab_initialize(void)
827 unsigned long pteg_count;
829 unsigned long base = 0, size = 0;
830 struct memblock_region *reg;
832 DBG(" -> htab_initialize()\n");
834 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
835 mmu_kernel_ssize = MMU_SEGSIZE_1T;
836 mmu_highuser_ssize = MMU_SEGSIZE_1T;
837 printk(KERN_INFO "Using 1TB segments\n");
841 * Calculate the required size of the htab. We want the number of
842 * PTEGs to equal one half the number of real pages.
844 htab_size_bytes = htab_get_table_size();
845 pteg_count = htab_size_bytes >> 7;
847 htab_hash_mask = pteg_count - 1;
849 if (firmware_has_feature(FW_FEATURE_LPAR) ||
850 firmware_has_feature(FW_FEATURE_PS3_LV1)) {
851 /* Using a hypervisor which owns the htab */
855 * On POWER9, we need to do a H_REGISTER_PROC_TBL hcall
856 * to inform the hypervisor that we wish to use the HPT.
858 if (cpu_has_feature(CPU_FTR_ARCH_300))
859 register_process_table(0, 0, 0);
860 #ifdef CONFIG_FA_DUMP
862 * If firmware assisted dump is active firmware preserves
863 * the contents of htab along with entire partition memory.
864 * Clear the htab if firmware assisted dump is active so
865 * that we dont end up using old mappings.
867 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
868 mmu_hash_ops.hpte_clear_all();
871 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
873 #ifdef CONFIG_PPC_CELL
875 * Cell may require the hash table down low when using the
876 * Axon IOMMU in order to fit the dynamic region over it, see
877 * comments in cell/iommu.c
879 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
881 pr_info("Hash table forced below 2G for Axon IOMMU\n");
883 #endif /* CONFIG_PPC_CELL */
885 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes,
888 DBG("Hash table allocated at %lx, size: %lx\n", table,
891 htab_address = __va(table);
893 /* htab absolute addr + encoded htabsize */
894 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
896 /* Initialize the HPT with no entries */
897 memset((void *)table, 0, htab_size_bytes);
899 if (!cpu_has_feature(CPU_FTR_ARCH_300))
901 mtspr(SPRN_SDR1, _SDR1);
903 hash_init_partition_table(table, htab_size_bytes);
906 prot = pgprot_val(PAGE_KERNEL);
908 #ifdef CONFIG_DEBUG_PAGEALLOC
909 if (debug_pagealloc_enabled()) {
910 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
911 linear_map_hash_slots = __va(memblock_alloc_base(
912 linear_map_hash_count, 1, ppc64_rma_size));
913 memset(linear_map_hash_slots, 0, linear_map_hash_count);
915 #endif /* CONFIG_DEBUG_PAGEALLOC */
917 /* create bolted the linear mapping in the hash table */
918 for_each_memblock(memory, reg) {
919 base = (unsigned long)__va(reg->base);
922 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
925 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
926 prot, mmu_linear_psize, mmu_kernel_ssize));
928 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
931 * If we have a memory_limit and we've allocated TCEs then we need to
932 * explicitly map the TCE area at the top of RAM. We also cope with the
933 * case that the TCEs start below memory_limit.
934 * tce_alloc_start/end are 16MB aligned so the mapping should work
935 * for either 4K or 16MB pages.
937 if (tce_alloc_start) {
938 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
939 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
941 if (base + size >= tce_alloc_start)
942 tce_alloc_start = base + size + 1;
944 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
945 __pa(tce_alloc_start), prot,
946 mmu_linear_psize, mmu_kernel_ssize));
950 DBG(" <- htab_initialize()\n");
955 void __init hash__early_init_devtree(void)
957 /* Initialize segment sizes */
958 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
960 /* Initialize page sizes */
961 htab_scan_page_sizes();
964 void __init hash__early_init_mmu(void)
966 #ifndef CONFIG_PPC_64K_PAGES
968 * We have code in __hash_page_4K() and elsewhere, which assumes it can
970 * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);
972 * Where the slot number is between 0-15, and values of 8-15 indicate
973 * the secondary bucket. For that code to work H_PAGE_F_SECOND and
974 * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and
975 * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here
976 * with a BUILD_BUG_ON().
978 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3)));
979 #endif /* CONFIG_PPC_64K_PAGES */
981 htab_init_page_sizes();
984 * initialize page table size
986 __pte_frag_nr = H_PTE_FRAG_NR;
987 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
988 __pmd_frag_nr = H_PMD_FRAG_NR;
989 __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT;
991 __pte_index_size = H_PTE_INDEX_SIZE;
992 __pmd_index_size = H_PMD_INDEX_SIZE;
993 __pud_index_size = H_PUD_INDEX_SIZE;
994 __pgd_index_size = H_PGD_INDEX_SIZE;
995 __pud_cache_index = H_PUD_CACHE_INDEX;
996 __pte_table_size = H_PTE_TABLE_SIZE;
997 __pmd_table_size = H_PMD_TABLE_SIZE;
998 __pud_table_size = H_PUD_TABLE_SIZE;
999 __pgd_table_size = H_PGD_TABLE_SIZE;
1001 * 4k use hugepd format, so for hash set then to
1004 __pmd_val_bits = HASH_PMD_VAL_BITS;
1005 __pud_val_bits = HASH_PUD_VAL_BITS;
1006 __pgd_val_bits = HASH_PGD_VAL_BITS;
1008 __kernel_virt_start = H_KERN_VIRT_START;
1009 __kernel_virt_size = H_KERN_VIRT_SIZE;
1010 __vmalloc_start = H_VMALLOC_START;
1011 __vmalloc_end = H_VMALLOC_END;
1012 __kernel_io_start = H_KERN_IO_START;
1013 vmemmap = (struct page *)H_VMEMMAP_BASE;
1014 ioremap_bot = IOREMAP_BASE;
1017 pci_io_base = ISA_IO_BASE;
1020 /* Select appropriate backend */
1021 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1022 ps3_early_mm_init();
1023 else if (firmware_has_feature(FW_FEATURE_LPAR))
1024 hpte_init_pseries();
1025 else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1028 if (!mmu_hash_ops.hpte_insert)
1029 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1031 /* Initialize the MMU Hash table and create the linear mapping
1032 * of memory. Has to be done before SLB initialization as this is
1033 * currently where the page size encoding is obtained.
1037 pr_info("Initializing hash mmu with SLB\n");
1038 /* Initialize SLB management */
1041 if (cpu_has_feature(CPU_FTR_ARCH_206)
1042 && cpu_has_feature(CPU_FTR_HVMODE))
1047 void hash__early_init_mmu_secondary(void)
1049 /* Initialize hash table for that CPU */
1050 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1052 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1053 mtspr(SPRN_SDR1, _SDR1);
1056 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
1058 /* Initialize SLB */
1061 if (cpu_has_feature(CPU_FTR_ARCH_206)
1062 && cpu_has_feature(CPU_FTR_HVMODE))
1065 #endif /* CONFIG_SMP */
1068 * Called by asm hashtable.S for doing lazy icache flush
1070 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1074 if (!pfn_valid(pte_pfn(pte)))
1077 page = pte_page(pte);
1080 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1081 if (trap == 0x400) {
1082 flush_dcache_icache_page(page);
1083 set_bit(PG_arch_1, &page->flags);
1090 #ifdef CONFIG_PPC_MM_SLICES
1091 static unsigned int get_paca_psize(unsigned long addr)
1093 unsigned char *psizes;
1094 unsigned long index, mask_index;
1096 if (addr < SLICE_LOW_TOP) {
1097 psizes = get_paca()->mm_ctx_low_slices_psize;
1098 index = GET_LOW_SLICE_INDEX(addr);
1100 psizes = get_paca()->mm_ctx_high_slices_psize;
1101 index = GET_HIGH_SLICE_INDEX(addr);
1103 mask_index = index & 0x1;
1104 return (psizes[index >> 1] >> (mask_index * 4)) & 0xF;
1108 unsigned int get_paca_psize(unsigned long addr)
1110 return get_paca()->mm_ctx_user_psize;
1115 * Demote a segment to using 4k pages.
1116 * For now this makes the whole process use 4k pages.
1118 #ifdef CONFIG_PPC_64K_PAGES
1119 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1121 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1123 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1124 copro_flush_all_slbs(mm);
1125 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1127 copy_mm_to_paca(mm);
1128 slb_flush_and_rebolt();
1131 #endif /* CONFIG_PPC_64K_PAGES */
1133 #ifdef CONFIG_PPC_SUBPAGE_PROT
1135 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1136 * Userspace sets the subpage permissions using the subpage_prot system call.
1138 * Result is 0: full permissions, _PAGE_RW: read-only,
1139 * _PAGE_RWX: no access.
1141 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1143 struct subpage_prot_table *spt = &mm->context.spt;
1147 if (ea >= spt->maxaddr)
1149 if (ea < 0x100000000UL) {
1150 /* addresses below 4GB use spt->low_prot */
1151 sbpm = spt->low_prot;
1153 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1157 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1160 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1162 /* extract 2-bit bitfield for this 4k subpage */
1163 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1166 * 0 -> full premission
1169 * We return the flag that need to be cleared.
1171 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1175 #else /* CONFIG_PPC_SUBPAGE_PROT */
1176 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1182 void hash_failure_debug(unsigned long ea, unsigned long access,
1183 unsigned long vsid, unsigned long trap,
1184 int ssize, int psize, int lpsize, unsigned long pte)
1186 if (!printk_ratelimit())
1188 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1189 ea, access, current->comm);
1190 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1191 trap, vsid, ssize, psize, lpsize, pte);
1194 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1195 int psize, bool user_region)
1198 if (psize != get_paca_psize(ea)) {
1199 copy_mm_to_paca(mm);
1200 slb_flush_and_rebolt();
1202 } else if (get_paca()->vmalloc_sllp !=
1203 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1204 get_paca()->vmalloc_sllp =
1205 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1206 slb_vmalloc_update();
1212 * 1 - normal page fault
1213 * -1 - critical hash insertion error
1214 * -2 - access not permitted by subpage protection mechanism
1216 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1217 unsigned long access, unsigned long trap,
1218 unsigned long flags)
1221 enum ctx_state prev_state = exception_enter();
1226 int rc, user_region = 0;
1229 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1231 trace_hash_fault(ea, access, trap);
1233 /* Get region & vsid */
1234 switch (REGION_ID(ea)) {
1235 case USER_REGION_ID:
1238 DBG_LOW(" user region with no mm !\n");
1242 psize = get_slice_psize(mm, ea);
1243 ssize = user_segment_size(ea);
1244 vsid = get_user_vsid(&mm->context, ea, ssize);
1246 case VMALLOC_REGION_ID:
1247 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1248 if (ea < VMALLOC_END)
1249 psize = mmu_vmalloc_psize;
1251 psize = mmu_io_psize;
1252 ssize = mmu_kernel_ssize;
1255 /* Not a valid range
1256 * Send the problem up to do_page_fault
1261 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1265 DBG_LOW("Bad address!\n");
1271 if (pgdir == NULL) {
1276 /* Check CPU locality */
1277 if (user_region && mm_is_thread_local(mm))
1278 flags |= HPTE_LOCAL_UPDATE;
1280 #ifndef CONFIG_PPC_64K_PAGES
1281 /* If we use 4K pages and our psize is not 4K, then we might
1282 * be hitting a special driver mapping, and need to align the
1283 * address before we fetch the PTE.
1285 * It could also be a hugepage mapping, in which case this is
1286 * not necessary, but it's not harmful, either.
1288 if (psize != MMU_PAGE_4K)
1289 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1290 #endif /* CONFIG_PPC_64K_PAGES */
1292 /* Get PTE and page size from page tables */
1293 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1294 if (ptep == NULL || !pte_present(*ptep)) {
1295 DBG_LOW(" no PTE !\n");
1300 /* Add _PAGE_PRESENT to the required access perm */
1301 access |= _PAGE_PRESENT;
1303 /* Pre-check access permissions (will be re-checked atomically
1304 * in __hash_page_XX but this pre-check is a fast path
1306 if (!check_pte_access(access, pte_val(*ptep))) {
1307 DBG_LOW(" no access !\n");
1314 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1315 trap, flags, ssize, psize);
1316 #ifdef CONFIG_HUGETLB_PAGE
1318 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1319 flags, ssize, hugeshift, psize);
1323 * if we have hugeshift, and is not transhuge with
1324 * hugetlb disabled, something is really wrong.
1330 if (current->mm == mm)
1331 check_paca_psize(ea, mm, psize, user_region);
1336 #ifndef CONFIG_PPC_64K_PAGES
1337 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1339 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1340 pte_val(*(ptep + PTRS_PER_PTE)));
1342 /* Do actual hashing */
1343 #ifdef CONFIG_PPC_64K_PAGES
1344 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1345 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1346 demote_segment_4k(mm, ea);
1347 psize = MMU_PAGE_4K;
1350 /* If this PTE is non-cacheable and we have restrictions on
1351 * using non cacheable large pages, then we switch to 4k
1353 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1355 demote_segment_4k(mm, ea);
1356 psize = MMU_PAGE_4K;
1357 } else if (ea < VMALLOC_END) {
1359 * some driver did a non-cacheable mapping
1360 * in vmalloc space, so switch vmalloc
1363 printk(KERN_ALERT "Reducing vmalloc segment "
1364 "to 4kB pages because of "
1365 "non-cacheable mapping\n");
1366 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1367 copro_flush_all_slbs(mm);
1371 #endif /* CONFIG_PPC_64K_PAGES */
1373 if (current->mm == mm)
1374 check_paca_psize(ea, mm, psize, user_region);
1376 #ifdef CONFIG_PPC_64K_PAGES
1377 if (psize == MMU_PAGE_64K)
1378 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1381 #endif /* CONFIG_PPC_64K_PAGES */
1383 int spp = subpage_protection(mm, ea);
1387 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1391 /* Dump some info in case of hash insertion failure, they should
1392 * never happen so it is really useful to know if/when they do
1395 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1396 psize, pte_val(*ptep));
1397 #ifndef CONFIG_PPC_64K_PAGES
1398 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1400 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1401 pte_val(*(ptep + PTRS_PER_PTE)));
1403 DBG_LOW(" -> rc=%d\n", rc);
1406 exception_exit(prev_state);
1409 EXPORT_SYMBOL_GPL(hash_page_mm);
1411 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1412 unsigned long dsisr)
1414 unsigned long flags = 0;
1415 struct mm_struct *mm = current->mm;
1417 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1420 if (dsisr & DSISR_NOHPTE)
1421 flags |= HPTE_NOHPTE_UPDATE;
1423 return hash_page_mm(mm, ea, access, trap, flags);
1425 EXPORT_SYMBOL_GPL(hash_page);
1427 int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap,
1428 unsigned long dsisr)
1430 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1431 unsigned long flags = 0;
1432 struct mm_struct *mm = current->mm;
1434 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1437 if (dsisr & DSISR_NOHPTE)
1438 flags |= HPTE_NOHPTE_UPDATE;
1440 if (dsisr & DSISR_ISSTORE)
1441 access |= _PAGE_WRITE;
1443 * We set _PAGE_PRIVILEGED only when
1444 * kernel mode access kernel space.
1446 * _PAGE_PRIVILEGED is NOT set
1447 * 1) when kernel mode access user space
1448 * 2) user space access kernel space.
1450 access |= _PAGE_PRIVILEGED;
1451 if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID))
1452 access &= ~_PAGE_PRIVILEGED;
1455 access |= _PAGE_EXEC;
1457 return hash_page_mm(mm, ea, access, trap, flags);
1460 #ifdef CONFIG_PPC_MM_SLICES
1461 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1463 int psize = get_slice_psize(mm, ea);
1465 /* We only prefault standard pages for now */
1466 if (unlikely(psize != mm->context.user_psize))
1470 * Don't prefault if subpage protection is enabled for the EA.
1472 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1478 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1484 void hash_preload(struct mm_struct *mm, unsigned long ea,
1485 bool is_exec, unsigned long trap)
1491 unsigned long flags;
1492 int rc, ssize, update_flags = 0;
1493 unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0);
1495 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1497 if (!should_hash_preload(mm, ea))
1500 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1501 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1503 /* Get Linux PTE if available */
1509 ssize = user_segment_size(ea);
1510 vsid = get_user_vsid(&mm->context, ea, ssize);
1514 * Hash doesn't like irqs. Walking linux page table with irq disabled
1515 * saves us from holding multiple locks.
1517 local_irq_save(flags);
1520 * THP pages use update_mmu_cache_pmd. We don't do
1521 * hash preload there. Hence can ignore THP here
1523 ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift);
1527 WARN_ON(hugepage_shift);
1528 #ifdef CONFIG_PPC_64K_PAGES
1529 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1530 * a 64K kernel), then we don't preload, hash_page() will take
1531 * care of it once we actually try to access the page.
1532 * That way we don't have to duplicate all of the logic for segment
1533 * page size demotion here
1535 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1537 #endif /* CONFIG_PPC_64K_PAGES */
1539 /* Is that local to this CPU ? */
1540 if (mm_is_thread_local(mm))
1541 update_flags |= HPTE_LOCAL_UPDATE;
1544 #ifdef CONFIG_PPC_64K_PAGES
1545 if (mm->context.user_psize == MMU_PAGE_64K)
1546 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1547 update_flags, ssize);
1549 #endif /* CONFIG_PPC_64K_PAGES */
1550 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1551 ssize, subpage_protection(mm, ea));
1553 /* Dump some info in case of hash insertion failure, they should
1554 * never happen so it is really useful to know if/when they do
1557 hash_failure_debug(ea, access, vsid, trap, ssize,
1558 mm->context.user_psize,
1559 mm->context.user_psize,
1562 local_irq_restore(flags);
1565 #ifdef CONFIG_PPC_MEM_KEYS
1567 * Return the protection key associated with the given address and the
1570 u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address)
1574 unsigned long flags;
1576 if (!mm || !mm->pgd)
1579 local_irq_save(flags);
1580 ptep = find_linux_pte(mm->pgd, address, NULL, NULL);
1582 pkey = pte_to_pkey_bits(pte_val(READ_ONCE(*ptep)));
1583 local_irq_restore(flags);
1587 #endif /* CONFIG_PPC_MEM_KEYS */
1589 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1590 static inline void tm_flush_hash_page(int local)
1593 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1594 * page back to a block device w/PIO could pick up transactional data
1595 * (bad!) so we force an abort here. Before the sync the page will be
1596 * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1597 * kernel uses a page from userspace without unmapping it first, it may
1598 * see the speculated version.
1600 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1601 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1603 tm_abort(TM_CAUSE_TLBI);
1607 static inline void tm_flush_hash_page(int local)
1613 * Return the global hash slot, corresponding to the given PTE, which contains
1616 unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
1617 int ssize, real_pte_t rpte, unsigned int subpg_index)
1619 unsigned long hash, gslot, hidx;
1621 hash = hpt_hash(vpn, shift, ssize);
1622 hidx = __rpte_to_hidx(rpte, subpg_index);
1623 if (hidx & _PTEIDX_SECONDARY)
1625 gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1626 gslot += hidx & _PTEIDX_GROUP_IX;
1630 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1631 * do not forget to update the assembly call site !
1633 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1634 unsigned long flags)
1636 unsigned long index, shift, gslot;
1637 int local = flags & HPTE_LOCAL_UPDATE;
1639 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1640 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1641 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index);
1642 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot);
1644 * We use same base page size and actual psize, because we don't
1645 * use these functions for hugepage
1647 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize,
1649 } pte_iterate_hashed_end();
1651 tm_flush_hash_page(local);
1654 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1655 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1656 pmd_t *pmdp, unsigned int psize, int ssize,
1657 unsigned long flags)
1659 int i, max_hpte_count, valid;
1660 unsigned long s_addr;
1661 unsigned char *hpte_slot_array;
1662 unsigned long hidx, shift, vpn, hash, slot;
1663 int local = flags & HPTE_LOCAL_UPDATE;
1665 s_addr = addr & HPAGE_PMD_MASK;
1666 hpte_slot_array = get_hpte_slot_array(pmdp);
1668 * IF we try to do a HUGE PTE update after a withdraw is done.
1669 * we will find the below NULL. This happens when we do
1670 * split_huge_page_pmd
1672 if (!hpte_slot_array)
1675 if (mmu_hash_ops.hugepage_invalidate) {
1676 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1677 psize, ssize, local);
1681 * No bluk hpte removal support, invalidate each entry
1683 shift = mmu_psize_defs[psize].shift;
1684 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1685 for (i = 0; i < max_hpte_count; i++) {
1687 * 8 bits per each hpte entries
1688 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1690 valid = hpte_valid(hpte_slot_array, i);
1693 hidx = hpte_hash_index(hpte_slot_array, i);
1696 addr = s_addr + (i * (1ul << shift));
1697 vpn = hpt_vpn(addr, vsid, ssize);
1698 hash = hpt_hash(vpn, shift, ssize);
1699 if (hidx & _PTEIDX_SECONDARY)
1702 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1703 slot += hidx & _PTEIDX_GROUP_IX;
1704 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1705 MMU_PAGE_16M, ssize, local);
1708 tm_flush_hash_page(local);
1710 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1712 void flush_hash_range(unsigned long number, int local)
1714 if (mmu_hash_ops.flush_hash_range)
1715 mmu_hash_ops.flush_hash_range(number, local);
1718 struct ppc64_tlb_batch *batch =
1719 this_cpu_ptr(&ppc64_tlb_batch);
1721 for (i = 0; i < number; i++)
1722 flush_hash_page(batch->vpn[i], batch->pte[i],
1723 batch->psize, batch->ssize, local);
1728 * low_hash_fault is called when we the low level hash code failed
1729 * to instert a PTE due to an hypervisor error
1731 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1733 enum ctx_state prev_state = exception_enter();
1735 if (user_mode(regs)) {
1736 #ifdef CONFIG_PPC_SUBPAGE_PROT
1738 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1741 _exception(SIGBUS, regs, BUS_ADRERR, address);
1743 bad_page_fault(regs, address, SIGBUS);
1745 exception_exit(prev_state);
1748 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1749 unsigned long pa, unsigned long rflags,
1750 unsigned long vflags, int psize, int ssize)
1752 unsigned long hpte_group;
1756 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1758 /* Insert into the hash table, primary slot */
1759 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1760 psize, psize, ssize);
1762 /* Primary is full, try the secondary */
1763 if (unlikely(slot == -1)) {
1764 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;
1765 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1766 vflags | HPTE_V_SECONDARY,
1767 psize, psize, ssize);
1770 hpte_group = (hash & htab_hash_mask) *
1773 mmu_hash_ops.hpte_remove(hpte_group);
1781 #ifdef CONFIG_DEBUG_PAGEALLOC
1782 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1785 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1786 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1787 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1790 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1792 /* Don't create HPTE entries for bad address */
1796 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1798 mmu_linear_psize, mmu_kernel_ssize);
1801 spin_lock(&linear_map_hash_lock);
1802 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1803 linear_map_hash_slots[lmi] = ret | 0x80;
1804 spin_unlock(&linear_map_hash_lock);
1807 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1809 unsigned long hash, hidx, slot;
1810 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1811 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1813 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1814 spin_lock(&linear_map_hash_lock);
1815 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1816 hidx = linear_map_hash_slots[lmi] & 0x7f;
1817 linear_map_hash_slots[lmi] = 0;
1818 spin_unlock(&linear_map_hash_lock);
1819 if (hidx & _PTEIDX_SECONDARY)
1821 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1822 slot += hidx & _PTEIDX_GROUP_IX;
1823 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1825 mmu_kernel_ssize, 0);
1828 void __kernel_map_pages(struct page *page, int numpages, int enable)
1830 unsigned long flags, vaddr, lmi;
1833 local_irq_save(flags);
1834 for (i = 0; i < numpages; i++, page++) {
1835 vaddr = (unsigned long)page_address(page);
1836 lmi = __pa(vaddr) >> PAGE_SHIFT;
1837 if (lmi >= linear_map_hash_count)
1840 kernel_map_linear_page(vaddr, lmi);
1842 kernel_unmap_linear_page(vaddr, lmi);
1844 local_irq_restore(flags);
1846 #endif /* CONFIG_DEBUG_PAGEALLOC */
1848 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1849 phys_addr_t first_memblock_size)
1851 /* We don't currently support the first MEMBLOCK not mapping 0
1852 * physical on those processors
1854 BUG_ON(first_memblock_base != 0);
1857 * On virtualized systems the first entry is our RMA region aka VRMA,
1858 * non-virtualized 64-bit hash MMU systems don't have a limitation
1859 * on real mode access.
1861 * For guests on platforms before POWER9, we clamp the it limit to 1G
1862 * to avoid some funky things such as RTAS bugs etc...
1864 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) {
1865 ppc64_rma_size = first_memblock_size;
1866 if (!early_cpu_has_feature(CPU_FTR_ARCH_300))
1867 ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000);
1869 /* Finally limit subsequent allocations */
1870 memblock_set_current_limit(ppc64_rma_size);
1872 ppc64_rma_size = ULONG_MAX;
1876 #ifdef CONFIG_DEBUG_FS
1878 static int hpt_order_get(void *data, u64 *val)
1880 *val = ppc64_pft_size;
1884 static int hpt_order_set(void *data, u64 val)
1886 if (!mmu_hash_ops.resize_hpt)
1889 return mmu_hash_ops.resize_hpt(val);
1892 DEFINE_SIMPLE_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
1894 static int __init hash64_debugfs(void)
1896 if (!debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root,
1897 NULL, &fops_hpt_order)) {
1898 pr_err("lpar: unable to create hpt_order debugsfs file\n");
1903 machine_device_initcall(pseries, hash64_debugfs);
1904 #endif /* CONFIG_DEBUG_FS */