2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/export.h>
31 #include <linux/ctype.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/signal.h>
35 #include <linux/memblock.h>
36 #include <linux/context_tracking.h>
38 #include <asm/processor.h>
39 #include <asm/pgtable.h>
41 #include <asm/mmu_context.h>
43 #include <asm/types.h>
44 #include <asm/uaccess.h>
45 #include <asm/machdep.h>
47 #include <asm/tlbflush.h>
51 #include <asm/cacheflush.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
54 #include <asm/copro.h>
56 #include <asm/code-patching.h>
57 #include <asm/fadump.h>
58 #include <asm/firmware.h>
60 #include <asm/trace.h>
63 #define DBG(fmt...) udbg_printf(fmt)
69 #define DBG_LOW(fmt...) udbg_printf(fmt)
71 #define DBG_LOW(fmt...)
79 * Note: pte --> Linux PTE
80 * HPTE --> PowerPC Hashed Page Table Entry
83 * htab_initialize is called with the MMU off (of course), but
84 * the kernel has been copied down to zero so it can directly
85 * reference global data. At this point it is very difficult
86 * to print debug info.
91 extern unsigned long dart_tablebase;
92 #endif /* CONFIG_U3_DART */
94 static unsigned long _SDR1;
95 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
96 EXPORT_SYMBOL_GPL(mmu_psize_defs);
98 struct hash_pte *htab_address;
99 unsigned long htab_size_bytes;
100 unsigned long htab_hash_mask;
101 EXPORT_SYMBOL_GPL(htab_hash_mask);
102 int mmu_linear_psize = MMU_PAGE_4K;
103 EXPORT_SYMBOL_GPL(mmu_linear_psize);
104 int mmu_virtual_psize = MMU_PAGE_4K;
105 int mmu_vmalloc_psize = MMU_PAGE_4K;
106 #ifdef CONFIG_SPARSEMEM_VMEMMAP
107 int mmu_vmemmap_psize = MMU_PAGE_4K;
109 int mmu_io_psize = MMU_PAGE_4K;
110 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
111 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
112 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
113 u16 mmu_slb_size = 64;
114 EXPORT_SYMBOL_GPL(mmu_slb_size);
115 #ifdef CONFIG_PPC_64K_PAGES
116 int mmu_ci_restrictions;
118 #ifdef CONFIG_DEBUG_PAGEALLOC
119 static u8 *linear_map_hash_slots;
120 static unsigned long linear_map_hash_count;
121 static DEFINE_SPINLOCK(linear_map_hash_lock);
122 #endif /* CONFIG_DEBUG_PAGEALLOC */
124 /* There are definitions of page sizes arrays to be used when none
125 * is provided by the firmware.
128 /* Pre-POWER4 CPUs (4k pages only)
130 static struct mmu_psize_def mmu_psize_defaults_old[] = {
134 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
140 /* POWER4, GPUL, POWER5
142 * Support for 16Mb large pages
144 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
148 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
155 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
156 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
162 unsigned long htab_convert_pte_flags(unsigned long pteflags)
164 unsigned long rflags = 0;
166 /* _PAGE_EXEC -> NOEXEC */
167 if ((pteflags & _PAGE_EXEC) == 0)
171 * Linux uses slb key 0 for kernel and 1 for user.
172 * kernel RW areas are mapped with PPP=0b000
173 * User area is mapped with PPP=0b010 for read/write
174 * or PPP=0b011 for read-only (including writeable but clean pages).
176 if (pteflags & _PAGE_PRIVILEGED) {
178 * Kernel read only mapped with ppp bits 0b110
180 if (!(pteflags & _PAGE_WRITE))
181 rflags |= (HPTE_R_PP0 | 0x2);
183 if (pteflags & _PAGE_RWX)
185 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
189 * Always add "C" bit for perf. Memory coherence is always enabled
191 rflags |= HPTE_R_C | HPTE_R_M;
196 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
198 if ((pteflags & _PAGE_CACHE_CTL ) == _PAGE_NON_IDEMPOTENT)
199 rflags |= (HPTE_R_I | HPTE_R_G);
200 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
201 rflags |= (HPTE_R_I | HPTE_R_W);
206 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
207 unsigned long pstart, unsigned long prot,
208 int psize, int ssize)
210 unsigned long vaddr, paddr;
211 unsigned int step, shift;
214 shift = mmu_psize_defs[psize].shift;
217 prot = htab_convert_pte_flags(prot);
219 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
220 vstart, vend, pstart, prot, psize, ssize);
222 for (vaddr = vstart, paddr = pstart; vaddr < vend;
223 vaddr += step, paddr += step) {
224 unsigned long hash, hpteg;
225 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
226 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
227 unsigned long tprot = prot;
230 * If we hit a bad address return error.
234 /* Make kernel text executable */
235 if (overlaps_kernel_text(vaddr, vaddr + step))
238 /* Make kvm guest trampolines executable */
239 if (overlaps_kvm_tmp(vaddr, vaddr + step))
243 * If relocatable, check if it overlaps interrupt vectors that
244 * are copied down to real 0. For relocatable kernel
245 * (e.g. kdump case) we copy interrupt vectors down to real
246 * address 0. Mark that region as executable. This is
247 * because on p8 system with relocation on exception feature
248 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
249 * in order to execute the interrupt handlers in virtual
250 * mode the vector region need to be marked as executable.
252 if ((PHYSICAL_START > MEMORY_START) &&
253 overlaps_interrupt_vector_text(vaddr, vaddr + step))
256 hash = hpt_hash(vpn, shift, ssize);
257 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
259 BUG_ON(!ppc_md.hpte_insert);
260 ret = ppc_md.hpte_insert(hpteg, vpn, paddr, tprot,
261 HPTE_V_BOLTED, psize, psize, ssize);
266 #ifdef CONFIG_DEBUG_PAGEALLOC
267 if (debug_pagealloc_enabled() &&
268 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
269 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
270 #endif /* CONFIG_DEBUG_PAGEALLOC */
272 return ret < 0 ? ret : 0;
275 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
276 int psize, int ssize)
279 unsigned int step, shift;
283 shift = mmu_psize_defs[psize].shift;
286 if (!ppc_md.hpte_removebolted)
289 for (vaddr = vstart; vaddr < vend; vaddr += step) {
290 rc = ppc_md.hpte_removebolted(vaddr, psize, ssize);
302 static int __init htab_dt_scan_seg_sizes(unsigned long node,
303 const char *uname, int depth,
306 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
310 /* We are scanning "cpu" nodes only */
311 if (type == NULL || strcmp(type, "cpu") != 0)
314 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
317 for (; size >= 4; size -= 4, ++prop) {
318 if (be32_to_cpu(prop[0]) == 40) {
319 DBG("1T segment support detected\n");
320 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
324 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
328 static void __init htab_init_seg_sizes(void)
330 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
333 static int __init get_idx_from_shift(unsigned int shift)
357 static int __init htab_dt_scan_page_sizes(unsigned long node,
358 const char *uname, int depth,
361 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
365 /* We are scanning "cpu" nodes only */
366 if (type == NULL || strcmp(type, "cpu") != 0)
369 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
373 pr_info("Page sizes from device-tree:\n");
375 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
377 unsigned int base_shift = be32_to_cpu(prop[0]);
378 unsigned int slbenc = be32_to_cpu(prop[1]);
379 unsigned int lpnum = be32_to_cpu(prop[2]);
380 struct mmu_psize_def *def;
383 size -= 3; prop += 3;
384 base_idx = get_idx_from_shift(base_shift);
386 /* skip the pte encoding also */
387 prop += lpnum * 2; size -= lpnum * 2;
390 def = &mmu_psize_defs[base_idx];
391 if (base_idx == MMU_PAGE_16M)
392 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
394 def->shift = base_shift;
395 if (base_shift <= 23)
398 def->avpnm = (1 << (base_shift - 23)) - 1;
401 * We don't know for sure what's up with tlbiel, so
402 * for now we only set it for 4K and 64K pages
404 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
409 while (size > 0 && lpnum) {
410 unsigned int shift = be32_to_cpu(prop[0]);
411 int penc = be32_to_cpu(prop[1]);
413 prop += 2; size -= 2;
416 idx = get_idx_from_shift(shift);
421 pr_err("Invalid penc for base_shift=%d "
422 "shift=%d\n", base_shift, shift);
424 def->penc[idx] = penc;
425 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
426 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
427 base_shift, shift, def->sllp,
428 def->avpnm, def->tlbiel, def->penc[idx]);
435 #ifdef CONFIG_HUGETLB_PAGE
436 /* Scan for 16G memory blocks that have been set aside for huge pages
437 * and reserve those blocks for 16G huge pages.
439 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
440 const char *uname, int depth,
442 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
443 const __be64 *addr_prop;
444 const __be32 *page_count_prop;
445 unsigned int expected_pages;
446 long unsigned int phys_addr;
447 long unsigned int block_size;
449 /* We are scanning "memory" nodes only */
450 if (type == NULL || strcmp(type, "memory") != 0)
453 /* This property is the log base 2 of the number of virtual pages that
454 * will represent this memory block. */
455 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
456 if (page_count_prop == NULL)
458 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
459 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
460 if (addr_prop == NULL)
462 phys_addr = be64_to_cpu(addr_prop[0]);
463 block_size = be64_to_cpu(addr_prop[1]);
464 if (block_size != (16 * GB))
466 printk(KERN_INFO "Huge page(16GB) memory: "
467 "addr = 0x%lX size = 0x%lX pages = %d\n",
468 phys_addr, block_size, expected_pages);
469 if (phys_addr + (16 * GB) <= memblock_end_of_DRAM()) {
470 memblock_reserve(phys_addr, block_size * expected_pages);
471 add_gpage(phys_addr, block_size, expected_pages);
475 #endif /* CONFIG_HUGETLB_PAGE */
477 static void mmu_psize_set_default_penc(void)
480 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
481 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
482 mmu_psize_defs[bpsize].penc[apsize] = -1;
485 #ifdef CONFIG_PPC_64K_PAGES
487 static bool might_have_hea(void)
490 * The HEA ethernet adapter requires awareness of the
491 * GX bus. Without that awareness we can easily assume
492 * we will never see an HEA ethernet device.
494 #ifdef CONFIG_IBMEBUS
495 return !cpu_has_feature(CPU_FTR_ARCH_207S);
501 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
503 static void __init htab_init_page_sizes(void)
507 /* se the invalid penc to -1 */
508 mmu_psize_set_default_penc();
510 /* Default to 4K pages only */
511 memcpy(mmu_psize_defs, mmu_psize_defaults_old,
512 sizeof(mmu_psize_defaults_old));
515 * Try to find the available page sizes in the device-tree
517 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
518 if (rc != 0) /* Found */
522 * Not in the device-tree, let's fallback on known size
523 * list for 16M capable GP & GR
525 if (mmu_has_feature(MMU_FTR_16M_PAGE))
526 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
527 sizeof(mmu_psize_defaults_gp));
529 if (!debug_pagealloc_enabled()) {
531 * Pick a size for the linear mapping. Currently, we only
532 * support 16M, 1M and 4K which is the default
534 if (mmu_psize_defs[MMU_PAGE_16M].shift)
535 mmu_linear_psize = MMU_PAGE_16M;
536 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
537 mmu_linear_psize = MMU_PAGE_1M;
540 #ifdef CONFIG_PPC_64K_PAGES
542 * Pick a size for the ordinary pages. Default is 4K, we support
543 * 64K for user mappings and vmalloc if supported by the processor.
544 * We only use 64k for ioremap if the processor
545 * (and firmware) support cache-inhibited large pages.
546 * If not, we use 4k and set mmu_ci_restrictions so that
547 * hash_page knows to switch processes that use cache-inhibited
548 * mappings to 4k pages.
550 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
551 mmu_virtual_psize = MMU_PAGE_64K;
552 mmu_vmalloc_psize = MMU_PAGE_64K;
553 if (mmu_linear_psize == MMU_PAGE_4K)
554 mmu_linear_psize = MMU_PAGE_64K;
555 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
557 * When running on pSeries using 64k pages for ioremap
558 * would stop us accessing the HEA ethernet. So if we
559 * have the chance of ever seeing one, stay at 4k.
561 if (!might_have_hea() || !machine_is(pseries))
562 mmu_io_psize = MMU_PAGE_64K;
564 mmu_ci_restrictions = 1;
566 #endif /* CONFIG_PPC_64K_PAGES */
568 #ifdef CONFIG_SPARSEMEM_VMEMMAP
569 /* We try to use 16M pages for vmemmap if that is supported
570 * and we have at least 1G of RAM at boot
572 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
573 memblock_phys_mem_size() >= 0x40000000)
574 mmu_vmemmap_psize = MMU_PAGE_16M;
575 else if (mmu_psize_defs[MMU_PAGE_64K].shift)
576 mmu_vmemmap_psize = MMU_PAGE_64K;
578 mmu_vmemmap_psize = MMU_PAGE_4K;
579 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
581 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
582 "virtual = %d, io = %d"
583 #ifdef CONFIG_SPARSEMEM_VMEMMAP
587 mmu_psize_defs[mmu_linear_psize].shift,
588 mmu_psize_defs[mmu_virtual_psize].shift,
589 mmu_psize_defs[mmu_io_psize].shift
590 #ifdef CONFIG_SPARSEMEM_VMEMMAP
591 ,mmu_psize_defs[mmu_vmemmap_psize].shift
595 #ifdef CONFIG_HUGETLB_PAGE
596 /* Reserve 16G huge page memory sections for huge pages */
597 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
598 #endif /* CONFIG_HUGETLB_PAGE */
601 static int __init htab_dt_scan_pftsize(unsigned long node,
602 const char *uname, int depth,
605 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
608 /* We are scanning "cpu" nodes only */
609 if (type == NULL || strcmp(type, "cpu") != 0)
612 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
614 /* pft_size[0] is the NUMA CEC cookie */
615 ppc64_pft_size = be32_to_cpu(prop[1]);
621 unsigned htab_shift_for_mem_size(unsigned long mem_size)
623 unsigned memshift = __ilog2(mem_size);
624 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
627 /* round mem_size up to next power of 2 */
628 if ((1UL << memshift) < mem_size)
631 /* aim for 2 pages / pteg */
632 pteg_shift = memshift - (pshift + 1);
635 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
636 * size permitted by the architecture.
638 return max(pteg_shift + 7, 18U);
641 static unsigned long __init htab_get_table_size(void)
643 /* If hash size isn't already provided by the platform, we try to
644 * retrieve it from the device-tree. If it's not there neither, we
645 * calculate it now based on the total RAM size
647 if (ppc64_pft_size == 0)
648 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
650 return 1UL << ppc64_pft_size;
652 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
655 #ifdef CONFIG_MEMORY_HOTPLUG
656 int create_section_mapping(unsigned long start, unsigned long end)
658 int rc = htab_bolt_mapping(start, end, __pa(start),
659 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
663 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
665 BUG_ON(rc2 && (rc2 != -ENOENT));
670 int remove_section_mapping(unsigned long start, unsigned long end)
672 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
677 #endif /* CONFIG_MEMORY_HOTPLUG */
679 static void __init hash_init_partition_table(phys_addr_t hash_table,
680 unsigned long pteg_count)
682 unsigned long ps_field;
683 unsigned long htab_size;
684 unsigned long patb_size = 1UL << PATB_SIZE_SHIFT;
687 * slb llp encoding for the page size used in VPM real mode.
688 * We can ignore that for lpid 0
691 htab_size = __ilog2(pteg_count) - 11;
693 BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 24), "Partition table size too large.");
694 partition_tb = __va(memblock_alloc_base(patb_size, patb_size,
695 MEMBLOCK_ALLOC_ANYWHERE));
697 /* Initialize the Partition Table with no entries */
698 memset((void *)partition_tb, 0, patb_size);
699 partition_tb->patb0 = cpu_to_be64(ps_field | hash_table | htab_size);
701 * FIXME!! This should be done via update_partition table
702 * For now UPRT is 0 for us.
704 partition_tb->patb1 = 0;
705 DBG("Partition table %p\n", partition_tb);
707 * update partition table control register,
710 mtspr(SPRN_PTCR, __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
714 static void __init htab_initialize(void)
717 unsigned long pteg_count;
719 unsigned long base = 0, size = 0, limit;
720 struct memblock_region *reg;
722 DBG(" -> htab_initialize()\n");
724 /* Initialize segment sizes */
725 htab_init_seg_sizes();
727 /* Initialize page sizes */
728 htab_init_page_sizes();
730 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
731 mmu_kernel_ssize = MMU_SEGSIZE_1T;
732 mmu_highuser_ssize = MMU_SEGSIZE_1T;
733 printk(KERN_INFO "Using 1TB segments\n");
737 * Calculate the required size of the htab. We want the number of
738 * PTEGs to equal one half the number of real pages.
740 htab_size_bytes = htab_get_table_size();
741 pteg_count = htab_size_bytes >> 7;
743 htab_hash_mask = pteg_count - 1;
745 if (firmware_has_feature(FW_FEATURE_LPAR)) {
746 /* Using a hypervisor which owns the htab */
749 #ifdef CONFIG_FA_DUMP
751 * If firmware assisted dump is active firmware preserves
752 * the contents of htab along with entire partition memory.
753 * Clear the htab if firmware assisted dump is active so
754 * that we dont end up using old mappings.
756 if (is_fadump_active() && ppc_md.hpte_clear_all)
757 ppc_md.hpte_clear_all();
760 /* Find storage for the HPT. Must be contiguous in
761 * the absolute address space. On cell we want it to be
762 * in the first 2 Gig so we can use it for IOMMU hacks.
764 if (machine_is(cell))
767 limit = MEMBLOCK_ALLOC_ANYWHERE;
769 table = memblock_alloc_base(htab_size_bytes, htab_size_bytes, limit);
771 DBG("Hash table allocated at %lx, size: %lx\n", table,
774 htab_address = __va(table);
776 /* htab absolute addr + encoded htabsize */
777 _SDR1 = table + __ilog2(pteg_count) - 11;
779 /* Initialize the HPT with no entries */
780 memset((void *)table, 0, htab_size_bytes);
782 if (!cpu_has_feature(CPU_FTR_ARCH_300))
784 mtspr(SPRN_SDR1, _SDR1);
786 hash_init_partition_table(table, pteg_count);
789 prot = pgprot_val(PAGE_KERNEL);
791 #ifdef CONFIG_DEBUG_PAGEALLOC
792 if (debug_pagealloc_enabled()) {
793 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
794 linear_map_hash_slots = __va(memblock_alloc_base(
795 linear_map_hash_count, 1, ppc64_rma_size));
796 memset(linear_map_hash_slots, 0, linear_map_hash_count);
798 #endif /* CONFIG_DEBUG_PAGEALLOC */
800 /* On U3 based machines, we need to reserve the DART area and
801 * _NOT_ map it to avoid cache paradoxes as it's remapped non
805 /* create bolted the linear mapping in the hash table */
806 for_each_memblock(memory, reg) {
807 base = (unsigned long)__va(reg->base);
810 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
813 #ifdef CONFIG_U3_DART
814 /* Do not map the DART space. Fortunately, it will be aligned
815 * in such a way that it will not cross two memblock regions and
816 * will fit within a single 16Mb page.
817 * The DART space is assumed to be a full 16Mb region even if
818 * we only use 2Mb of that space. We will use more of it later
819 * for AGP GART. We have to use a full 16Mb large page.
821 DBG("DART base: %lx\n", dart_tablebase);
823 if (dart_tablebase != 0 && dart_tablebase >= base
824 && dart_tablebase < (base + size)) {
825 unsigned long dart_table_end = dart_tablebase + 16 * MB;
826 if (base != dart_tablebase)
827 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
831 if ((base + size) > dart_table_end)
832 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
834 __pa(dart_table_end),
840 #endif /* CONFIG_U3_DART */
841 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
842 prot, mmu_linear_psize, mmu_kernel_ssize));
844 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
847 * If we have a memory_limit and we've allocated TCEs then we need to
848 * explicitly map the TCE area at the top of RAM. We also cope with the
849 * case that the TCEs start below memory_limit.
850 * tce_alloc_start/end are 16MB aligned so the mapping should work
851 * for either 4K or 16MB pages.
853 if (tce_alloc_start) {
854 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
855 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
857 if (base + size >= tce_alloc_start)
858 tce_alloc_start = base + size + 1;
860 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
861 __pa(tce_alloc_start), prot,
862 mmu_linear_psize, mmu_kernel_ssize));
866 DBG(" <- htab_initialize()\n");
871 void __init hash__early_init_mmu(void)
874 * initialize page table size
876 __pte_frag_nr = H_PTE_FRAG_NR;
877 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
879 __pte_index_size = H_PTE_INDEX_SIZE;
880 __pmd_index_size = H_PMD_INDEX_SIZE;
881 __pud_index_size = H_PUD_INDEX_SIZE;
882 __pgd_index_size = H_PGD_INDEX_SIZE;
883 __pmd_cache_index = H_PMD_CACHE_INDEX;
884 __pte_table_size = H_PTE_TABLE_SIZE;
885 __pmd_table_size = H_PMD_TABLE_SIZE;
886 __pud_table_size = H_PUD_TABLE_SIZE;
887 __pgd_table_size = H_PGD_TABLE_SIZE;
889 * 4k use hugepd format, so for hash set then to
896 __kernel_virt_start = H_KERN_VIRT_START;
897 __kernel_virt_size = H_KERN_VIRT_SIZE;
898 __vmalloc_start = H_VMALLOC_START;
899 __vmalloc_end = H_VMALLOC_END;
900 vmemmap = (struct page *)H_VMEMMAP_BASE;
901 ioremap_bot = IOREMAP_BASE;
903 /* Initialize the MMU Hash table and create the linear mapping
904 * of memory. Has to be done before SLB initialization as this is
905 * currently where the page size encoding is obtained.
909 /* Initialize SLB management */
914 void hash__early_init_mmu_secondary(void)
916 /* Initialize hash table for that CPU */
917 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
918 if (!cpu_has_feature(CPU_FTR_ARCH_300))
919 mtspr(SPRN_SDR1, _SDR1);
922 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
927 #endif /* CONFIG_SMP */
930 * Called by asm hashtable.S for doing lazy icache flush
932 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
936 if (!pfn_valid(pte_pfn(pte)))
939 page = pte_page(pte);
942 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
944 flush_dcache_icache_page(page);
945 set_bit(PG_arch_1, &page->flags);
952 #ifdef CONFIG_PPC_MM_SLICES
953 static unsigned int get_paca_psize(unsigned long addr)
956 unsigned char *hpsizes;
957 unsigned long index, mask_index;
959 if (addr < SLICE_LOW_TOP) {
960 lpsizes = get_paca()->mm_ctx_low_slices_psize;
961 index = GET_LOW_SLICE_INDEX(addr);
962 return (lpsizes >> (index * 4)) & 0xF;
964 hpsizes = get_paca()->mm_ctx_high_slices_psize;
965 index = GET_HIGH_SLICE_INDEX(addr);
966 mask_index = index & 0x1;
967 return (hpsizes[index >> 1] >> (mask_index * 4)) & 0xF;
971 unsigned int get_paca_psize(unsigned long addr)
973 return get_paca()->mm_ctx_user_psize;
978 * Demote a segment to using 4k pages.
979 * For now this makes the whole process use 4k pages.
981 #ifdef CONFIG_PPC_64K_PAGES
982 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
984 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
986 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
987 copro_flush_all_slbs(mm);
988 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
990 copy_mm_to_paca(&mm->context);
991 slb_flush_and_rebolt();
994 #endif /* CONFIG_PPC_64K_PAGES */
996 #ifdef CONFIG_PPC_SUBPAGE_PROT
998 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
999 * Userspace sets the subpage permissions using the subpage_prot system call.
1001 * Result is 0: full permissions, _PAGE_RW: read-only,
1002 * _PAGE_RWX: no access.
1004 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1006 struct subpage_prot_table *spt = &mm->context.spt;
1010 if (ea >= spt->maxaddr)
1012 if (ea < 0x100000000UL) {
1013 /* addresses below 4GB use spt->low_prot */
1014 sbpm = spt->low_prot;
1016 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1020 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1023 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1025 /* extract 2-bit bitfield for this 4k subpage */
1026 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1029 * 0 -> full premission
1032 * We return the flag that need to be cleared.
1034 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1038 #else /* CONFIG_PPC_SUBPAGE_PROT */
1039 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1045 void hash_failure_debug(unsigned long ea, unsigned long access,
1046 unsigned long vsid, unsigned long trap,
1047 int ssize, int psize, int lpsize, unsigned long pte)
1049 if (!printk_ratelimit())
1051 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1052 ea, access, current->comm);
1053 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1054 trap, vsid, ssize, psize, lpsize, pte);
1057 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1058 int psize, bool user_region)
1061 if (psize != get_paca_psize(ea)) {
1062 copy_mm_to_paca(&mm->context);
1063 slb_flush_and_rebolt();
1065 } else if (get_paca()->vmalloc_sllp !=
1066 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1067 get_paca()->vmalloc_sllp =
1068 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1069 slb_vmalloc_update();
1075 * 1 - normal page fault
1076 * -1 - critical hash insertion error
1077 * -2 - access not permitted by subpage protection mechanism
1079 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1080 unsigned long access, unsigned long trap,
1081 unsigned long flags)
1084 enum ctx_state prev_state = exception_enter();
1089 const struct cpumask *tmp;
1090 int rc, user_region = 0;
1093 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1095 trace_hash_fault(ea, access, trap);
1097 /* Get region & vsid */
1098 switch (REGION_ID(ea)) {
1099 case USER_REGION_ID:
1102 DBG_LOW(" user region with no mm !\n");
1106 psize = get_slice_psize(mm, ea);
1107 ssize = user_segment_size(ea);
1108 vsid = get_vsid(mm->context.id, ea, ssize);
1110 case VMALLOC_REGION_ID:
1111 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1112 if (ea < VMALLOC_END)
1113 psize = mmu_vmalloc_psize;
1115 psize = mmu_io_psize;
1116 ssize = mmu_kernel_ssize;
1119 /* Not a valid range
1120 * Send the problem up to do_page_fault
1125 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1129 DBG_LOW("Bad address!\n");
1135 if (pgdir == NULL) {
1140 /* Check CPU locality */
1141 tmp = cpumask_of(smp_processor_id());
1142 if (user_region && cpumask_equal(mm_cpumask(mm), tmp))
1143 flags |= HPTE_LOCAL_UPDATE;
1145 #ifndef CONFIG_PPC_64K_PAGES
1146 /* If we use 4K pages and our psize is not 4K, then we might
1147 * be hitting a special driver mapping, and need to align the
1148 * address before we fetch the PTE.
1150 * It could also be a hugepage mapping, in which case this is
1151 * not necessary, but it's not harmful, either.
1153 if (psize != MMU_PAGE_4K)
1154 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1155 #endif /* CONFIG_PPC_64K_PAGES */
1157 /* Get PTE and page size from page tables */
1158 ptep = __find_linux_pte_or_hugepte(pgdir, ea, &is_thp, &hugeshift);
1159 if (ptep == NULL || !pte_present(*ptep)) {
1160 DBG_LOW(" no PTE !\n");
1165 /* Add _PAGE_PRESENT to the required access perm */
1166 access |= _PAGE_PRESENT;
1168 /* Pre-check access permissions (will be re-checked atomically
1169 * in __hash_page_XX but this pre-check is a fast path
1171 if (!check_pte_access(access, pte_val(*ptep))) {
1172 DBG_LOW(" no access !\n");
1179 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1180 trap, flags, ssize, psize);
1181 #ifdef CONFIG_HUGETLB_PAGE
1183 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1184 flags, ssize, hugeshift, psize);
1188 * if we have hugeshift, and is not transhuge with
1189 * hugetlb disabled, something is really wrong.
1195 if (current->mm == mm)
1196 check_paca_psize(ea, mm, psize, user_region);
1201 #ifndef CONFIG_PPC_64K_PAGES
1202 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1204 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1205 pte_val(*(ptep + PTRS_PER_PTE)));
1207 /* Do actual hashing */
1208 #ifdef CONFIG_PPC_64K_PAGES
1209 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1210 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1211 demote_segment_4k(mm, ea);
1212 psize = MMU_PAGE_4K;
1215 /* If this PTE is non-cacheable and we have restrictions on
1216 * using non cacheable large pages, then we switch to 4k
1218 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1220 demote_segment_4k(mm, ea);
1221 psize = MMU_PAGE_4K;
1222 } else if (ea < VMALLOC_END) {
1224 * some driver did a non-cacheable mapping
1225 * in vmalloc space, so switch vmalloc
1228 printk(KERN_ALERT "Reducing vmalloc segment "
1229 "to 4kB pages because of "
1230 "non-cacheable mapping\n");
1231 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1232 copro_flush_all_slbs(mm);
1236 #endif /* CONFIG_PPC_64K_PAGES */
1238 if (current->mm == mm)
1239 check_paca_psize(ea, mm, psize, user_region);
1241 #ifdef CONFIG_PPC_64K_PAGES
1242 if (psize == MMU_PAGE_64K)
1243 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1246 #endif /* CONFIG_PPC_64K_PAGES */
1248 int spp = subpage_protection(mm, ea);
1252 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1256 /* Dump some info in case of hash insertion failure, they should
1257 * never happen so it is really useful to know if/when they do
1260 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1261 psize, pte_val(*ptep));
1262 #ifndef CONFIG_PPC_64K_PAGES
1263 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1265 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1266 pte_val(*(ptep + PTRS_PER_PTE)));
1268 DBG_LOW(" -> rc=%d\n", rc);
1271 exception_exit(prev_state);
1274 EXPORT_SYMBOL_GPL(hash_page_mm);
1276 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1277 unsigned long dsisr)
1279 unsigned long flags = 0;
1280 struct mm_struct *mm = current->mm;
1282 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1285 if (dsisr & DSISR_NOHPTE)
1286 flags |= HPTE_NOHPTE_UPDATE;
1288 return hash_page_mm(mm, ea, access, trap, flags);
1290 EXPORT_SYMBOL_GPL(hash_page);
1292 int __hash_page(unsigned long ea, unsigned long msr, unsigned long trap,
1293 unsigned long dsisr)
1295 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1296 unsigned long flags = 0;
1297 struct mm_struct *mm = current->mm;
1299 if (REGION_ID(ea) == VMALLOC_REGION_ID)
1302 if (dsisr & DSISR_NOHPTE)
1303 flags |= HPTE_NOHPTE_UPDATE;
1305 if (dsisr & DSISR_ISSTORE)
1306 access |= _PAGE_WRITE;
1308 * We set _PAGE_PRIVILEGED only when
1309 * kernel mode access kernel space.
1311 * _PAGE_PRIVILEGED is NOT set
1312 * 1) when kernel mode access user space
1313 * 2) user space access kernel space.
1315 access |= _PAGE_PRIVILEGED;
1316 if ((msr & MSR_PR) || (REGION_ID(ea) == USER_REGION_ID))
1317 access &= ~_PAGE_PRIVILEGED;
1320 access |= _PAGE_EXEC;
1322 return hash_page_mm(mm, ea, access, trap, flags);
1325 #ifdef CONFIG_PPC_MM_SLICES
1326 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1328 int psize = get_slice_psize(mm, ea);
1330 /* We only prefault standard pages for now */
1331 if (unlikely(psize != mm->context.user_psize))
1335 * Don't prefault if subpage protection is enabled for the EA.
1337 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1343 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1349 void hash_preload(struct mm_struct *mm, unsigned long ea,
1350 unsigned long access, unsigned long trap)
1356 unsigned long flags;
1357 int rc, ssize, update_flags = 0;
1359 BUG_ON(REGION_ID(ea) != USER_REGION_ID);
1361 if (!should_hash_preload(mm, ea))
1364 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1365 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1367 /* Get Linux PTE if available */
1373 ssize = user_segment_size(ea);
1374 vsid = get_vsid(mm->context.id, ea, ssize);
1378 * Hash doesn't like irqs. Walking linux page table with irq disabled
1379 * saves us from holding multiple locks.
1381 local_irq_save(flags);
1384 * THP pages use update_mmu_cache_pmd. We don't do
1385 * hash preload there. Hence can ignore THP here
1387 ptep = find_linux_pte_or_hugepte(pgdir, ea, NULL, &hugepage_shift);
1391 WARN_ON(hugepage_shift);
1392 #ifdef CONFIG_PPC_64K_PAGES
1393 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1394 * a 64K kernel), then we don't preload, hash_page() will take
1395 * care of it once we actually try to access the page.
1396 * That way we don't have to duplicate all of the logic for segment
1397 * page size demotion here
1399 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1401 #endif /* CONFIG_PPC_64K_PAGES */
1403 /* Is that local to this CPU ? */
1404 if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
1405 update_flags |= HPTE_LOCAL_UPDATE;
1408 #ifdef CONFIG_PPC_64K_PAGES
1409 if (mm->context.user_psize == MMU_PAGE_64K)
1410 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1411 update_flags, ssize);
1413 #endif /* CONFIG_PPC_64K_PAGES */
1414 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1415 ssize, subpage_protection(mm, ea));
1417 /* Dump some info in case of hash insertion failure, they should
1418 * never happen so it is really useful to know if/when they do
1421 hash_failure_debug(ea, access, vsid, trap, ssize,
1422 mm->context.user_psize,
1423 mm->context.user_psize,
1426 local_irq_restore(flags);
1429 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1430 * do not forget to update the assembly call site !
1432 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1433 unsigned long flags)
1435 unsigned long hash, index, shift, hidx, slot;
1436 int local = flags & HPTE_LOCAL_UPDATE;
1438 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1439 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1440 hash = hpt_hash(vpn, shift, ssize);
1441 hidx = __rpte_to_hidx(pte, index);
1442 if (hidx & _PTEIDX_SECONDARY)
1444 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1445 slot += hidx & _PTEIDX_GROUP_IX;
1446 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
1448 * We use same base page size and actual psize, because we don't
1449 * use these functions for hugepage
1451 ppc_md.hpte_invalidate(slot, vpn, psize, psize, ssize, local);
1452 } pte_iterate_hashed_end();
1454 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1455 /* Transactions are not aborted by tlbiel, only tlbie.
1456 * Without, syncing a page back to a block device w/ PIO could pick up
1457 * transactional data (bad!) so we force an abort here. Before the
1458 * sync the page will be made read-only, which will flush_hash_page.
1459 * BIG ISSUE here: if the kernel uses a page from userspace without
1460 * unmapping it first, it may see the speculated version.
1462 if (local && cpu_has_feature(CPU_FTR_TM) &&
1463 current->thread.regs &&
1464 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1466 tm_abort(TM_CAUSE_TLBI);
1471 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1472 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1473 pmd_t *pmdp, unsigned int psize, int ssize,
1474 unsigned long flags)
1476 int i, max_hpte_count, valid;
1477 unsigned long s_addr;
1478 unsigned char *hpte_slot_array;
1479 unsigned long hidx, shift, vpn, hash, slot;
1480 int local = flags & HPTE_LOCAL_UPDATE;
1482 s_addr = addr & HPAGE_PMD_MASK;
1483 hpte_slot_array = get_hpte_slot_array(pmdp);
1485 * IF we try to do a HUGE PTE update after a withdraw is done.
1486 * we will find the below NULL. This happens when we do
1487 * split_huge_page_pmd
1489 if (!hpte_slot_array)
1492 if (ppc_md.hugepage_invalidate) {
1493 ppc_md.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1494 psize, ssize, local);
1498 * No bluk hpte removal support, invalidate each entry
1500 shift = mmu_psize_defs[psize].shift;
1501 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1502 for (i = 0; i < max_hpte_count; i++) {
1504 * 8 bits per each hpte entries
1505 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1507 valid = hpte_valid(hpte_slot_array, i);
1510 hidx = hpte_hash_index(hpte_slot_array, i);
1513 addr = s_addr + (i * (1ul << shift));
1514 vpn = hpt_vpn(addr, vsid, ssize);
1515 hash = hpt_hash(vpn, shift, ssize);
1516 if (hidx & _PTEIDX_SECONDARY)
1519 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1520 slot += hidx & _PTEIDX_GROUP_IX;
1521 ppc_md.hpte_invalidate(slot, vpn, psize,
1522 MMU_PAGE_16M, ssize, local);
1525 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1526 /* Transactions are not aborted by tlbiel, only tlbie.
1527 * Without, syncing a page back to a block device w/ PIO could pick up
1528 * transactional data (bad!) so we force an abort here. Before the
1529 * sync the page will be made read-only, which will flush_hash_page.
1530 * BIG ISSUE here: if the kernel uses a page from userspace without
1531 * unmapping it first, it may see the speculated version.
1533 if (local && cpu_has_feature(CPU_FTR_TM) &&
1534 current->thread.regs &&
1535 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1537 tm_abort(TM_CAUSE_TLBI);
1542 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1544 void flush_hash_range(unsigned long number, int local)
1546 if (ppc_md.flush_hash_range)
1547 ppc_md.flush_hash_range(number, local);
1550 struct ppc64_tlb_batch *batch =
1551 this_cpu_ptr(&ppc64_tlb_batch);
1553 for (i = 0; i < number; i++)
1554 flush_hash_page(batch->vpn[i], batch->pte[i],
1555 batch->psize, batch->ssize, local);
1560 * low_hash_fault is called when we the low level hash code failed
1561 * to instert a PTE due to an hypervisor error
1563 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1565 enum ctx_state prev_state = exception_enter();
1567 if (user_mode(regs)) {
1568 #ifdef CONFIG_PPC_SUBPAGE_PROT
1570 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1573 _exception(SIGBUS, regs, BUS_ADRERR, address);
1575 bad_page_fault(regs, address, SIGBUS);
1577 exception_exit(prev_state);
1580 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1581 unsigned long pa, unsigned long rflags,
1582 unsigned long vflags, int psize, int ssize)
1584 unsigned long hpte_group;
1588 hpte_group = ((hash & htab_hash_mask) *
1589 HPTES_PER_GROUP) & ~0x7UL;
1591 /* Insert into the hash table, primary slot */
1592 slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1593 psize, psize, ssize);
1595 /* Primary is full, try the secondary */
1596 if (unlikely(slot == -1)) {
1597 hpte_group = ((~hash & htab_hash_mask) *
1598 HPTES_PER_GROUP) & ~0x7UL;
1599 slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags,
1600 vflags | HPTE_V_SECONDARY,
1601 psize, psize, ssize);
1604 hpte_group = ((hash & htab_hash_mask) *
1605 HPTES_PER_GROUP)&~0x7UL;
1607 ppc_md.hpte_remove(hpte_group);
1615 #ifdef CONFIG_DEBUG_PAGEALLOC
1616 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1619 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1620 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1621 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1624 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1626 /* Don't create HPTE entries for bad address */
1630 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1632 mmu_linear_psize, mmu_kernel_ssize);
1635 spin_lock(&linear_map_hash_lock);
1636 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1637 linear_map_hash_slots[lmi] = ret | 0x80;
1638 spin_unlock(&linear_map_hash_lock);
1641 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1643 unsigned long hash, hidx, slot;
1644 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1645 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1647 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1648 spin_lock(&linear_map_hash_lock);
1649 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1650 hidx = linear_map_hash_slots[lmi] & 0x7f;
1651 linear_map_hash_slots[lmi] = 0;
1652 spin_unlock(&linear_map_hash_lock);
1653 if (hidx & _PTEIDX_SECONDARY)
1655 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1656 slot += hidx & _PTEIDX_GROUP_IX;
1657 ppc_md.hpte_invalidate(slot, vpn, mmu_linear_psize, mmu_linear_psize,
1658 mmu_kernel_ssize, 0);
1661 void __kernel_map_pages(struct page *page, int numpages, int enable)
1663 unsigned long flags, vaddr, lmi;
1666 local_irq_save(flags);
1667 for (i = 0; i < numpages; i++, page++) {
1668 vaddr = (unsigned long)page_address(page);
1669 lmi = __pa(vaddr) >> PAGE_SHIFT;
1670 if (lmi >= linear_map_hash_count)
1673 kernel_map_linear_page(vaddr, lmi);
1675 kernel_unmap_linear_page(vaddr, lmi);
1677 local_irq_restore(flags);
1679 #endif /* CONFIG_DEBUG_PAGEALLOC */
1681 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1682 phys_addr_t first_memblock_size)
1684 /* We don't currently support the first MEMBLOCK not mapping 0
1685 * physical on those processors
1687 BUG_ON(first_memblock_base != 0);
1689 /* On LPAR systems, the first entry is our RMA region,
1690 * non-LPAR 64-bit hash MMU systems don't have a limitation
1691 * on real mode access, but using the first entry works well
1692 * enough. We also clamp it to 1G to avoid some funky things
1693 * such as RTAS bugs etc...
1695 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
1697 /* Finally limit subsequent allocations */
1698 memblock_set_current_limit(ppc64_rma_size);