3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
11 * This file contains low-level assembler routines for managing
12 * the PowerPC MMU hash table. (PPC 8xx processors don't use a
13 * hash table, so this file is not used on them.)
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <asm/pgtable.h>
25 #include <asm/cputable.h>
26 #include <asm/ppc_asm.h>
27 #include <asm/thread_info.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/export.h>
30 #include <asm/feature-fixups.h>
31 #include <asm/code-patching-asm.h>
38 #endif /* CONFIG_SMP */
41 * Load a PTE into the hash table, if possible.
42 * The address is in r4, and r3 contains an access flag:
43 * _PAGE_RW (0x400) if a write.
44 * r9 contains the SRR1 value, from which we use the MSR_PR bit.
45 * SPRG_THREAD contains the physical address of the current task's thread.
47 * Returns to the caller if the access is illegal or there is no
48 * mapping for the address. Otherwise it places an appropriate PTE
49 * in the hash table and returns from the exception.
50 * Uses r0, r3 - r8, r10, ctr, lr.
54 tophys(r7,0) /* gets -KERNELBASE into r7 */
56 addis r8,r7,mmu_hash_lock@h
57 ori r8,r8,mmu_hash_lock@l
70 /* Get PTE (linux-style) and check access */
71 lis r0,KERNELBASE@h /* check if kernel address */
73 ori r3,r3,_PAGE_USER|_PAGE_PRESENT /* test low addresses as user */
74 mfspr r5, SPRN_SPRG_PGDIR /* virt page-table root */
75 blt+ 112f /* assume user more likely */
76 lis r5,swapper_pg_dir@ha /* if kernel address, use */
77 addi r5,r5,swapper_pg_dir@l /* kernel page table */
78 rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
79 112: add r5,r5,r7 /* convert to phys addr */
80 #ifndef CONFIG_PTE_64BIT
81 rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
82 lwz r8,0(r5) /* get pmd entry */
83 rlwinm. r8,r8,0,0,19 /* extract address of pte page */
85 rlwinm r8,r4,13,19,29 /* Compute pgdir/pmd offset */
86 lwzx r8,r8,r5 /* Get L1 entry */
87 rlwinm. r8,r8,0,0,20 /* extract pt base address */
90 beq- hash_page_out /* return if no mapping */
92 /* XXX it seems like the 601 will give a machine fault on the
93 rfi if its alignment is wrong (bottom 4 bits of address are
94 8 or 0xc) and we have had a not-taken conditional branch
95 to the address following the rfi. */
98 #ifndef CONFIG_PTE_64BIT
99 rlwimi r8,r4,22,20,29 /* insert next 10 bits of address */
101 rlwimi r8,r4,23,20,28 /* compute pte address */
103 rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */
104 ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE
107 * Update the linux PTE atomically. We do the lwarx up-front
108 * because almost always, there won't be a permission violation
109 * and there won't already be an HPTE, and thus we will have
110 * to update the PTE to set _PAGE_HASHPTE. -- paulus.
112 * If PTE_64BIT is set, the low word is the flags word; use that
113 * word for locking since it contains all the interesting bits.
115 #if (PTE_FLAGS_OFFSET != 0)
116 addi r8,r8,PTE_FLAGS_OFFSET
119 lwarx r6,0,r8 /* get linux-style pte, flag word */
120 andc. r5,r3,r6 /* check access & ~permission */
122 bne- hash_page_out /* return if access not permitted */
126 or r5,r0,r6 /* set accessed/dirty bits */
127 #ifdef CONFIG_PTE_64BIT
129 subf r10,r6,r8 /* create false data dependency */
130 subi r10,r10,PTE_FLAGS_OFFSET
131 lwzx r10,r6,r10 /* Get upper PTE word */
133 lwz r10,-PTE_FLAGS_OFFSET(r8)
134 #endif /* CONFIG_SMP */
135 #endif /* CONFIG_PTE_64BIT */
136 stwcx. r5,0,r8 /* attempt to update PTE */
137 bne- retry /* retry if someone got there first */
139 mfsrin r3,r4 /* get segment reg for segment */
142 bl create_hpte /* add the hash table entry */
146 addis r8,r7,mmu_hash_lock@ha
148 stw r0,mmu_hash_lock@l(r8)
151 /* Return from the exception */
157 b fast_exception_return
162 addis r8,r7,mmu_hash_lock@ha
164 stw r0,mmu_hash_lock@l(r8)
166 #endif /* CONFIG_SMP */
169 * Add an entry for a particular page to the hash table.
171 * add_hash_page(unsigned context, unsigned long va, unsigned long pmdval)
173 * We assume any necessary modifications to the pte (e.g. setting
174 * the accessed bit) have already been done and that there is actually
175 * a hash table in use (i.e. we're not on a 603).
177 _GLOBAL(add_hash_page)
181 /* Convert context and va to VSID */
182 mulli r3,r3,897*16 /* multiply context by context skew */
183 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
184 mulli r0,r0,0x111 /* multiply by ESID skew */
185 add r3,r3,r0 /* note create_hpte trims to 24 bits */
188 CURRENT_THREAD_INFO(r8, r1) /* use cpu number to make tag */
189 lwz r8,TI_CPU(r8) /* to go in mmu_hash_lock */
191 #endif /* CONFIG_SMP */
194 * We disable interrupts here, even on UP, because we don't
195 * want to race with hash_page, and because we want the
196 * _PAGE_HASHPTE bit to be a reliable indication of whether
197 * the HPTE exists (or at least whether one did once).
198 * We also turn off the MMU for data accesses so that we
199 * we can't take a hash table miss (assuming the code is
200 * covered by a BAT). -- paulus
204 rlwinm r0,r9,0,17,15 /* clear bit 16 (MSR_EE) */
205 rlwinm r0,r0,0,28,26 /* clear MSR_DR */
213 addis r6,r7,mmu_hash_lock@ha
214 addi r6,r6,mmu_hash_lock@l
215 10: lwarx r0,0,r6 /* take the mmu_hash_lock */
228 * Fetch the linux pte and test and set _PAGE_HASHPTE atomically.
229 * If _PAGE_HASHPTE was already set, we don't replace the existing
230 * HPTE, so we just unlock and return.
233 #ifndef CONFIG_PTE_64BIT
234 rlwimi r8,r4,22,20,29
236 rlwimi r8,r4,23,20,28
237 addi r8,r8,PTE_FLAGS_OFFSET
240 andi. r0,r6,_PAGE_HASHPTE
241 bne 9f /* if HASHPTE already set, done */
242 #ifdef CONFIG_PTE_64BIT
244 subf r10,r6,r8 /* create false data dependency */
245 subi r10,r10,PTE_FLAGS_OFFSET
246 lwzx r10,r6,r10 /* Get upper PTE word */
248 lwz r10,-PTE_FLAGS_OFFSET(r8)
249 #endif /* CONFIG_SMP */
250 #endif /* CONFIG_PTE_64BIT */
251 ori r5,r6,_PAGE_HASHPTE
259 addis r6,r7,mmu_hash_lock@ha
260 addi r6,r6,mmu_hash_lock@l
263 stw r0,0(r6) /* clear mmu_hash_lock */
266 /* reenable interrupts and DR */
276 * This routine adds a hardware PTE to the hash table.
277 * It is designed to be called with the MMU either on or off.
278 * r3 contains the VSID, r4 contains the virtual address,
279 * r5 contains the linux PTE, r6 contains the old value of the
280 * linux PTE (before setting _PAGE_HASHPTE) and r7 contains the
281 * offset to be added to addresses (0 if the MMU is on,
282 * -KERNELBASE if it is off). r10 contains the upper half of
283 * the PTE if CONFIG_PTE_64BIT.
284 * On SMP, the caller should have the mmu_hash_lock held.
285 * We assume that the caller has (or will) set the _PAGE_HASHPTE
286 * bit in the linux PTE in memory. The value passed in r6 should
287 * be the old linux PTE value; if it doesn't have _PAGE_HASHPTE set
288 * this routine will skip the search for an existing HPTE.
289 * This procedure modifies r0, r3 - r6, r8, cr0.
292 * For speed, 4 of the instructions get patched once the size and
293 * physical address of the hash table are known. These definitions
294 * of Hash_base and Hash_bits below are just an example.
296 Hash_base = 0xc0180000
297 Hash_bits = 12 /* e.g. 256kB hash table */
298 Hash_msk = (((1 << Hash_bits) - 1) * 64)
300 /* defines for the PTE format for 32-bit PPCs */
303 #define LG_PTEG_SIZE 6
309 #define PTE_V 0x80000000
310 #define TST_V(r) rlwinm. r,r,0,0,0
311 #define SET_V(r) oris r,r,PTE_V@h
312 #define CLR_V(r,t) rlwinm r,r,0,1,31
314 #define HASH_LEFT 31-(LG_PTEG_SIZE+Hash_bits-1)
315 #define HASH_RIGHT 31-LG_PTEG_SIZE
318 /* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */
319 rlwinm r8,r5,32-10,31,31 /* _PAGE_RW -> PP lsb */
320 rlwinm r0,r5,32-7,31,31 /* _PAGE_DIRTY -> PP lsb */
321 and r8,r8,r0 /* writable if _RW & _DIRTY */
322 rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */
323 rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */
324 ori r8,r8,0xe04 /* clear out reserved bits */
325 andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */
327 rlwinm r8,r8,0,~_PAGE_COHERENT /* clear M (coherence not required) */
328 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
329 #ifdef CONFIG_PTE_64BIT
330 /* Put the XPN bits into the PTE */
331 rlwimi r8,r10,8,20,22
332 rlwimi r8,r10,2,29,29
335 /* Construct the high word of the PPC-style PTE (r5) */
336 rlwinm r5,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
337 rlwimi r5,r4,10,26,31 /* put in API (abbrev page index) */
338 SET_V(r5) /* set V (valid) bit */
340 patch_site 0f, patch__hash_page_A0
341 patch_site 1f, patch__hash_page_A1
342 patch_site 2f, patch__hash_page_A2
343 /* Get the address of the primary PTE group in the hash table (r3) */
344 0: addis r0,r7,Hash_base@h /* base address of hash table */
345 1: rlwimi r0,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
346 2: rlwinm r3,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
347 xor r3,r3,r0 /* make primary hash */
348 li r0,8 /* PTEs/group */
351 * Test the _PAGE_HASHPTE bit in the old linux PTE, and skip the search
352 * if it is clear, meaning that the HPTE isn't there already...
354 andi. r6,r6,_PAGE_HASHPTE
355 beq+ 10f /* no PTE: go look for an empty slot */
358 addis r4,r7,htab_hash_searches@ha
359 lwz r6,htab_hash_searches@l(r4)
360 addi r6,r6,1 /* count how many searches we do */
361 stw r6,htab_hash_searches@l(r4)
363 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
365 addi r4,r3,-HPTE_SIZE
366 1: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */
368 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
371 patch_site 0f, patch__hash_page_B
372 /* Search the secondary PTEG for a matching PTE */
373 ori r5,r5,PTE_H /* set H (secondary hash) bit */
374 0: xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
375 xori r4,r4,(-PTEG_SIZE & 0xffff)
376 addi r4,r4,-HPTE_SIZE
378 2: LDPTEu r6,HPTE_SIZE(r4)
382 xori r5,r5,PTE_H /* clear H bit again */
384 /* Search the primary PTEG for an empty slot */
386 addi r4,r3,-HPTE_SIZE /* search primary PTEG */
387 1: LDPTEu r6,HPTE_SIZE(r4) /* get next PTE */
388 TST_V(r6) /* test valid bit */
389 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
392 /* update counter of times that the primary PTEG is full */
393 addis r4,r7,primary_pteg_full@ha
394 lwz r6,primary_pteg_full@l(r4)
396 stw r6,primary_pteg_full@l(r4)
398 patch_site 0f, patch__hash_page_C
399 /* Search the secondary PTEG for an empty slot */
400 ori r5,r5,PTE_H /* set H (secondary hash) bit */
401 0: xoris r4,r3,Hash_msk>>16 /* compute secondary hash */
402 xori r4,r4,(-PTEG_SIZE & 0xffff)
403 addi r4,r4,-HPTE_SIZE
405 2: LDPTEu r6,HPTE_SIZE(r4)
409 xori r5,r5,PTE_H /* clear H bit again */
412 * Choose an arbitrary slot in the primary PTEG to overwrite.
413 * Since both the primary and secondary PTEGs are full, and we
414 * have no information that the PTEs in the primary PTEG are
415 * more important or useful than those in the secondary PTEG,
416 * and we know there is a definite (although small) speed
417 * advantage to putting the PTE in the primary PTEG, we always
418 * put the PTE in the primary PTEG.
420 * In addition, we skip any slot that is mapping kernel text in
421 * order to avoid a deadlock when not using BAT mappings if
422 * trying to hash in the kernel hash code itself after it has
423 * already taken the hash table lock. This works in conjunction
424 * with pre-faulting of the kernel text.
426 * If the hash table bucket is full of kernel text entries, we'll
427 * lockup here but that shouldn't happen
430 1: addis r4,r7,next_slot@ha /* get next evict slot */
431 lwz r6,next_slot@l(r4)
432 addi r6,r6,HPTE_SIZE /* search for candidate */
433 andi. r6,r6,7*HPTE_SIZE
434 stw r6,next_slot@l(r4)
436 LDPTE r0,HPTE_SIZE/2(r4) /* get PTE second word */
439 ori r6,r6,etext@l /* get etext */
441 cmpl cr0,r0,r6 /* compare and try again */
445 /* Store PTE in PTEG */
449 STPTE r8,HPTE_SIZE/2(r4)
451 #else /* CONFIG_SMP */
453 * Between the tlbie above and updating the hash table entry below,
454 * another CPU could read the hash table entry and put it in its TLB.
456 * 1. using an empty slot
457 * 2. updating an earlier entry to change permissions (i.e. enable write)
458 * 3. taking over the PTE for an unrelated address
460 * In each case it doesn't really matter if the other CPUs have the old
461 * PTE in their TLB. So we don't need to bother with another tlbie here,
462 * which is convenient as we've overwritten the register that had the
463 * address. :-) The tlbie above is mainly to make sure that this CPU comes
464 * and gets the new PTE from the hash table.
466 * We do however have to make sure that the PTE is never in an invalid
467 * state with the V bit set.
471 CLR_V(r5,r0) /* clear V (valid) bit in PTE */
475 STPTE r8,HPTE_SIZE/2(r4) /* put in correct RPN, WIMG, PP bits */
478 STPTE r5,0(r4) /* finally set V bit in PTE */
479 #endif /* CONFIG_SMP */
481 sync /* make sure pte updates get to memory */
495 * Flush the entry for a particular page from the hash table.
497 * flush_hash_pages(unsigned context, unsigned long va, unsigned long pmdval,
500 * We assume that there is a hash table in use (Hash != 0).
502 _GLOBAL(flush_hash_pages)
506 * We disable interrupts here, even on UP, because we want
507 * the _PAGE_HASHPTE bit to be a reliable indication of
508 * whether the HPTE exists (or at least whether one did once).
509 * We also turn off the MMU for data accesses so that we
510 * we can't take a hash table miss (assuming the code is
511 * covered by a BAT). -- paulus
515 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
516 rlwinm r0,r0,0,28,26 /* clear MSR_DR */
521 /* First find a PTE in the range that has _PAGE_HASHPTE set */
522 #ifndef CONFIG_PTE_64BIT
523 rlwimi r5,r4,22,20,29
525 rlwimi r5,r4,23,20,28
527 1: lwz r0,PTE_FLAGS_OFFSET(r5)
529 andi. r0,r0,_PAGE_HASHPTE
537 /* Convert context and va to VSID */
538 2: mulli r3,r3,897*16 /* multiply context by context skew */
539 rlwinm r0,r4,4,28,31 /* get ESID (top 4 bits of va) */
540 mulli r0,r0,0x111 /* multiply by ESID skew */
541 add r3,r3,r0 /* note code below trims to 24 bits */
543 /* Construct the high word of the PPC-style PTE (r11) */
544 rlwinm r11,r3,7,1,24 /* put VSID in 0x7fffff80 bits */
545 rlwimi r11,r4,10,26,31 /* put in API (abbrev page index) */
546 SET_V(r11) /* set V (valid) bit */
549 addis r9,r7,mmu_hash_lock@ha
550 addi r9,r9,mmu_hash_lock@l
551 CURRENT_THREAD_INFO(r8, r1)
568 * Check the _PAGE_HASHPTE bit in the linux PTE. If it is
569 * already clear, we're done (for this pte). If not,
570 * clear it (atomically) and proceed. -- paulus.
572 #if (PTE_FLAGS_OFFSET != 0)
573 addi r5,r5,PTE_FLAGS_OFFSET
575 33: lwarx r8,0,r5 /* fetch the pte flags word */
576 andi. r0,r8,_PAGE_HASHPTE
577 beq 8f /* done if HASHPTE is already clear */
578 rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */
579 stwcx. r8,0,r5 /* update the pte */
582 patch_site 0f, patch__flush_hash_A0
583 patch_site 1f, patch__flush_hash_A1
584 patch_site 2f, patch__flush_hash_A2
585 /* Get the address of the primary PTE group in the hash table (r3) */
586 0: addis r8,r7,Hash_base@h /* base address of hash table */
587 1: rlwimi r8,r3,LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* VSID -> hash */
588 2: rlwinm r0,r4,20+LG_PTEG_SIZE,HASH_LEFT,HASH_RIGHT /* PI -> hash */
589 xor r8,r0,r8 /* make primary hash */
591 /* Search the primary PTEG for a PTE whose 1st (d)word matches r5 */
592 li r0,8 /* PTEs/group */
594 addi r12,r8,-HPTE_SIZE
595 1: LDPTEu r0,HPTE_SIZE(r12) /* get next PTE */
597 bdnzf 2,1b /* loop while ctr != 0 && !cr0.eq */
600 patch_site 0f, patch__flush_hash_B
601 /* Search the secondary PTEG for a matching PTE */
602 ori r11,r11,PTE_H /* set H (secondary hash) bit */
603 li r0,8 /* PTEs/group */
604 0: xoris r12,r8,Hash_msk>>16 /* compute secondary hash */
605 xori r12,r12,(-PTEG_SIZE & 0xffff)
606 addi r12,r12,-HPTE_SIZE
608 2: LDPTEu r0,HPTE_SIZE(r12)
611 xori r11,r11,PTE_H /* clear H again */
612 bne- 4f /* should rarely fail to find it */
615 STPTE r0,0(r12) /* invalidate entry */
617 tlbie r4 /* in hw tlb too */
620 8: ble cr1,9f /* if all ptes checked */
624 lwz r0,0(r5) /* check next pte */
626 andi. r0,r0,_PAGE_HASHPTE
634 stw r0,0(r9) /* clear mmu_hash_lock */
641 EXPORT_SYMBOL(flush_hash_pages)
644 * Flush an entry from the TLB
648 CURRENT_THREAD_INFO(r8, r1)
653 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
654 rlwinm r0,r0,0,28,26 /* clear DR */
658 lis r9,mmu_hash_lock@h
659 ori r9,r9,mmu_hash_lock@l
671 stw r0,0(r9) /* clear mmu_hash_lock */
675 #else /* CONFIG_SMP */
678 #endif /* CONFIG_SMP */
682 * Flush the entire TLB. 603/603e only
685 #if defined(CONFIG_SMP)
686 CURRENT_THREAD_INFO(r8, r1)
691 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
692 rlwinm r0,r0,0,28,26 /* clear DR */
696 lis r9,mmu_hash_lock@h
697 ori r9,r9,mmu_hash_lock@l
709 stw r0,0(r9) /* clear mmu_hash_lock */
713 #else /* CONFIG_SMP */
717 #endif /* CONFIG_SMP */