1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Page table handling routines for radix page table.
5 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
8 #define pr_fmt(fmt) "radix-mmu: " fmt
10 #include <linux/kernel.h>
11 #include <linux/sched/mm.h>
12 #include <linux/memblock.h>
13 #include <linux/of_fdt.h>
15 #include <linux/string_helpers.h>
16 #include <linux/stop_machine.h>
18 #include <asm/pgtable.h>
19 #include <asm/pgalloc.h>
20 #include <asm/mmu_context.h>
22 #include <asm/machdep.h>
24 #include <asm/firmware.h>
25 #include <asm/powernv.h>
26 #include <asm/sections.h>
27 #include <asm/trace.h>
28 #include <asm/uaccess.h>
30 #include <trace/events/thp.h>
32 unsigned int mmu_pid_bits;
33 unsigned int mmu_base_pid;
35 static int native_register_process_table(unsigned long base, unsigned long pg_sz,
36 unsigned long table_size)
38 unsigned long patb0, patb1;
40 patb0 = be64_to_cpu(partition_tb[0].patb0);
41 patb1 = base | table_size | PATB_GR;
43 mmu_partition_table_set_entry(0, patb0, patb1);
48 static __ref void *early_alloc_pgtable(unsigned long size, int nid,
49 unsigned long region_start, unsigned long region_end)
51 phys_addr_t min_addr = MEMBLOCK_LOW_LIMIT;
52 phys_addr_t max_addr = MEMBLOCK_ALLOC_ANYWHERE;
56 min_addr = region_start;
58 max_addr = region_end;
60 ptr = memblock_alloc_try_nid(size, size, min_addr, max_addr, nid);
63 panic("%s: Failed to allocate %lu bytes align=0x%lx nid=%d from=%pa max_addr=%pa\n",
64 __func__, size, size, nid, &min_addr, &max_addr);
69 static int early_map_kernel_page(unsigned long ea, unsigned long pa,
71 unsigned int map_page_size,
73 unsigned long region_start, unsigned long region_end)
75 unsigned long pfn = pa >> PAGE_SHIFT;
81 pgdp = pgd_offset_k(ea);
82 if (pgd_none(*pgdp)) {
83 pudp = early_alloc_pgtable(PUD_TABLE_SIZE, nid,
84 region_start, region_end);
85 pgd_populate(&init_mm, pgdp, pudp);
87 pudp = pud_offset(pgdp, ea);
88 if (map_page_size == PUD_SIZE) {
92 if (pud_none(*pudp)) {
93 pmdp = early_alloc_pgtable(PMD_TABLE_SIZE, nid,
94 region_start, region_end);
95 pud_populate(&init_mm, pudp, pmdp);
97 pmdp = pmd_offset(pudp, ea);
98 if (map_page_size == PMD_SIZE) {
99 ptep = pmdp_ptep(pmdp);
102 if (!pmd_present(*pmdp)) {
103 ptep = early_alloc_pgtable(PAGE_SIZE, nid,
104 region_start, region_end);
105 pmd_populate_kernel(&init_mm, pmdp, ptep);
107 ptep = pte_offset_kernel(pmdp, ea);
110 set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
116 * nid, region_start, and region_end are hints to try to place the page
117 * table memory in the same node or region.
119 static int __map_kernel_page(unsigned long ea, unsigned long pa,
121 unsigned int map_page_size,
123 unsigned long region_start, unsigned long region_end)
125 unsigned long pfn = pa >> PAGE_SHIFT;
131 * Make sure task size is correct as per the max adddr
133 BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
135 #ifdef CONFIG_PPC_64K_PAGES
136 BUILD_BUG_ON(RADIX_KERN_MAP_SIZE != (1UL << MAX_EA_BITS_PER_CONTEXT));
139 if (unlikely(!slab_is_available()))
140 return early_map_kernel_page(ea, pa, flags, map_page_size,
141 nid, region_start, region_end);
144 * Should make page table allocation functions be able to take a
145 * node, so we can place kernel page tables on the right nodes after
148 pgdp = pgd_offset_k(ea);
149 pudp = pud_alloc(&init_mm, pgdp, ea);
152 if (map_page_size == PUD_SIZE) {
153 ptep = (pte_t *)pudp;
156 pmdp = pmd_alloc(&init_mm, pudp, ea);
159 if (map_page_size == PMD_SIZE) {
160 ptep = pmdp_ptep(pmdp);
163 ptep = pte_alloc_kernel(pmdp, ea);
168 set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
173 int radix__map_kernel_page(unsigned long ea, unsigned long pa,
175 unsigned int map_page_size)
177 return __map_kernel_page(ea, pa, flags, map_page_size, -1, 0, 0);
180 #ifdef CONFIG_STRICT_KERNEL_RWX
181 void radix__change_memory_range(unsigned long start, unsigned long end,
190 start = ALIGN_DOWN(start, PAGE_SIZE);
191 end = PAGE_ALIGN(end); // aligns up
193 pr_debug("Changing flags on range %lx-%lx removing 0x%lx\n",
196 for (idx = start; idx < end; idx += PAGE_SIZE) {
197 pgdp = pgd_offset_k(idx);
198 pudp = pud_alloc(&init_mm, pgdp, idx);
201 if (pud_huge(*pudp)) {
202 ptep = (pte_t *)pudp;
205 pmdp = pmd_alloc(&init_mm, pudp, idx);
208 if (pmd_huge(*pmdp)) {
209 ptep = pmdp_ptep(pmdp);
212 ptep = pte_alloc_kernel(pmdp, idx);
216 radix__pte_update(&init_mm, idx, ptep, clear, 0, 0);
219 radix__flush_tlb_kernel_range(start, end);
222 void radix__mark_rodata_ro(void)
224 unsigned long start, end;
226 start = (unsigned long)_stext;
227 end = (unsigned long)__init_begin;
229 radix__change_memory_range(start, end, _PAGE_WRITE);
232 void radix__mark_initmem_nx(void)
234 unsigned long start = (unsigned long)__init_begin;
235 unsigned long end = (unsigned long)__init_end;
237 radix__change_memory_range(start, end, _PAGE_EXEC);
239 #endif /* CONFIG_STRICT_KERNEL_RWX */
241 static inline void __meminit
242 print_mapping(unsigned long start, unsigned long end, unsigned long size, bool exec)
249 string_get_size(size, 1, STRING_UNITS_2, buf, sizeof(buf));
251 pr_info("Mapped 0x%016lx-0x%016lx with %s pages%s\n", start, end, buf,
252 exec ? " (exec)" : "");
255 static unsigned long next_boundary(unsigned long addr, unsigned long end)
257 #ifdef CONFIG_STRICT_KERNEL_RWX
258 if (addr < __pa_symbol(__init_begin))
259 return __pa_symbol(__init_begin);
264 static int __meminit create_physical_mapping(unsigned long start,
268 unsigned long vaddr, addr, mapping_size = 0;
269 bool prev_exec, exec = false;
273 start = _ALIGN_UP(start, PAGE_SIZE);
274 for (addr = start; addr < end; addr += mapping_size) {
275 unsigned long gap, previous_size;
278 gap = next_boundary(addr, end) - addr;
279 previous_size = mapping_size;
282 if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE &&
283 mmu_psize_defs[MMU_PAGE_1G].shift) {
284 mapping_size = PUD_SIZE;
286 } else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE &&
287 mmu_psize_defs[MMU_PAGE_2M].shift) {
288 mapping_size = PMD_SIZE;
291 mapping_size = PAGE_SIZE;
292 psize = mmu_virtual_psize;
295 vaddr = (unsigned long)__va(addr);
297 if (overlaps_kernel_text(vaddr, vaddr + mapping_size) ||
298 overlaps_interrupt_vector_text(vaddr, vaddr + mapping_size)) {
299 prot = PAGE_KERNEL_X;
306 if (mapping_size != previous_size || exec != prev_exec) {
307 print_mapping(start, addr, previous_size, prev_exec);
311 rc = __map_kernel_page(vaddr, addr, prot, mapping_size, nid, start, end);
315 update_page_count(psize, 1);
318 print_mapping(start, addr, mapping_size, exec);
322 void __init radix_init_pgtable(void)
324 unsigned long rts_field;
325 struct memblock_region *reg;
327 /* We don't support slb for radix */
330 * Create the linear mapping, using standard page size for now
332 for_each_memblock(memory, reg) {
334 * The memblock allocator is up at this point, so the
335 * page tables will be allocated within the range. No
336 * need or a node (which we don't have yet).
339 if ((reg->base + reg->size) >= RADIX_VMALLOC_START) {
340 pr_warn("Outside the supported range\n");
344 WARN_ON(create_physical_mapping(reg->base,
345 reg->base + reg->size,
349 /* Find out how many PID bits are supported */
350 if (cpu_has_feature(CPU_FTR_HVMODE)) {
353 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
355 * When KVM is possible, we only use the top half of the
356 * PID space to avoid collisions between host and guest PIDs
357 * which can cause problems due to prefetch when exiting the
360 mmu_base_pid = 1 << (mmu_pid_bits - 1);
365 /* The guest uses the bottom half of the PID space */
372 * Allocate Partition table and process table for the
375 BUG_ON(PRTB_SIZE_SHIFT > 36);
376 process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT, -1, 0, 0);
378 * Fill in the process table.
380 rts_field = radix__get_tree_size();
381 process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE);
383 * Fill in the partition table. We are suppose to use effective address
384 * of process table here. But our linear mapping also enable us to use
385 * physical address here.
387 register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12);
388 pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
389 asm volatile("ptesync" : : : "memory");
390 asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
391 "r" (TLBIEL_INVAL_SET_LPID), "r" (0));
392 asm volatile("eieio; tlbsync; ptesync" : : : "memory");
393 trace_tlbie(0, 0, TLBIEL_INVAL_SET_LPID, 0, 2, 1, 1);
396 * The init_mm context is given the first available (non-zero) PID,
397 * which is the "guard PID" and contains no page table. PIDR should
398 * never be set to zero because that duplicates the kernel address
399 * space at the 0x0... offset (quadrant 0)!
401 * An arbitrary PID that may later be allocated by the PID allocator
402 * for userspace processes must not be used either, because that
403 * would cause stale user mappings for that PID on CPUs outside of
404 * the TLB invalidation scheme (because it won't be in mm_cpumask).
406 * So permanently carve out one PID for the purpose of a guard PID.
408 init_mm.context.id = mmu_base_pid;
412 static void __init radix_init_partition_table(void)
414 unsigned long rts_field, dw0;
416 mmu_partition_table_init();
417 rts_field = radix__get_tree_size();
418 dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR;
419 mmu_partition_table_set_entry(0, dw0, 0);
421 pr_info("Initializing Radix MMU\n");
422 pr_info("Partition table %p\n", partition_tb);
425 void __init radix_init_native(void)
427 register_process_table = native_register_process_table;
430 static int __init get_idx_from_shift(unsigned int shift)
451 static int __init radix_dt_scan_page_sizes(unsigned long node,
452 const char *uname, int depth,
459 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
461 /* We are scanning "cpu" nodes only */
462 if (type == NULL || strcmp(type, "cpu") != 0)
465 /* Find MMU PID size */
466 prop = of_get_flat_dt_prop(node, "ibm,mmu-pid-bits", &size);
467 if (prop && size == 4)
468 mmu_pid_bits = be32_to_cpup(prop);
470 /* Grab page size encodings */
471 prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
475 pr_info("Page sizes from device-tree:\n");
476 for (; size >= 4; size -= 4, ++prop) {
478 struct mmu_psize_def *def;
480 /* top 3 bit is AP encoding */
481 shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
482 ap = be32_to_cpu(prop[0]) >> 29;
483 pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
485 idx = get_idx_from_shift(shift);
489 def = &mmu_psize_defs[idx];
495 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
499 void __init radix__early_init_devtree(void)
504 * Try to find the available page sizes in the device-tree
506 rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
507 if (rc != 0) /* Found */
510 * let's assume we have page 4k and 64k support
512 mmu_psize_defs[MMU_PAGE_4K].shift = 12;
513 mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;
515 mmu_psize_defs[MMU_PAGE_64K].shift = 16;
516 mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
518 #ifdef CONFIG_SPARSEMEM_VMEMMAP
519 if (mmu_psize_defs[MMU_PAGE_2M].shift) {
521 * map vmemmap using 2M if available
523 mmu_vmemmap_psize = MMU_PAGE_2M;
525 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
529 static void radix_init_amor(void)
532 * In HV mode, we init AMOR (Authority Mask Override Register) so that
533 * the hypervisor and guest can setup IAMR (Instruction Authority Mask
534 * Register), enable key 0 and set it to 1.
536 * AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)
538 mtspr(SPRN_AMOR, (3ul << 62));
541 #ifdef CONFIG_PPC_KUEP
542 void setup_kuep(bool disabled)
544 if (disabled || !early_radix_enabled())
547 if (smp_processor_id() == boot_cpuid)
548 pr_info("Activating Kernel Userspace Execution Prevention\n");
551 * Radix always uses key0 of the IAMR to determine if an access is
552 * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction
555 mtspr(SPRN_IAMR, (1ul << 62));
559 #ifdef CONFIG_PPC_KUAP
560 void setup_kuap(bool disabled)
562 if (disabled || !early_radix_enabled())
565 if (smp_processor_id() == boot_cpuid) {
566 pr_info("Activating Kernel Userspace Access Prevention\n");
567 cur_cpu_spec->mmu_features |= MMU_FTR_RADIX_KUAP;
570 /* Make sure userspace can't change the AMR */
571 mtspr(SPRN_UAMOR, 0);
572 mtspr(SPRN_AMR, AMR_KUAP_BLOCKED);
577 void __init radix__early_init_mmu(void)
581 #ifdef CONFIG_PPC_64K_PAGES
582 /* PAGE_SIZE mappings */
583 mmu_virtual_psize = MMU_PAGE_64K;
585 mmu_virtual_psize = MMU_PAGE_4K;
588 #ifdef CONFIG_SPARSEMEM_VMEMMAP
589 /* vmemmap mapping */
590 mmu_vmemmap_psize = mmu_virtual_psize;
593 * initialize page table size
595 __pte_index_size = RADIX_PTE_INDEX_SIZE;
596 __pmd_index_size = RADIX_PMD_INDEX_SIZE;
597 __pud_index_size = RADIX_PUD_INDEX_SIZE;
598 __pgd_index_size = RADIX_PGD_INDEX_SIZE;
599 __pud_cache_index = RADIX_PUD_INDEX_SIZE;
600 __pte_table_size = RADIX_PTE_TABLE_SIZE;
601 __pmd_table_size = RADIX_PMD_TABLE_SIZE;
602 __pud_table_size = RADIX_PUD_TABLE_SIZE;
603 __pgd_table_size = RADIX_PGD_TABLE_SIZE;
605 __pmd_val_bits = RADIX_PMD_VAL_BITS;
606 __pud_val_bits = RADIX_PUD_VAL_BITS;
607 __pgd_val_bits = RADIX_PGD_VAL_BITS;
609 __kernel_virt_start = RADIX_KERN_VIRT_START;
610 __vmalloc_start = RADIX_VMALLOC_START;
611 __vmalloc_end = RADIX_VMALLOC_END;
612 __kernel_io_start = RADIX_KERN_IO_START;
613 __kernel_io_end = RADIX_KERN_IO_END;
614 vmemmap = (struct page *)RADIX_VMEMMAP_START;
615 ioremap_bot = IOREMAP_BASE;
618 pci_io_base = ISA_IO_BASE;
620 __pte_frag_nr = RADIX_PTE_FRAG_NR;
621 __pte_frag_size_shift = RADIX_PTE_FRAG_SIZE_SHIFT;
622 __pmd_frag_nr = RADIX_PMD_FRAG_NR;
623 __pmd_frag_size_shift = RADIX_PMD_FRAG_SIZE_SHIFT;
625 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
627 lpcr = mfspr(SPRN_LPCR);
628 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
629 radix_init_partition_table();
632 radix_init_pseries();
635 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
637 radix_init_pgtable();
638 /* Switch to the guard PID before turning on MMU */
639 radix__switch_mmu_context(NULL, &init_mm);
640 if (cpu_has_feature(CPU_FTR_HVMODE))
644 void radix__early_init_mmu_secondary(void)
648 * update partition table control register and UPRT
650 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
651 lpcr = mfspr(SPRN_LPCR);
652 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
655 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
659 radix__switch_mmu_context(NULL, &init_mm);
660 if (cpu_has_feature(CPU_FTR_HVMODE))
664 void radix__mmu_cleanup_all(void)
668 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
669 lpcr = mfspr(SPRN_LPCR);
670 mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
672 powernv_set_nmmu_ptcr(0);
673 radix__flush_tlb_all();
677 void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
678 phys_addr_t first_memblock_size)
681 * We don't currently support the first MEMBLOCK not mapping 0
682 * physical on those processors
684 BUG_ON(first_memblock_base != 0);
687 * Radix mode is not limited by RMA / VRMA addressing.
689 ppc64_rma_size = ULONG_MAX;
692 #ifdef CONFIG_MEMORY_HOTPLUG
693 static void free_pte_table(pte_t *pte_start, pmd_t *pmd)
698 for (i = 0; i < PTRS_PER_PTE; i++) {
704 pte_free_kernel(&init_mm, pte_start);
708 static void free_pmd_table(pmd_t *pmd_start, pud_t *pud)
713 for (i = 0; i < PTRS_PER_PMD; i++) {
719 pmd_free(&init_mm, pmd_start);
723 struct change_mapping_params {
727 unsigned long aligned_start;
728 unsigned long aligned_end;
731 static int __meminit stop_machine_change_mapping(void *data)
733 struct change_mapping_params *params =
734 (struct change_mapping_params *)data;
739 spin_unlock(&init_mm.page_table_lock);
740 pte_clear(&init_mm, params->aligned_start, params->pte);
741 create_physical_mapping(params->aligned_start, params->start, -1);
742 create_physical_mapping(params->end, params->aligned_end, -1);
743 spin_lock(&init_mm.page_table_lock);
747 static void remove_pte_table(pte_t *pte_start, unsigned long addr,
753 pte = pte_start + pte_index(addr);
754 for (; addr < end; addr = next, pte++) {
755 next = (addr + PAGE_SIZE) & PAGE_MASK;
759 if (!pte_present(*pte))
762 if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(next)) {
764 * The vmemmap_free() and remove_section_mapping()
765 * codepaths call us with aligned addresses.
767 WARN_ONCE(1, "%s: unaligned range\n", __func__);
771 pte_clear(&init_mm, addr, pte);
776 * clear the pte and potentially split the mapping helper
778 static void __meminit split_kernel_mapping(unsigned long addr, unsigned long end,
779 unsigned long size, pte_t *pte)
781 unsigned long mask = ~(size - 1);
782 unsigned long aligned_start = addr & mask;
783 unsigned long aligned_end = addr + size;
784 struct change_mapping_params params;
785 bool split_region = false;
787 if ((end - addr) < size) {
789 * We're going to clear the PTE, but not flushed
790 * the mapping, time to remap and flush. The
791 * effects if visible outside the processor or
792 * if we are running in code close to the
793 * mapping we cleared, we are in trouble.
795 if (overlaps_kernel_text(aligned_start, addr) ||
796 overlaps_kernel_text(end, aligned_end)) {
798 * Hack, just return, don't pte_clear
800 WARN_ONCE(1, "Linear mapping %lx->%lx overlaps kernel "
801 "text, not splitting\n", addr, end);
811 params.aligned_start = addr & ~(size - 1);
812 params.aligned_end = min_t(unsigned long, aligned_end,
813 (unsigned long)__va(memblock_end_of_DRAM()));
814 stop_machine(stop_machine_change_mapping, ¶ms, NULL);
818 pte_clear(&init_mm, addr, pte);
821 static void remove_pmd_table(pmd_t *pmd_start, unsigned long addr,
828 pmd = pmd_start + pmd_index(addr);
829 for (; addr < end; addr = next, pmd++) {
830 next = pmd_addr_end(addr, end);
832 if (!pmd_present(*pmd))
835 if (pmd_huge(*pmd)) {
836 split_kernel_mapping(addr, end, PMD_SIZE, (pte_t *)pmd);
840 pte_base = (pte_t *)pmd_page_vaddr(*pmd);
841 remove_pte_table(pte_base, addr, next);
842 free_pte_table(pte_base, pmd);
846 static void remove_pud_table(pud_t *pud_start, unsigned long addr,
853 pud = pud_start + pud_index(addr);
854 for (; addr < end; addr = next, pud++) {
855 next = pud_addr_end(addr, end);
857 if (!pud_present(*pud))
860 if (pud_huge(*pud)) {
861 split_kernel_mapping(addr, end, PUD_SIZE, (pte_t *)pud);
865 pmd_base = (pmd_t *)pud_page_vaddr(*pud);
866 remove_pmd_table(pmd_base, addr, next);
867 free_pmd_table(pmd_base, pud);
871 static void __meminit remove_pagetable(unsigned long start, unsigned long end)
873 unsigned long addr, next;
877 spin_lock(&init_mm.page_table_lock);
879 for (addr = start; addr < end; addr = next) {
880 next = pgd_addr_end(addr, end);
882 pgd = pgd_offset_k(addr);
883 if (!pgd_present(*pgd))
886 if (pgd_huge(*pgd)) {
887 split_kernel_mapping(addr, end, PGDIR_SIZE, (pte_t *)pgd);
891 pud_base = (pud_t *)pgd_page_vaddr(*pgd);
892 remove_pud_table(pud_base, addr, next);
895 spin_unlock(&init_mm.page_table_lock);
896 radix__flush_tlb_kernel_range(start, end);
899 int __meminit radix__create_section_mapping(unsigned long start, unsigned long end, int nid)
901 if (end >= RADIX_VMALLOC_START) {
902 pr_warn("Outside the supported range\n");
906 return create_physical_mapping(start, end, nid);
909 int __meminit radix__remove_section_mapping(unsigned long start, unsigned long end)
911 remove_pagetable(start, end);
914 #endif /* CONFIG_MEMORY_HOTPLUG */
916 #ifdef CONFIG_SPARSEMEM_VMEMMAP
917 static int __map_kernel_page_nid(unsigned long ea, unsigned long pa,
918 pgprot_t flags, unsigned int map_page_size,
921 return __map_kernel_page(ea, pa, flags, map_page_size, nid, 0, 0);
924 int __meminit radix__vmemmap_create_mapping(unsigned long start,
925 unsigned long page_size,
928 /* Create a PTE encoding */
929 unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW;
930 int nid = early_pfn_to_nid(phys >> PAGE_SHIFT);
933 if ((start + page_size) >= RADIX_VMEMMAP_END) {
934 pr_warn("Outside the supported range\n");
938 ret = __map_kernel_page_nid(start, phys, __pgprot(flags), page_size, nid);
944 #ifdef CONFIG_MEMORY_HOTPLUG
945 void __meminit radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
947 remove_pagetable(start, start + page_size);
952 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
954 unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
955 pmd_t *pmdp, unsigned long clr,
960 #ifdef CONFIG_DEBUG_VM
961 WARN_ON(!radix__pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp));
962 assert_spin_locked(pmd_lockptr(mm, pmdp));
965 old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
966 trace_hugepage_update(addr, old, clr, set);
971 pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
977 VM_BUG_ON(address & ~HPAGE_PMD_MASK);
978 VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
979 VM_BUG_ON(pmd_devmap(*pmdp));
981 * khugepaged calls this for normal pmd
986 /*FIXME!! Verify whether we need this kick below */
987 serialize_against_pte_lookup(vma->vm_mm);
989 radix__flush_tlb_collapsed_pmd(vma->vm_mm, address);
995 * For us pgtable_t is pte_t *. Inorder to save the deposisted
996 * page table, we consider the allocated page table as a list
997 * head. On withdraw we need to make sure we zero out the used
998 * list_head memory area.
1000 void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
1003 struct list_head *lh = (struct list_head *) pgtable;
1005 assert_spin_locked(pmd_lockptr(mm, pmdp));
1008 if (!pmd_huge_pte(mm, pmdp))
1011 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
1012 pmd_huge_pte(mm, pmdp) = pgtable;
1015 pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
1019 struct list_head *lh;
1021 assert_spin_locked(pmd_lockptr(mm, pmdp));
1024 pgtable = pmd_huge_pte(mm, pmdp);
1025 lh = (struct list_head *) pgtable;
1027 pmd_huge_pte(mm, pmdp) = NULL;
1029 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
1032 ptep = (pte_t *) pgtable;
1039 pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
1040 unsigned long addr, pmd_t *pmdp)
1045 old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
1046 old_pmd = __pmd(old);
1048 * Serialize against find_current_mm_pte which does lock-less
1049 * lookup in page tables with local interrupts disabled. For huge pages
1050 * it casts pmd_t to pte_t. Since format of pte_t is different from
1051 * pmd_t we want to prevent transit from pmd pointing to page table
1052 * to pmd pointing to huge page (and back) while interrupts are disabled.
1053 * We clear pmd to possibly replace it with page table pointer in
1054 * different code paths. So make sure we wait for the parallel
1055 * find_current_mm_pte to finish.
1057 serialize_against_pte_lookup(mm);
1061 int radix__has_transparent_hugepage(void)
1063 /* For radix 2M at PMD level means thp */
1064 if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
1068 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1070 void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep,
1071 pte_t entry, unsigned long address, int psize)
1073 struct mm_struct *mm = vma->vm_mm;
1074 unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED |
1075 _PAGE_RW | _PAGE_EXEC);
1077 unsigned long change = pte_val(entry) ^ pte_val(*ptep);
1079 * To avoid NMMU hang while relaxing access, we need mark
1080 * the pte invalid in between.
1082 if ((change & _PAGE_RW) && atomic_read(&mm->context.copros) > 0) {
1083 unsigned long old_pte, new_pte;
1085 old_pte = __radix_pte_update(ptep, _PAGE_PRESENT, _PAGE_INVALID);
1089 new_pte = old_pte | set;
1090 radix__flush_tlb_page_psize(mm, address, psize);
1091 __radix_pte_update(ptep, _PAGE_INVALID, new_pte);
1093 __radix_pte_update(ptep, 0, set);
1095 * Book3S does not require a TLB flush when relaxing access
1096 * restrictions when the address space is not attached to a
1097 * NMMU, because the core MMU will reload the pte after taking
1098 * an access fault, which is defined by the architectue.
1101 /* See ptesync comment in radix__set_pte_at */
1104 void radix__ptep_modify_prot_commit(struct vm_area_struct *vma,
1105 unsigned long addr, pte_t *ptep,
1106 pte_t old_pte, pte_t pte)
1108 struct mm_struct *mm = vma->vm_mm;
1111 * To avoid NMMU hang while relaxing access we need to flush the tlb before
1112 * we set the new value. We need to do this only for radix, because hash
1113 * translation does flush when updating the linux pte.
1115 if (is_pte_rw_upgrade(pte_val(old_pte), pte_val(pte)) &&
1116 (atomic_read(&mm->context.copros) > 0))
1117 radix__flush_tlb_page(vma, addr);
1119 set_pte_at(mm, addr, ptep, pte);