1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
4 * {mikejc|engebret}@us.ibm.com
6 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
8 * SMP scalability work:
9 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
14 * PowerPC Hashed Page Table functions
20 #define pr_fmt(fmt) "hash-mmu: " fmt
21 #include <linux/spinlock.h>
22 #include <linux/errno.h>
23 #include <linux/sched/mm.h>
24 #include <linux/proc_fs.h>
25 #include <linux/stat.h>
26 #include <linux/sysctl.h>
27 #include <linux/export.h>
28 #include <linux/ctype.h>
29 #include <linux/cache.h>
30 #include <linux/init.h>
31 #include <linux/signal.h>
32 #include <linux/memblock.h>
33 #include <linux/context_tracking.h>
34 #include <linux/libfdt.h>
35 #include <linux/pkeys.h>
36 #include <linux/hugetlb.h>
37 #include <linux/cpu.h>
38 #include <linux/pgtable.h>
40 #include <asm/debugfs.h>
41 #include <asm/processor.h>
43 #include <asm/mmu_context.h>
45 #include <asm/types.h>
46 #include <linux/uaccess.h>
47 #include <asm/machdep.h>
52 #include <asm/cacheflush.h>
53 #include <asm/cputable.h>
54 #include <asm/sections.h>
55 #include <asm/copro.h>
57 #include <asm/code-patching.h>
58 #include <asm/fadump.h>
59 #include <asm/firmware.h>
61 #include <asm/trace.h>
63 #include <asm/pte-walk.h>
64 #include <asm/asm-prototypes.h>
65 #include <asm/ultravisor.h>
67 #include <mm/mmu_decl.h>
73 #define DBG(fmt...) udbg_printf(fmt)
79 #define DBG_LOW(fmt...) udbg_printf(fmt)
81 #define DBG_LOW(fmt...)
89 * Note: pte --> Linux PTE
90 * HPTE --> PowerPC Hashed Page Table Entry
93 * htab_initialize is called with the MMU off (of course), but
94 * the kernel has been copied down to zero so it can directly
95 * reference global data. At this point it is very difficult
96 * to print debug info.
100 static unsigned long _SDR1;
101 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
102 EXPORT_SYMBOL_GPL(mmu_psize_defs);
104 u8 hpte_page_sizes[1 << LP_BITS];
105 EXPORT_SYMBOL_GPL(hpte_page_sizes);
107 struct hash_pte *htab_address;
108 unsigned long htab_size_bytes;
109 unsigned long htab_hash_mask;
110 EXPORT_SYMBOL_GPL(htab_hash_mask);
111 int mmu_linear_psize = MMU_PAGE_4K;
112 EXPORT_SYMBOL_GPL(mmu_linear_psize);
113 int mmu_virtual_psize = MMU_PAGE_4K;
114 int mmu_vmalloc_psize = MMU_PAGE_4K;
115 #ifdef CONFIG_SPARSEMEM_VMEMMAP
116 int mmu_vmemmap_psize = MMU_PAGE_4K;
118 int mmu_io_psize = MMU_PAGE_4K;
119 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
120 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
121 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
122 u16 mmu_slb_size = 64;
123 EXPORT_SYMBOL_GPL(mmu_slb_size);
124 #ifdef CONFIG_PPC_64K_PAGES
125 int mmu_ci_restrictions;
127 #ifdef CONFIG_DEBUG_PAGEALLOC
128 static u8 *linear_map_hash_slots;
129 static unsigned long linear_map_hash_count;
130 static DEFINE_SPINLOCK(linear_map_hash_lock);
131 #endif /* CONFIG_DEBUG_PAGEALLOC */
132 struct mmu_hash_ops mmu_hash_ops;
133 EXPORT_SYMBOL(mmu_hash_ops);
136 * These are definitions of page sizes arrays to be used when none
137 * is provided by the firmware.
141 * Fallback (4k pages only)
143 static struct mmu_psize_def mmu_psize_defaults[] = {
147 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
154 * POWER4, GPUL, POWER5
156 * Support for 16Mb large pages
158 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
162 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
169 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
170 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
177 * 'R' and 'C' update notes:
178 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
179 * create writeable HPTEs without C set, because the hcall H_PROTECT
180 * that we use in that case will not update C
181 * - The above is however not a problem, because we also don't do that
182 * fancy "no flush" variant of eviction and we use H_REMOVE which will
183 * do the right thing and thus we don't have the race I described earlier
185 * - Under bare metal, we do have the race, so we need R and C set
186 * - We make sure R is always set and never lost
187 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
189 unsigned long htab_convert_pte_flags(unsigned long pteflags)
191 unsigned long rflags = 0;
193 /* _PAGE_EXEC -> NOEXEC */
194 if ((pteflags & _PAGE_EXEC) == 0)
198 * Linux uses slb key 0 for kernel and 1 for user.
199 * kernel RW areas are mapped with PPP=0b000
200 * User area is mapped with PPP=0b010 for read/write
201 * or PPP=0b011 for read-only (including writeable but clean pages).
203 if (pteflags & _PAGE_PRIVILEGED) {
205 * Kernel read only mapped with ppp bits 0b110
207 if (!(pteflags & _PAGE_WRITE)) {
208 if (mmu_has_feature(MMU_FTR_KERNEL_RO))
209 rflags |= (HPTE_R_PP0 | 0x2);
214 if (pteflags & _PAGE_RWX)
216 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
220 * We can't allow hardware to update hpte bits. Hence always
221 * set 'R' bit and set 'C' if it is a write fault
225 if (pteflags & _PAGE_DIRTY)
231 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
233 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
234 rflags |= (HPTE_R_I | HPTE_R_G);
235 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
236 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
239 * Add memory coherence if cache inhibited is not set
243 rflags |= pte_to_hpte_pkey_bits(pteflags);
247 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
248 unsigned long pstart, unsigned long prot,
249 int psize, int ssize)
251 unsigned long vaddr, paddr;
252 unsigned int step, shift;
255 shift = mmu_psize_defs[psize].shift;
258 prot = htab_convert_pte_flags(prot);
260 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
261 vstart, vend, pstart, prot, psize, ssize);
263 for (vaddr = vstart, paddr = pstart; vaddr < vend;
264 vaddr += step, paddr += step) {
265 unsigned long hash, hpteg;
266 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
267 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
268 unsigned long tprot = prot;
269 bool secondary_hash = false;
272 * If we hit a bad address return error.
276 /* Make kernel text executable */
277 if (overlaps_kernel_text(vaddr, vaddr + step))
281 * If relocatable, check if it overlaps interrupt vectors that
282 * are copied down to real 0. For relocatable kernel
283 * (e.g. kdump case) we copy interrupt vectors down to real
284 * address 0. Mark that region as executable. This is
285 * because on p8 system with relocation on exception feature
286 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
287 * in order to execute the interrupt handlers in virtual
288 * mode the vector region need to be marked as executable.
290 if ((PHYSICAL_START > MEMORY_START) &&
291 overlaps_interrupt_vector_text(vaddr, vaddr + step))
294 hash = hpt_hash(vpn, shift, ssize);
295 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
297 BUG_ON(!mmu_hash_ops.hpte_insert);
299 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
300 HPTE_V_BOLTED, psize, psize,
304 * Try to to keep bolted entries in primary.
305 * Remove non bolted entries and try insert again
307 ret = mmu_hash_ops.hpte_remove(hpteg);
309 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
310 HPTE_V_BOLTED, psize, psize,
312 if (ret == -1 && !secondary_hash) {
313 secondary_hash = true;
314 hpteg = ((~hash & htab_hash_mask) * HPTES_PER_GROUP);
323 #ifdef CONFIG_DEBUG_PAGEALLOC
324 if (debug_pagealloc_enabled() &&
325 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
326 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
327 #endif /* CONFIG_DEBUG_PAGEALLOC */
329 return ret < 0 ? ret : 0;
332 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
333 int psize, int ssize)
336 unsigned int step, shift;
340 shift = mmu_psize_defs[psize].shift;
343 if (!mmu_hash_ops.hpte_removebolted)
346 for (vaddr = vstart; vaddr < vend; vaddr += step) {
347 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
359 static bool disable_1tb_segments = false;
361 static int __init parse_disable_1tb_segments(char *p)
363 disable_1tb_segments = true;
366 early_param("disable_1tb_segments", parse_disable_1tb_segments);
368 static int __init htab_dt_scan_seg_sizes(unsigned long node,
369 const char *uname, int depth,
372 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
376 /* We are scanning "cpu" nodes only */
377 if (type == NULL || strcmp(type, "cpu") != 0)
380 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
383 for (; size >= 4; size -= 4, ++prop) {
384 if (be32_to_cpu(prop[0]) == 40) {
385 DBG("1T segment support detected\n");
387 if (disable_1tb_segments) {
388 DBG("1T segments disabled by command line\n");
392 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
396 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
400 static int __init get_idx_from_shift(unsigned int shift)
424 static int __init htab_dt_scan_page_sizes(unsigned long node,
425 const char *uname, int depth,
428 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
432 /* We are scanning "cpu" nodes only */
433 if (type == NULL || strcmp(type, "cpu") != 0)
436 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
440 pr_info("Page sizes from device-tree:\n");
442 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
444 unsigned int base_shift = be32_to_cpu(prop[0]);
445 unsigned int slbenc = be32_to_cpu(prop[1]);
446 unsigned int lpnum = be32_to_cpu(prop[2]);
447 struct mmu_psize_def *def;
450 size -= 3; prop += 3;
451 base_idx = get_idx_from_shift(base_shift);
453 /* skip the pte encoding also */
454 prop += lpnum * 2; size -= lpnum * 2;
457 def = &mmu_psize_defs[base_idx];
458 if (base_idx == MMU_PAGE_16M)
459 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
461 def->shift = base_shift;
462 if (base_shift <= 23)
465 def->avpnm = (1 << (base_shift - 23)) - 1;
468 * We don't know for sure what's up with tlbiel, so
469 * for now we only set it for 4K and 64K pages
471 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
476 while (size > 0 && lpnum) {
477 unsigned int shift = be32_to_cpu(prop[0]);
478 int penc = be32_to_cpu(prop[1]);
480 prop += 2; size -= 2;
483 idx = get_idx_from_shift(shift);
488 pr_err("Invalid penc for base_shift=%d "
489 "shift=%d\n", base_shift, shift);
491 def->penc[idx] = penc;
492 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
493 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
494 base_shift, shift, def->sllp,
495 def->avpnm, def->tlbiel, def->penc[idx]);
502 #ifdef CONFIG_HUGETLB_PAGE
504 * Scan for 16G memory blocks that have been set aside for huge pages
505 * and reserve those blocks for 16G huge pages.
507 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
508 const char *uname, int depth,
510 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
511 const __be64 *addr_prop;
512 const __be32 *page_count_prop;
513 unsigned int expected_pages;
514 long unsigned int phys_addr;
515 long unsigned int block_size;
517 /* We are scanning "memory" nodes only */
518 if (type == NULL || strcmp(type, "memory") != 0)
522 * This property is the log base 2 of the number of virtual pages that
523 * will represent this memory block.
525 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
526 if (page_count_prop == NULL)
528 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
529 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
530 if (addr_prop == NULL)
532 phys_addr = be64_to_cpu(addr_prop[0]);
533 block_size = be64_to_cpu(addr_prop[1]);
534 if (block_size != (16 * GB))
536 printk(KERN_INFO "Huge page(16GB) memory: "
537 "addr = 0x%lX size = 0x%lX pages = %d\n",
538 phys_addr, block_size, expected_pages);
539 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
540 memblock_reserve(phys_addr, block_size * expected_pages);
541 pseries_add_gpage(phys_addr, block_size, expected_pages);
545 #endif /* CONFIG_HUGETLB_PAGE */
547 static void mmu_psize_set_default_penc(void)
550 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
551 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
552 mmu_psize_defs[bpsize].penc[apsize] = -1;
555 #ifdef CONFIG_PPC_64K_PAGES
557 static bool might_have_hea(void)
560 * The HEA ethernet adapter requires awareness of the
561 * GX bus. Without that awareness we can easily assume
562 * we will never see an HEA ethernet device.
564 #ifdef CONFIG_IBMEBUS
565 return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
566 firmware_has_feature(FW_FEATURE_SPLPAR);
572 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
574 static void __init htab_scan_page_sizes(void)
578 /* se the invalid penc to -1 */
579 mmu_psize_set_default_penc();
581 /* Default to 4K pages only */
582 memcpy(mmu_psize_defs, mmu_psize_defaults,
583 sizeof(mmu_psize_defaults));
586 * Try to find the available page sizes in the device-tree
588 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
589 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
591 * Nothing in the device-tree, but the CPU supports 16M pages,
592 * so let's fallback on a known size list for 16M capable CPUs.
594 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
595 sizeof(mmu_psize_defaults_gp));
598 #ifdef CONFIG_HUGETLB_PAGE
599 if (!hugetlb_disabled && !early_radix_enabled() ) {
600 /* Reserve 16G huge page memory sections for huge pages */
601 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
603 #endif /* CONFIG_HUGETLB_PAGE */
607 * Fill in the hpte_page_sizes[] array.
608 * We go through the mmu_psize_defs[] array looking for all the
609 * supported base/actual page size combinations. Each combination
610 * has a unique pagesize encoding (penc) value in the low bits of
611 * the LP field of the HPTE. For actual page sizes less than 1MB,
612 * some of the upper LP bits are used for RPN bits, meaning that
613 * we need to fill in several entries in hpte_page_sizes[].
615 * In diagrammatic form, with r = RPN bits and z = page size bits:
616 * PTE LP actual page size
623 * The zzzz bits are implementation-specific but are chosen so that
624 * no encoding for a larger page size uses the same value in its
625 * low-order N bits as the encoding for the 2^(12+N) byte page size
628 static void init_hpte_page_sizes(void)
631 long int shift, penc;
633 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
634 if (!mmu_psize_defs[bp].shift)
635 continue; /* not a supported page size */
636 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
637 penc = mmu_psize_defs[bp].penc[ap];
638 if (penc == -1 || !mmu_psize_defs[ap].shift)
640 shift = mmu_psize_defs[ap].shift - LP_SHIFT;
642 continue; /* should never happen */
644 * For page sizes less than 1MB, this loop
645 * replicates the entry for all possible values
648 while (penc < (1 << LP_BITS)) {
649 hpte_page_sizes[penc] = (ap << 4) | bp;
656 static void __init htab_init_page_sizes(void)
659 init_hpte_page_sizes();
661 if (!debug_pagealloc_enabled()) {
663 * Pick a size for the linear mapping. Currently, we only
664 * support 16M, 1M and 4K which is the default
666 if (IS_ENABLED(CONFIG_STRICT_KERNEL_RWX) &&
667 (unsigned long)_stext % 0x1000000) {
668 if (mmu_psize_defs[MMU_PAGE_16M].shift)
669 pr_warn("Kernel not 16M aligned, disabling 16M linear map alignment\n");
673 if (mmu_psize_defs[MMU_PAGE_16M].shift && aligned)
674 mmu_linear_psize = MMU_PAGE_16M;
675 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
676 mmu_linear_psize = MMU_PAGE_1M;
679 #ifdef CONFIG_PPC_64K_PAGES
681 * Pick a size for the ordinary pages. Default is 4K, we support
682 * 64K for user mappings and vmalloc if supported by the processor.
683 * We only use 64k for ioremap if the processor
684 * (and firmware) support cache-inhibited large pages.
685 * If not, we use 4k and set mmu_ci_restrictions so that
686 * hash_page knows to switch processes that use cache-inhibited
687 * mappings to 4k pages.
689 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
690 mmu_virtual_psize = MMU_PAGE_64K;
691 mmu_vmalloc_psize = MMU_PAGE_64K;
692 if (mmu_linear_psize == MMU_PAGE_4K)
693 mmu_linear_psize = MMU_PAGE_64K;
694 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
696 * When running on pSeries using 64k pages for ioremap
697 * would stop us accessing the HEA ethernet. So if we
698 * have the chance of ever seeing one, stay at 4k.
700 if (!might_have_hea())
701 mmu_io_psize = MMU_PAGE_64K;
703 mmu_ci_restrictions = 1;
705 #endif /* CONFIG_PPC_64K_PAGES */
707 #ifdef CONFIG_SPARSEMEM_VMEMMAP
709 * We try to use 16M pages for vmemmap if that is supported
710 * and we have at least 1G of RAM at boot
712 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
713 memblock_phys_mem_size() >= 0x40000000)
714 mmu_vmemmap_psize = MMU_PAGE_16M;
716 mmu_vmemmap_psize = mmu_virtual_psize;
717 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
719 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
720 "virtual = %d, io = %d"
721 #ifdef CONFIG_SPARSEMEM_VMEMMAP
725 mmu_psize_defs[mmu_linear_psize].shift,
726 mmu_psize_defs[mmu_virtual_psize].shift,
727 mmu_psize_defs[mmu_io_psize].shift
728 #ifdef CONFIG_SPARSEMEM_VMEMMAP
729 ,mmu_psize_defs[mmu_vmemmap_psize].shift
734 static int __init htab_dt_scan_pftsize(unsigned long node,
735 const char *uname, int depth,
738 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
741 /* We are scanning "cpu" nodes only */
742 if (type == NULL || strcmp(type, "cpu") != 0)
745 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
747 /* pft_size[0] is the NUMA CEC cookie */
748 ppc64_pft_size = be32_to_cpu(prop[1]);
754 unsigned htab_shift_for_mem_size(unsigned long mem_size)
756 unsigned memshift = __ilog2(mem_size);
757 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
760 /* round mem_size up to next power of 2 */
761 if ((1UL << memshift) < mem_size)
764 /* aim for 2 pages / pteg */
765 pteg_shift = memshift - (pshift + 1);
768 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
769 * size permitted by the architecture.
771 return max(pteg_shift + 7, 18U);
774 static unsigned long __init htab_get_table_size(void)
777 * If hash size isn't already provided by the platform, we try to
778 * retrieve it from the device-tree. If it's not there neither, we
779 * calculate it now based on the total RAM size
781 if (ppc64_pft_size == 0)
782 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
784 return 1UL << ppc64_pft_size;
786 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
789 #ifdef CONFIG_MEMORY_HOTPLUG
790 static int resize_hpt_for_hotplug(unsigned long new_mem_size)
792 unsigned target_hpt_shift;
794 if (!mmu_hash_ops.resize_hpt)
797 target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
800 * To avoid lots of HPT resizes if memory size is fluctuating
801 * across a boundary, we deliberately have some hysterisis
802 * here: we immediately increase the HPT size if the target
803 * shift exceeds the current shift, but we won't attempt to
804 * reduce unless the target shift is at least 2 below the
807 if (target_hpt_shift > ppc64_pft_size ||
808 target_hpt_shift < ppc64_pft_size - 1)
809 return mmu_hash_ops.resize_hpt(target_hpt_shift);
814 int hash__create_section_mapping(unsigned long start, unsigned long end,
815 int nid, pgprot_t prot)
819 if (end >= H_VMALLOC_START) {
820 pr_warn("Outside the supported range\n");
824 resize_hpt_for_hotplug(memblock_phys_mem_size());
826 rc = htab_bolt_mapping(start, end, __pa(start),
827 pgprot_val(prot), mmu_linear_psize,
831 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
833 BUG_ON(rc2 && (rc2 != -ENOENT));
838 int hash__remove_section_mapping(unsigned long start, unsigned long end)
840 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
844 if (resize_hpt_for_hotplug(memblock_phys_mem_size()) == -ENOSPC)
845 pr_warn("Hash collision while resizing HPT\n");
849 #endif /* CONFIG_MEMORY_HOTPLUG */
851 static void __init hash_init_partition_table(phys_addr_t hash_table,
852 unsigned long htab_size)
854 mmu_partition_table_init();
857 * PS field (VRMA page size) is not used for LPID 0, hence set to 0.
858 * For now, UPRT is 0 and we have no segment table.
860 htab_size = __ilog2(htab_size) - 18;
861 mmu_partition_table_set_entry(0, hash_table | htab_size, 0, false);
862 pr_info("Partition table %p\n", partition_tb);
865 static void __init htab_initialize(void)
868 unsigned long pteg_count;
870 unsigned long base = 0, size = 0;
871 struct memblock_region *reg;
873 DBG(" -> htab_initialize()\n");
875 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
876 mmu_kernel_ssize = MMU_SEGSIZE_1T;
877 mmu_highuser_ssize = MMU_SEGSIZE_1T;
878 printk(KERN_INFO "Using 1TB segments\n");
881 if (stress_slb_enabled)
882 static_branch_enable(&stress_slb_key);
885 * Calculate the required size of the htab. We want the number of
886 * PTEGs to equal one half the number of real pages.
888 htab_size_bytes = htab_get_table_size();
889 pteg_count = htab_size_bytes >> 7;
891 htab_hash_mask = pteg_count - 1;
893 if (firmware_has_feature(FW_FEATURE_LPAR) ||
894 firmware_has_feature(FW_FEATURE_PS3_LV1)) {
895 /* Using a hypervisor which owns the htab */
898 #ifdef CONFIG_FA_DUMP
900 * If firmware assisted dump is active firmware preserves
901 * the contents of htab along with entire partition memory.
902 * Clear the htab if firmware assisted dump is active so
903 * that we dont end up using old mappings.
905 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
906 mmu_hash_ops.hpte_clear_all();
909 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
911 #ifdef CONFIG_PPC_CELL
913 * Cell may require the hash table down low when using the
914 * Axon IOMMU in order to fit the dynamic region over it, see
915 * comments in cell/iommu.c
917 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
919 pr_info("Hash table forced below 2G for Axon IOMMU\n");
921 #endif /* CONFIG_PPC_CELL */
923 table = memblock_phys_alloc_range(htab_size_bytes,
927 panic("ERROR: Failed to allocate %pa bytes below %pa\n",
928 &htab_size_bytes, &limit);
930 DBG("Hash table allocated at %lx, size: %lx\n", table,
933 htab_address = __va(table);
935 /* htab absolute addr + encoded htabsize */
936 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
938 /* Initialize the HPT with no entries */
939 memset((void *)table, 0, htab_size_bytes);
941 if (!cpu_has_feature(CPU_FTR_ARCH_300))
943 mtspr(SPRN_SDR1, _SDR1);
945 hash_init_partition_table(table, htab_size_bytes);
948 prot = pgprot_val(PAGE_KERNEL);
950 #ifdef CONFIG_DEBUG_PAGEALLOC
951 if (debug_pagealloc_enabled()) {
952 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
953 linear_map_hash_slots = memblock_alloc_try_nid(
954 linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT,
955 ppc64_rma_size, NUMA_NO_NODE);
956 if (!linear_map_hash_slots)
957 panic("%s: Failed to allocate %lu bytes max_addr=%pa\n",
958 __func__, linear_map_hash_count, &ppc64_rma_size);
960 #endif /* CONFIG_DEBUG_PAGEALLOC */
962 /* create bolted the linear mapping in the hash table */
963 for_each_memblock(memory, reg) {
964 base = (unsigned long)__va(reg->base);
967 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
970 if ((base + size) >= H_VMALLOC_START) {
971 pr_warn("Outside the supported range\n");
975 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
976 prot, mmu_linear_psize, mmu_kernel_ssize));
978 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
981 * If we have a memory_limit and we've allocated TCEs then we need to
982 * explicitly map the TCE area at the top of RAM. We also cope with the
983 * case that the TCEs start below memory_limit.
984 * tce_alloc_start/end are 16MB aligned so the mapping should work
985 * for either 4K or 16MB pages.
987 if (tce_alloc_start) {
988 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
989 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
991 if (base + size >= tce_alloc_start)
992 tce_alloc_start = base + size + 1;
994 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
995 __pa(tce_alloc_start), prot,
996 mmu_linear_psize, mmu_kernel_ssize));
1000 DBG(" <- htab_initialize()\n");
1005 void __init hash__early_init_devtree(void)
1007 /* Initialize segment sizes */
1008 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
1010 /* Initialize page sizes */
1011 htab_scan_page_sizes();
1014 static struct hash_mm_context init_hash_mm_context;
1015 void __init hash__early_init_mmu(void)
1017 #ifndef CONFIG_PPC_64K_PAGES
1019 * We have code in __hash_page_4K() and elsewhere, which assumes it can
1021 * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);
1023 * Where the slot number is between 0-15, and values of 8-15 indicate
1024 * the secondary bucket. For that code to work H_PAGE_F_SECOND and
1025 * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and
1026 * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here
1027 * with a BUILD_BUG_ON().
1029 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3)));
1030 #endif /* CONFIG_PPC_64K_PAGES */
1032 htab_init_page_sizes();
1035 * initialize page table size
1037 __pte_frag_nr = H_PTE_FRAG_NR;
1038 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
1039 __pmd_frag_nr = H_PMD_FRAG_NR;
1040 __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT;
1042 __pte_index_size = H_PTE_INDEX_SIZE;
1043 __pmd_index_size = H_PMD_INDEX_SIZE;
1044 __pud_index_size = H_PUD_INDEX_SIZE;
1045 __pgd_index_size = H_PGD_INDEX_SIZE;
1046 __pud_cache_index = H_PUD_CACHE_INDEX;
1047 __pte_table_size = H_PTE_TABLE_SIZE;
1048 __pmd_table_size = H_PMD_TABLE_SIZE;
1049 __pud_table_size = H_PUD_TABLE_SIZE;
1050 __pgd_table_size = H_PGD_TABLE_SIZE;
1052 * 4k use hugepd format, so for hash set then to
1055 __pmd_val_bits = HASH_PMD_VAL_BITS;
1056 __pud_val_bits = HASH_PUD_VAL_BITS;
1057 __pgd_val_bits = HASH_PGD_VAL_BITS;
1059 __kernel_virt_start = H_KERN_VIRT_START;
1060 __vmalloc_start = H_VMALLOC_START;
1061 __vmalloc_end = H_VMALLOC_END;
1062 __kernel_io_start = H_KERN_IO_START;
1063 __kernel_io_end = H_KERN_IO_END;
1064 vmemmap = (struct page *)H_VMEMMAP_START;
1065 ioremap_bot = IOREMAP_BASE;
1068 pci_io_base = ISA_IO_BASE;
1071 /* Select appropriate backend */
1072 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1073 ps3_early_mm_init();
1074 else if (firmware_has_feature(FW_FEATURE_LPAR))
1075 hpte_init_pseries();
1076 else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1079 if (!mmu_hash_ops.hpte_insert)
1080 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1083 * Initialize the MMU Hash table and create the linear mapping
1084 * of memory. Has to be done before SLB initialization as this is
1085 * currently where the page size encoding is obtained.
1089 init_mm.context.hash_context = &init_hash_mm_context;
1090 mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT);
1092 pr_info("Initializing hash mmu with SLB\n");
1093 /* Initialize SLB management */
1096 if (cpu_has_feature(CPU_FTR_ARCH_206)
1097 && cpu_has_feature(CPU_FTR_HVMODE))
1102 void hash__early_init_mmu_secondary(void)
1104 /* Initialize hash table for that CPU */
1105 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1107 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1108 mtspr(SPRN_SDR1, _SDR1);
1110 set_ptcr_when_no_uv(__pa(partition_tb) |
1111 (PATB_SIZE_SHIFT - 12));
1113 /* Initialize SLB */
1116 if (cpu_has_feature(CPU_FTR_ARCH_206)
1117 && cpu_has_feature(CPU_FTR_HVMODE))
1120 #ifdef CONFIG_PPC_MEM_KEYS
1121 if (mmu_has_feature(MMU_FTR_PKEY))
1122 mtspr(SPRN_UAMOR, default_uamor);
1125 #endif /* CONFIG_SMP */
1128 * Called by asm hashtable.S for doing lazy icache flush
1130 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1134 if (!pfn_valid(pte_pfn(pte)))
1137 page = pte_page(pte);
1140 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1141 if (trap == 0x400) {
1142 flush_dcache_icache_page(page);
1143 set_bit(PG_arch_1, &page->flags);
1150 #ifdef CONFIG_PPC_MM_SLICES
1151 static unsigned int get_paca_psize(unsigned long addr)
1153 unsigned char *psizes;
1154 unsigned long index, mask_index;
1156 if (addr < SLICE_LOW_TOP) {
1157 psizes = get_paca()->mm_ctx_low_slices_psize;
1158 index = GET_LOW_SLICE_INDEX(addr);
1160 psizes = get_paca()->mm_ctx_high_slices_psize;
1161 index = GET_HIGH_SLICE_INDEX(addr);
1163 mask_index = index & 0x1;
1164 return (psizes[index >> 1] >> (mask_index * 4)) & 0xF;
1168 unsigned int get_paca_psize(unsigned long addr)
1170 return get_paca()->mm_ctx_user_psize;
1175 * Demote a segment to using 4k pages.
1176 * For now this makes the whole process use 4k pages.
1178 #ifdef CONFIG_PPC_64K_PAGES
1179 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1181 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1183 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1184 copro_flush_all_slbs(mm);
1185 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1187 copy_mm_to_paca(mm);
1188 slb_flush_and_restore_bolted();
1191 #endif /* CONFIG_PPC_64K_PAGES */
1193 #ifdef CONFIG_PPC_SUBPAGE_PROT
1195 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1196 * Userspace sets the subpage permissions using the subpage_prot system call.
1198 * Result is 0: full permissions, _PAGE_RW: read-only,
1199 * _PAGE_RWX: no access.
1201 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1203 struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context);
1210 if (ea >= spt->maxaddr)
1212 if (ea < 0x100000000UL) {
1213 /* addresses below 4GB use spt->low_prot */
1214 sbpm = spt->low_prot;
1216 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1220 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1223 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1225 /* extract 2-bit bitfield for this 4k subpage */
1226 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1229 * 0 -> full premission
1232 * We return the flag that need to be cleared.
1234 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1238 #else /* CONFIG_PPC_SUBPAGE_PROT */
1239 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1245 void hash_failure_debug(unsigned long ea, unsigned long access,
1246 unsigned long vsid, unsigned long trap,
1247 int ssize, int psize, int lpsize, unsigned long pte)
1249 if (!printk_ratelimit())
1251 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1252 ea, access, current->comm);
1253 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1254 trap, vsid, ssize, psize, lpsize, pte);
1257 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1258 int psize, bool user_region)
1261 if (psize != get_paca_psize(ea)) {
1262 copy_mm_to_paca(mm);
1263 slb_flush_and_restore_bolted();
1265 } else if (get_paca()->vmalloc_sllp !=
1266 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1267 get_paca()->vmalloc_sllp =
1268 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1269 slb_vmalloc_update();
1276 * 1 - normal page fault
1277 * -1 - critical hash insertion error
1278 * -2 - access not permitted by subpage protection mechanism
1280 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1281 unsigned long access, unsigned long trap,
1282 unsigned long flags)
1285 enum ctx_state prev_state = exception_enter();
1290 int rc, user_region = 0;
1293 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1295 trace_hash_fault(ea, access, trap);
1297 /* Get region & vsid */
1298 switch (get_region_id(ea)) {
1299 case USER_REGION_ID:
1302 DBG_LOW(" user region with no mm !\n");
1306 psize = get_slice_psize(mm, ea);
1307 ssize = user_segment_size(ea);
1308 vsid = get_user_vsid(&mm->context, ea, ssize);
1310 case VMALLOC_REGION_ID:
1311 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1312 psize = mmu_vmalloc_psize;
1313 ssize = mmu_kernel_ssize;
1317 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1318 psize = mmu_io_psize;
1319 ssize = mmu_kernel_ssize;
1324 * Send the problem up to do_page_fault()
1329 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1333 DBG_LOW("Bad address!\n");
1339 if (pgdir == NULL) {
1344 /* Check CPU locality */
1345 if (user_region && mm_is_thread_local(mm))
1346 flags |= HPTE_LOCAL_UPDATE;
1348 #ifndef CONFIG_PPC_64K_PAGES
1350 * If we use 4K pages and our psize is not 4K, then we might
1351 * be hitting a special driver mapping, and need to align the
1352 * address before we fetch the PTE.
1354 * It could also be a hugepage mapping, in which case this is
1355 * not necessary, but it's not harmful, either.
1357 if (psize != MMU_PAGE_4K)
1358 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1359 #endif /* CONFIG_PPC_64K_PAGES */
1361 /* Get PTE and page size from page tables */
1362 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1363 if (ptep == NULL || !pte_present(*ptep)) {
1364 DBG_LOW(" no PTE !\n");
1370 * Add _PAGE_PRESENT to the required access perm. If there are parallel
1371 * updates to the pte that can possibly clear _PAGE_PTE, catch that too.
1373 * We can safely use the return pte address in rest of the function
1374 * because we do set H_PAGE_BUSY which prevents further updates to pte
1375 * from generic code.
1377 access |= _PAGE_PRESENT | _PAGE_PTE;
1380 * Pre-check access permissions (will be re-checked atomically
1381 * in __hash_page_XX but this pre-check is a fast path
1383 if (!check_pte_access(access, pte_val(*ptep))) {
1384 DBG_LOW(" no access !\n");
1391 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1392 trap, flags, ssize, psize);
1393 #ifdef CONFIG_HUGETLB_PAGE
1395 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1396 flags, ssize, hugeshift, psize);
1400 * if we have hugeshift, and is not transhuge with
1401 * hugetlb disabled, something is really wrong.
1407 if (current->mm == mm)
1408 check_paca_psize(ea, mm, psize, user_region);
1413 #ifndef CONFIG_PPC_64K_PAGES
1414 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1416 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1417 pte_val(*(ptep + PTRS_PER_PTE)));
1419 /* Do actual hashing */
1420 #ifdef CONFIG_PPC_64K_PAGES
1421 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1422 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1423 demote_segment_4k(mm, ea);
1424 psize = MMU_PAGE_4K;
1428 * If this PTE is non-cacheable and we have restrictions on
1429 * using non cacheable large pages, then we switch to 4k
1431 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1433 demote_segment_4k(mm, ea);
1434 psize = MMU_PAGE_4K;
1435 } else if (ea < VMALLOC_END) {
1437 * some driver did a non-cacheable mapping
1438 * in vmalloc space, so switch vmalloc
1441 printk(KERN_ALERT "Reducing vmalloc segment "
1442 "to 4kB pages because of "
1443 "non-cacheable mapping\n");
1444 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1445 copro_flush_all_slbs(mm);
1449 #endif /* CONFIG_PPC_64K_PAGES */
1451 if (current->mm == mm)
1452 check_paca_psize(ea, mm, psize, user_region);
1454 #ifdef CONFIG_PPC_64K_PAGES
1455 if (psize == MMU_PAGE_64K)
1456 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1459 #endif /* CONFIG_PPC_64K_PAGES */
1461 int spp = subpage_protection(mm, ea);
1465 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1470 * Dump some info in case of hash insertion failure, they should
1471 * never happen so it is really useful to know if/when they do
1474 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1475 psize, pte_val(*ptep));
1476 #ifndef CONFIG_PPC_64K_PAGES
1477 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1479 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1480 pte_val(*(ptep + PTRS_PER_PTE)));
1482 DBG_LOW(" -> rc=%d\n", rc);
1485 exception_exit(prev_state);
1488 EXPORT_SYMBOL_GPL(hash_page_mm);
1490 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1491 unsigned long dsisr)
1493 unsigned long flags = 0;
1494 struct mm_struct *mm = current->mm;
1496 if ((get_region_id(ea) == VMALLOC_REGION_ID) ||
1497 (get_region_id(ea) == IO_REGION_ID))
1500 if (dsisr & DSISR_NOHPTE)
1501 flags |= HPTE_NOHPTE_UPDATE;
1503 return hash_page_mm(mm, ea, access, trap, flags);
1505 EXPORT_SYMBOL_GPL(hash_page);
1507 int __hash_page(unsigned long trap, unsigned long ea, unsigned long dsisr,
1510 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1511 unsigned long flags = 0;
1512 struct mm_struct *mm = current->mm;
1513 unsigned int region_id = get_region_id(ea);
1515 if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID))
1518 if (dsisr & DSISR_NOHPTE)
1519 flags |= HPTE_NOHPTE_UPDATE;
1521 if (dsisr & DSISR_ISSTORE)
1522 access |= _PAGE_WRITE;
1524 * We set _PAGE_PRIVILEGED only when
1525 * kernel mode access kernel space.
1527 * _PAGE_PRIVILEGED is NOT set
1528 * 1) when kernel mode access user space
1529 * 2) user space access kernel space.
1531 access |= _PAGE_PRIVILEGED;
1532 if ((msr & MSR_PR) || (region_id == USER_REGION_ID))
1533 access &= ~_PAGE_PRIVILEGED;
1536 access |= _PAGE_EXEC;
1538 return hash_page_mm(mm, ea, access, trap, flags);
1541 #ifdef CONFIG_PPC_MM_SLICES
1542 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1544 int psize = get_slice_psize(mm, ea);
1546 /* We only prefault standard pages for now */
1547 if (unlikely(psize != mm_ctx_user_psize(&mm->context)))
1551 * Don't prefault if subpage protection is enabled for the EA.
1553 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1559 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1565 static void hash_preload(struct mm_struct *mm, pte_t *ptep, unsigned long ea,
1566 bool is_exec, unsigned long trap)
1570 int rc, ssize, update_flags = 0;
1571 unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0);
1572 unsigned long flags;
1574 BUG_ON(get_region_id(ea) != USER_REGION_ID);
1576 if (!should_hash_preload(mm, ea))
1579 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1580 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1582 /* Get Linux PTE if available */
1588 ssize = user_segment_size(ea);
1589 vsid = get_user_vsid(&mm->context, ea, ssize);
1593 #ifdef CONFIG_PPC_64K_PAGES
1594 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1595 * a 64K kernel), then we don't preload, hash_page() will take
1596 * care of it once we actually try to access the page.
1597 * That way we don't have to duplicate all of the logic for segment
1598 * page size demotion here
1599 * Called with PTL held, hence can be sure the value won't change in
1602 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1604 #endif /* CONFIG_PPC_64K_PAGES */
1607 * __hash_page_* must run with interrupts off, as it sets the
1608 * H_PAGE_BUSY bit. It's possible for perf interrupts to hit at any
1609 * time and may take a hash fault reading the user stack, see
1610 * read_user_stack_slow() in the powerpc/perf code.
1612 * If that takes a hash fault on the same page as we lock here, it
1613 * will bail out when seeing H_PAGE_BUSY set, and retry the access
1614 * leading to an infinite loop.
1616 * Disabling interrupts here does not prevent perf interrupts, but it
1617 * will prevent them taking hash faults (see the NMI test in
1618 * do_hash_page), then read_user_stack's copy_from_user_nofault will
1619 * fail and perf will fall back to read_user_stack_slow(), which
1620 * walks the Linux page tables.
1622 * Interrupts must also be off for the duration of the
1623 * mm_is_thread_local test and update, to prevent preempt running the
1624 * mm on another CPU (XXX: this may be racy vs kthread_use_mm).
1626 local_irq_save(flags);
1628 /* Is that local to this CPU ? */
1629 if (mm_is_thread_local(mm))
1630 update_flags |= HPTE_LOCAL_UPDATE;
1633 #ifdef CONFIG_PPC_64K_PAGES
1634 if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K)
1635 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1636 update_flags, ssize);
1638 #endif /* CONFIG_PPC_64K_PAGES */
1639 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1640 ssize, subpage_protection(mm, ea));
1642 /* Dump some info in case of hash insertion failure, they should
1643 * never happen so it is really useful to know if/when they do
1646 hash_failure_debug(ea, access, vsid, trap, ssize,
1647 mm_ctx_user_psize(&mm->context),
1648 mm_ctx_user_psize(&mm->context),
1651 local_irq_restore(flags);
1655 * This is called at the end of handling a user page fault, when the
1656 * fault has been handled by updating a PTE in the linux page tables.
1657 * We use it to preload an HPTE into the hash table corresponding to
1658 * the updated linux PTE.
1660 * This must always be called with the pte lock held.
1662 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
1666 * We don't need to worry about _PAGE_PRESENT here because we are
1667 * called with either mm->page_table_lock held or ptl lock held
1672 if (radix_enabled())
1675 /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
1676 if (!pte_young(*ptep) || address >= TASK_SIZE)
1680 * We try to figure out if we are coming from an instruction
1681 * access fault and pass that down to __hash_page so we avoid
1682 * double-faulting on execution of fresh text. We have to test
1683 * for regs NULL since init will get here first thing at boot.
1685 * We also avoid filling the hash if not coming from a fault.
1688 trap = current->thread.regs ? TRAP(current->thread.regs) : 0UL;
1700 hash_preload(vma->vm_mm, ptep, address, is_exec, trap);
1703 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1704 static inline void tm_flush_hash_page(int local)
1707 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1708 * page back to a block device w/PIO could pick up transactional data
1709 * (bad!) so we force an abort here. Before the sync the page will be
1710 * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1711 * kernel uses a page from userspace without unmapping it first, it may
1712 * see the speculated version.
1714 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1715 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1717 tm_abort(TM_CAUSE_TLBI);
1721 static inline void tm_flush_hash_page(int local)
1727 * Return the global hash slot, corresponding to the given PTE, which contains
1730 unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
1731 int ssize, real_pte_t rpte, unsigned int subpg_index)
1733 unsigned long hash, gslot, hidx;
1735 hash = hpt_hash(vpn, shift, ssize);
1736 hidx = __rpte_to_hidx(rpte, subpg_index);
1737 if (hidx & _PTEIDX_SECONDARY)
1739 gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1740 gslot += hidx & _PTEIDX_GROUP_IX;
1744 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1745 unsigned long flags)
1747 unsigned long index, shift, gslot;
1748 int local = flags & HPTE_LOCAL_UPDATE;
1750 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1751 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1752 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index);
1753 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot);
1755 * We use same base page size and actual psize, because we don't
1756 * use these functions for hugepage
1758 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize,
1760 } pte_iterate_hashed_end();
1762 tm_flush_hash_page(local);
1765 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1766 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1767 pmd_t *pmdp, unsigned int psize, int ssize,
1768 unsigned long flags)
1770 int i, max_hpte_count, valid;
1771 unsigned long s_addr;
1772 unsigned char *hpte_slot_array;
1773 unsigned long hidx, shift, vpn, hash, slot;
1774 int local = flags & HPTE_LOCAL_UPDATE;
1776 s_addr = addr & HPAGE_PMD_MASK;
1777 hpte_slot_array = get_hpte_slot_array(pmdp);
1779 * IF we try to do a HUGE PTE update after a withdraw is done.
1780 * we will find the below NULL. This happens when we do
1783 if (!hpte_slot_array)
1786 if (mmu_hash_ops.hugepage_invalidate) {
1787 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1788 psize, ssize, local);
1792 * No bluk hpte removal support, invalidate each entry
1794 shift = mmu_psize_defs[psize].shift;
1795 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1796 for (i = 0; i < max_hpte_count; i++) {
1798 * 8 bits per each hpte entries
1799 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1801 valid = hpte_valid(hpte_slot_array, i);
1804 hidx = hpte_hash_index(hpte_slot_array, i);
1807 addr = s_addr + (i * (1ul << shift));
1808 vpn = hpt_vpn(addr, vsid, ssize);
1809 hash = hpt_hash(vpn, shift, ssize);
1810 if (hidx & _PTEIDX_SECONDARY)
1813 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1814 slot += hidx & _PTEIDX_GROUP_IX;
1815 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1816 MMU_PAGE_16M, ssize, local);
1819 tm_flush_hash_page(local);
1821 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1823 void flush_hash_range(unsigned long number, int local)
1825 if (mmu_hash_ops.flush_hash_range)
1826 mmu_hash_ops.flush_hash_range(number, local);
1829 struct ppc64_tlb_batch *batch =
1830 this_cpu_ptr(&ppc64_tlb_batch);
1832 for (i = 0; i < number; i++)
1833 flush_hash_page(batch->vpn[i], batch->pte[i],
1834 batch->psize, batch->ssize, local);
1839 * low_hash_fault is called when we the low level hash code failed
1840 * to instert a PTE due to an hypervisor error
1842 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1844 enum ctx_state prev_state = exception_enter();
1846 if (user_mode(regs)) {
1847 #ifdef CONFIG_PPC_SUBPAGE_PROT
1849 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1852 _exception(SIGBUS, regs, BUS_ADRERR, address);
1854 bad_page_fault(regs, address, SIGBUS);
1856 exception_exit(prev_state);
1859 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1860 unsigned long pa, unsigned long rflags,
1861 unsigned long vflags, int psize, int ssize)
1863 unsigned long hpte_group;
1867 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1869 /* Insert into the hash table, primary slot */
1870 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1871 psize, psize, ssize);
1873 /* Primary is full, try the secondary */
1874 if (unlikely(slot == -1)) {
1875 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;
1876 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1877 vflags | HPTE_V_SECONDARY,
1878 psize, psize, ssize);
1881 hpte_group = (hash & htab_hash_mask) *
1884 mmu_hash_ops.hpte_remove(hpte_group);
1892 #ifdef CONFIG_DEBUG_PAGEALLOC
1893 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1896 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1897 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1898 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1901 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1903 /* Don't create HPTE entries for bad address */
1907 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1909 mmu_linear_psize, mmu_kernel_ssize);
1912 spin_lock(&linear_map_hash_lock);
1913 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1914 linear_map_hash_slots[lmi] = ret | 0x80;
1915 spin_unlock(&linear_map_hash_lock);
1918 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1920 unsigned long hash, hidx, slot;
1921 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1922 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1924 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1925 spin_lock(&linear_map_hash_lock);
1926 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1927 hidx = linear_map_hash_slots[lmi] & 0x7f;
1928 linear_map_hash_slots[lmi] = 0;
1929 spin_unlock(&linear_map_hash_lock);
1930 if (hidx & _PTEIDX_SECONDARY)
1932 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1933 slot += hidx & _PTEIDX_GROUP_IX;
1934 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1936 mmu_kernel_ssize, 0);
1939 void __kernel_map_pages(struct page *page, int numpages, int enable)
1941 unsigned long flags, vaddr, lmi;
1944 local_irq_save(flags);
1945 for (i = 0; i < numpages; i++, page++) {
1946 vaddr = (unsigned long)page_address(page);
1947 lmi = __pa(vaddr) >> PAGE_SHIFT;
1948 if (lmi >= linear_map_hash_count)
1951 kernel_map_linear_page(vaddr, lmi);
1953 kernel_unmap_linear_page(vaddr, lmi);
1955 local_irq_restore(flags);
1957 #endif /* CONFIG_DEBUG_PAGEALLOC */
1959 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1960 phys_addr_t first_memblock_size)
1963 * We don't currently support the first MEMBLOCK not mapping 0
1964 * physical on those processors
1966 BUG_ON(first_memblock_base != 0);
1969 * On virtualized systems the first entry is our RMA region aka VRMA,
1970 * non-virtualized 64-bit hash MMU systems don't have a limitation
1971 * on real mode access.
1973 * For guests on platforms before POWER9, we clamp the it limit to 1G
1974 * to avoid some funky things such as RTAS bugs etc...
1976 * On POWER9 we limit to 1TB in case the host erroneously told us that
1977 * the RMA was >1TB. Effective address bits 0:23 are treated as zero
1978 * (meaning the access is aliased to zero i.e. addr = addr % 1TB)
1979 * for virtual real mode addressing and so it doesn't make sense to
1980 * have an area larger than 1TB as it can't be addressed.
1982 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) {
1983 ppc64_rma_size = first_memblock_size;
1984 if (!early_cpu_has_feature(CPU_FTR_ARCH_300))
1985 ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000);
1987 ppc64_rma_size = min_t(u64, ppc64_rma_size,
1988 1UL << SID_SHIFT_1T);
1990 /* Finally limit subsequent allocations */
1991 memblock_set_current_limit(ppc64_rma_size);
1993 ppc64_rma_size = ULONG_MAX;
1997 #ifdef CONFIG_DEBUG_FS
1999 static int hpt_order_get(void *data, u64 *val)
2001 *val = ppc64_pft_size;
2005 static int hpt_order_set(void *data, u64 val)
2009 if (!mmu_hash_ops.resize_hpt)
2013 ret = mmu_hash_ops.resize_hpt(val);
2019 DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
2021 static int __init hash64_debugfs(void)
2023 debugfs_create_file("hpt_order", 0600, powerpc_debugfs_root, NULL,
2027 machine_device_initcall(pseries, hash64_debugfs);
2028 #endif /* CONFIG_DEBUG_FS */
2030 void __init print_system_hash_info(void)
2032 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
2035 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask);