2 * Modifications by Matt Porter (mporter@mvista.com) to support
3 * PPC44x Book E processors.
5 * This file contains the routines for initializing the MMU
6 * on the 4xx series of chips.
9 * Derived from arch/ppc/mm/init.c:
10 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
12 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
13 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
14 * Copyright (C) 1996 Paul Mackerras
16 * Derived from "arch/i386/mm/init.c"
17 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
26 #include <linux/init.h>
28 #include <asm/system.h>
30 #include <asm/cacheflush.h>
34 /* Used by the 44x TLB replacement exception handler.
35 * Just needed it declared someplace.
37 unsigned int tlb_44x_index; /* = 0 */
38 unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
39 int icache_44x_need_flush;
41 unsigned long tlb_47x_boltmap[1024/8];
43 static void __cpuinit ppc44x_update_tlb_hwater(void)
45 extern unsigned int tlb_44x_patch_hwater_D[];
46 extern unsigned int tlb_44x_patch_hwater_I[];
48 /* The TLB miss handlers hard codes the watermark in a cmpli
49 * instruction to improve performances rather than loading it
50 * from the global variable. Thus, we patch the instructions
51 * in the 2 TLB miss handlers when updating the value
53 tlb_44x_patch_hwater_D[0] = (tlb_44x_patch_hwater_D[0] & 0xffff0000) |
55 flush_icache_range((unsigned long)&tlb_44x_patch_hwater_D[0],
56 (unsigned long)&tlb_44x_patch_hwater_D[1]);
57 tlb_44x_patch_hwater_I[0] = (tlb_44x_patch_hwater_I[0] & 0xffff0000) |
59 flush_icache_range((unsigned long)&tlb_44x_patch_hwater_I[0],
60 (unsigned long)&tlb_44x_patch_hwater_I[1]);
64 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
66 static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
68 unsigned int entry = tlb_44x_hwater--;
70 ppc44x_update_tlb_hwater();
80 : "r" (PPC47x_TLB2_S_RWX),
82 : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
85 "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
87 "i" (PPC44x_TLB_PAGEID),
88 "i" (PPC44x_TLB_XLAT),
89 "i" (PPC44x_TLB_ATTRIB));
92 static int __init ppc47x_find_free_bolted(void)
94 unsigned int mmube0 = mfspr(SPRN_MMUBE0);
95 unsigned int mmube1 = mfspr(SPRN_MMUBE1);
97 if (!(mmube0 & MMUBE0_VBE0))
99 if (!(mmube0 & MMUBE0_VBE1))
101 if (!(mmube0 & MMUBE0_VBE2))
103 if (!(mmube1 & MMUBE1_VBE3))
105 if (!(mmube1 & MMUBE1_VBE4))
107 if (!(mmube1 & MMUBE1_VBE5))
112 static void __init ppc47x_update_boltmap(void)
114 unsigned int mmube0 = mfspr(SPRN_MMUBE0);
115 unsigned int mmube1 = mfspr(SPRN_MMUBE1);
117 if (mmube0 & MMUBE0_VBE0)
118 __set_bit((mmube0 >> MMUBE0_IBE0_SHIFT) & 0xff,
120 if (mmube0 & MMUBE0_VBE1)
121 __set_bit((mmube0 >> MMUBE0_IBE1_SHIFT) & 0xff,
123 if (mmube0 & MMUBE0_VBE2)
124 __set_bit((mmube0 >> MMUBE0_IBE2_SHIFT) & 0xff,
126 if (mmube1 & MMUBE1_VBE3)
127 __set_bit((mmube1 >> MMUBE1_IBE3_SHIFT) & 0xff,
129 if (mmube1 & MMUBE1_VBE4)
130 __set_bit((mmube1 >> MMUBE1_IBE4_SHIFT) & 0xff,
132 if (mmube1 & MMUBE1_VBE5)
133 __set_bit((mmube1 >> MMUBE1_IBE5_SHIFT) & 0xff,
138 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 47x type MMU
140 static void __cpuinit ppc47x_pin_tlb(unsigned int virt, unsigned int phys)
145 /* Base rA is HW way select, way 0, bolted bit set */
148 /* Look for a bolted entry slot */
149 bolted = ppc47x_find_free_bolted();
152 /* Insert bolted slot number */
155 pr_debug("256M TLB entry for 0x%08x->0x%08x in bolt slot %d\n",
158 mtspr(SPRN_MMUCR, 0);
160 __asm__ __volatile__(
165 : "r" (PPC47x_TLB2_SW | PPC47x_TLB2_SR |
172 "r" (virt | PPC47x_TLB0_VALID | PPC47x_TLB0_256M),
176 void __init MMU_init_hw(void)
178 /* This is not useful on 47x but won't hurt either */
179 ppc44x_update_tlb_hwater();
181 flush_instruction_cache();
184 unsigned long __init mmu_mapin_ram(unsigned long top)
188 /* Pin in enough TLBs to cover any lowmem not covered by the
189 * initial 256M mapping established in head_44x.S */
190 for (addr = PPC_PIN_SIZE; addr < lowmem_end_addr;
191 addr += PPC_PIN_SIZE) {
192 if (mmu_has_feature(MMU_FTR_TYPE_47x))
193 ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
195 ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
197 if (mmu_has_feature(MMU_FTR_TYPE_47x)) {
198 ppc47x_update_boltmap();
204 printk(KERN_DEBUG "bolted entries: ");
205 for (i = 0; i < 255; i++) {
206 if (test_bit(i, tlb_47x_boltmap))
217 void __cpuinit mmu_init_secondary(int cpu)
221 /* Pin in enough TLBs to cover any lowmem not covered by the
222 * initial 256M mapping established in head_44x.S
224 * WARNING: This is called with only the first 256M of the
225 * linear mapping in the TLB and we can't take faults yet
226 * so beware of what this code uses. It runs off a temporary
227 * stack. current (r2) isn't initialized, smp_processor_id()
228 * will not work, current thread info isn't accessible, ...
230 for (addr = PPC_PIN_SIZE; addr < lowmem_end_addr;
231 addr += PPC_PIN_SIZE) {
232 if (mmu_has_feature(MMU_FTR_TYPE_47x))
233 ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
235 ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
238 #endif /* CONFIG_SMP */