4 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/kprobes.h>
13 #include <linux/ptrace.h>
14 #include <linux/prefetch.h>
15 #include <asm/sstep.h>
16 #include <asm/processor.h>
17 #include <linux/uaccess.h>
18 #include <asm/cpu_has_feature.h>
19 #include <asm/cputable.h>
21 extern char system_call_common[];
24 /* Bits in SRR1 that are copied from MSR */
25 #define MSR_MASK 0xffffffff87c0ffffUL
27 #define MSR_MASK 0x87c0ffff
31 #define XER_SO 0x80000000U
32 #define XER_OV 0x40000000U
33 #define XER_CA 0x20000000U
34 #define XER_OV32 0x00080000U
35 #define XER_CA32 0x00040000U
39 * Functions in ldstfp.S
41 extern void get_fpr(int rn, double *p);
42 extern void put_fpr(int rn, const double *p);
43 extern void get_vr(int rn, __vector128 *p);
44 extern void put_vr(int rn, __vector128 *p);
45 extern void load_vsrn(int vsr, const void *p);
46 extern void store_vsrn(int vsr, void *p);
47 extern void conv_sp_to_dp(const float *sp, double *dp);
48 extern void conv_dp_to_sp(const double *dp, float *sp);
55 extern int do_lq(unsigned long ea, unsigned long *regs);
56 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
57 extern int do_lqarx(unsigned long ea, unsigned long *regs);
58 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
62 #ifdef __LITTLE_ENDIAN__
71 * Emulate the truncation of 64 bit values in 32-bit mode.
73 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
77 if ((msr & MSR_64BIT) == 0)
84 * Determine whether a conditional branch instruction would branch.
86 static nokprobe_inline int branch_taken(unsigned int instr,
87 const struct pt_regs *regs,
88 struct instruction_op *op)
90 unsigned int bo = (instr >> 21) & 0x1f;
94 /* decrement counter */
96 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
99 if ((bo & 0x10) == 0) {
100 /* check bit from CR */
101 bi = (instr >> 16) & 0x1f;
102 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
108 static nokprobe_inline long address_ok(struct pt_regs *regs,
109 unsigned long ea, int nb)
111 if (!user_mode(regs))
113 if (__access_ok(ea, nb, USER_DS))
115 if (__access_ok(ea, 1, USER_DS))
116 /* Access overlaps the end of the user region */
117 regs->dar = USER_DS.seg;
124 * Calculate effective address for a D-form instruction
126 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
127 const struct pt_regs *regs)
132 ra = (instr >> 16) & 0x1f;
133 ea = (signed short) instr; /* sign-extend */
142 * Calculate effective address for a DS-form instruction
144 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
145 const struct pt_regs *regs)
150 ra = (instr >> 16) & 0x1f;
151 ea = (signed short) (instr & ~3); /* sign-extend */
159 * Calculate effective address for a DQ-form instruction
161 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
162 const struct pt_regs *regs)
167 ra = (instr >> 16) & 0x1f;
168 ea = (signed short) (instr & ~0xf); /* sign-extend */
174 #endif /* __powerpc64 */
177 * Calculate effective address for an X-form instruction
179 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
180 const struct pt_regs *regs)
185 ra = (instr >> 16) & 0x1f;
186 rb = (instr >> 11) & 0x1f;
195 * Return the largest power of 2, not greater than sizeof(unsigned long),
196 * such that x is a multiple of it.
198 static nokprobe_inline unsigned long max_align(unsigned long x)
200 x |= sizeof(unsigned long);
201 return x & -x; /* isolates rightmost bit */
204 static nokprobe_inline unsigned long byterev_2(unsigned long x)
206 return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
209 static nokprobe_inline unsigned long byterev_4(unsigned long x)
211 return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
212 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
216 static nokprobe_inline unsigned long byterev_8(unsigned long x)
218 return (byterev_4(x) << 32) | byterev_4(x >> 32);
222 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
226 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
229 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
233 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
236 unsigned long *up = (unsigned long *)ptr;
238 tmp = byterev_8(up[0]);
239 up[0] = byterev_8(up[1]);
249 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
250 unsigned long ea, int nb,
251 struct pt_regs *regs)
258 err = __get_user(x, (unsigned char __user *) ea);
261 err = __get_user(x, (unsigned short __user *) ea);
264 err = __get_user(x, (unsigned int __user *) ea);
268 err = __get_user(x, (unsigned long __user *) ea);
280 * Copy from userspace to a buffer, using the largest possible
281 * aligned accesses, up to sizeof(long).
283 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb,
284 struct pt_regs *regs)
289 for (; nb > 0; nb -= c) {
295 err = __get_user(*dest, (unsigned char __user *) ea);
298 err = __get_user(*(u16 *)dest,
299 (unsigned short __user *) ea);
302 err = __get_user(*(u32 *)dest,
303 (unsigned int __user *) ea);
307 err = __get_user(*(unsigned long *)dest,
308 (unsigned long __user *) ea);
322 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
323 unsigned long ea, int nb,
324 struct pt_regs *regs)
328 u8 b[sizeof(unsigned long)];
334 i = IS_BE ? sizeof(unsigned long) - nb : 0;
335 err = copy_mem_in(&u.b[i], ea, nb, regs);
342 * Read memory at address ea for nb bytes, return 0 for success
343 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
344 * If nb < sizeof(long), the result is right-justified on BE systems.
346 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
347 struct pt_regs *regs)
349 if (!address_ok(regs, ea, nb))
351 if ((ea & (nb - 1)) == 0)
352 return read_mem_aligned(dest, ea, nb, regs);
353 return read_mem_unaligned(dest, ea, nb, regs);
355 NOKPROBE_SYMBOL(read_mem);
357 static nokprobe_inline int write_mem_aligned(unsigned long val,
358 unsigned long ea, int nb,
359 struct pt_regs *regs)
365 err = __put_user(val, (unsigned char __user *) ea);
368 err = __put_user(val, (unsigned short __user *) ea);
371 err = __put_user(val, (unsigned int __user *) ea);
375 err = __put_user(val, (unsigned long __user *) ea);
385 * Copy from a buffer to userspace, using the largest possible
386 * aligned accesses, up to sizeof(long).
388 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb,
389 struct pt_regs *regs)
394 for (; nb > 0; nb -= c) {
400 err = __put_user(*dest, (unsigned char __user *) ea);
403 err = __put_user(*(u16 *)dest,
404 (unsigned short __user *) ea);
407 err = __put_user(*(u32 *)dest,
408 (unsigned int __user *) ea);
412 err = __put_user(*(unsigned long *)dest,
413 (unsigned long __user *) ea);
427 static nokprobe_inline int write_mem_unaligned(unsigned long val,
428 unsigned long ea, int nb,
429 struct pt_regs *regs)
433 u8 b[sizeof(unsigned long)];
438 i = IS_BE ? sizeof(unsigned long) - nb : 0;
439 return copy_mem_out(&u.b[i], ea, nb, regs);
443 * Write memory at address ea for nb bytes, return 0 for success
444 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
446 static int write_mem(unsigned long val, unsigned long ea, int nb,
447 struct pt_regs *regs)
449 if (!address_ok(regs, ea, nb))
451 if ((ea & (nb - 1)) == 0)
452 return write_mem_aligned(val, ea, nb, regs);
453 return write_mem_unaligned(val, ea, nb, regs);
455 NOKPROBE_SYMBOL(write_mem);
457 #ifdef CONFIG_PPC_FPU
459 * These access either the real FP register or the image in the
460 * thread_struct, depending on regs->msr & MSR_FP.
462 static int do_fp_load(struct instruction_op *op, unsigned long ea,
463 struct pt_regs *regs, bool cross_endian)
472 u8 b[2 * sizeof(double)];
475 nb = GETSIZE(op->type);
476 if (!address_ok(regs, ea, nb))
479 err = copy_mem_in(u.b, ea, nb, regs);
482 if (unlikely(cross_endian)) {
483 do_byte_reverse(u.b, min(nb, 8));
485 do_byte_reverse(&u.b[8], 8);
489 if (op->type & FPCONV)
490 conv_sp_to_dp(&u.f, &u.d[0]);
491 else if (op->type & SIGNEXT)
496 if (regs->msr & MSR_FP)
497 put_fpr(rn, &u.d[0]);
499 current->thread.TS_FPR(rn) = u.l[0];
503 if (regs->msr & MSR_FP)
504 put_fpr(rn, &u.d[1]);
506 current->thread.TS_FPR(rn) = u.l[1];
511 NOKPROBE_SYMBOL(do_fp_load);
513 static int do_fp_store(struct instruction_op *op, unsigned long ea,
514 struct pt_regs *regs, bool cross_endian)
522 u8 b[2 * sizeof(double)];
525 nb = GETSIZE(op->type);
526 if (!address_ok(regs, ea, nb))
530 if (regs->msr & MSR_FP)
531 get_fpr(rn, &u.d[0]);
533 u.l[0] = current->thread.TS_FPR(rn);
535 if (op->type & FPCONV)
536 conv_dp_to_sp(&u.d[0], &u.f);
542 if (regs->msr & MSR_FP)
543 get_fpr(rn, &u.d[1]);
545 u.l[1] = current->thread.TS_FPR(rn);
548 if (unlikely(cross_endian)) {
549 do_byte_reverse(u.b, min(nb, 8));
551 do_byte_reverse(&u.b[8], 8);
553 return copy_mem_out(u.b, ea, nb, regs);
555 NOKPROBE_SYMBOL(do_fp_store);
558 #ifdef CONFIG_ALTIVEC
559 /* For Altivec/VMX, no need to worry about alignment */
560 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
561 int size, struct pt_regs *regs,
567 u8 b[sizeof(__vector128)];
570 if (!address_ok(regs, ea & ~0xfUL, 16))
572 /* align to multiple of size */
574 err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
577 if (unlikely(cross_endian))
578 do_byte_reverse(&u.b[ea & 0xf], size);
580 if (regs->msr & MSR_VEC)
583 current->thread.vr_state.vr[rn] = u.v;
588 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
589 int size, struct pt_regs *regs,
594 u8 b[sizeof(__vector128)];
597 if (!address_ok(regs, ea & ~0xfUL, 16))
599 /* align to multiple of size */
603 if (regs->msr & MSR_VEC)
606 u.v = current->thread.vr_state.vr[rn];
608 if (unlikely(cross_endian))
609 do_byte_reverse(&u.b[ea & 0xf], size);
610 return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
612 #endif /* CONFIG_ALTIVEC */
615 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
616 int reg, bool cross_endian)
620 if (!address_ok(regs, ea, 16))
622 /* if aligned, should be atomic */
623 if ((ea & 0xf) == 0) {
624 err = do_lq(ea, ®s->gpr[reg]);
626 err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs);
628 err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs);
630 if (!err && unlikely(cross_endian))
631 do_byte_reverse(®s->gpr[reg], 16);
635 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
636 int reg, bool cross_endian)
639 unsigned long vals[2];
641 if (!address_ok(regs, ea, 16))
643 vals[0] = regs->gpr[reg];
644 vals[1] = regs->gpr[reg + 1];
645 if (unlikely(cross_endian))
646 do_byte_reverse(vals, 16);
648 /* if aligned, should be atomic */
650 return do_stq(ea, vals[0], vals[1]);
652 err = write_mem(vals[IS_LE], ea, 8, regs);
654 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
657 #endif /* __powerpc64 */
660 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
661 const void *mem, bool rev)
665 const unsigned int *wp;
666 const unsigned short *hp;
667 const unsigned char *bp;
669 size = GETSIZE(op->type);
670 reg->d[0] = reg->d[1] = 0;
672 switch (op->element_size) {
674 /* whole vector; lxv[x] or lxvl[l] */
677 memcpy(reg, mem, size);
678 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
681 do_byte_reverse(reg, 16);
684 /* scalar loads, lxvd2x, lxvdsx */
685 read_size = (size >= 8) ? 8 : size;
686 i = IS_LE ? 8 : 8 - read_size;
687 memcpy(®->b[i], mem, read_size);
689 do_byte_reverse(®->b[i], 8);
691 if (op->type & SIGNEXT) {
692 /* size == 4 is the only case here */
693 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
694 } else if (op->vsx_flags & VSX_FPCONV) {
696 conv_sp_to_dp(®->fp[1 + IS_LE],
702 unsigned long v = *(unsigned long *)(mem + 8);
703 reg->d[IS_BE] = !rev ? v : byterev_8(v);
704 } else if (op->vsx_flags & VSX_SPLAT)
705 reg->d[IS_BE] = reg->d[IS_LE];
711 for (j = 0; j < size / 4; ++j) {
712 i = IS_LE ? 3 - j : j;
713 reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
715 if (op->vsx_flags & VSX_SPLAT) {
716 u32 val = reg->w[IS_LE ? 3 : 0];
718 i = IS_LE ? 3 - j : j;
726 for (j = 0; j < size / 2; ++j) {
727 i = IS_LE ? 7 - j : j;
728 reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
734 for (j = 0; j < size; ++j) {
735 i = IS_LE ? 15 - j : j;
741 EXPORT_SYMBOL_GPL(emulate_vsx_load);
742 NOKPROBE_SYMBOL(emulate_vsx_load);
744 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
747 int size, write_size;
754 size = GETSIZE(op->type);
756 switch (op->element_size) {
758 /* stxv, stxvx, stxvl, stxvll */
761 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
764 /* reverse 16 bytes */
765 buf.d[0] = byterev_8(reg->d[1]);
766 buf.d[1] = byterev_8(reg->d[0]);
769 memcpy(mem, reg, size);
772 /* scalar stores, stxvd2x */
773 write_size = (size >= 8) ? 8 : size;
774 i = IS_LE ? 8 : 8 - write_size;
775 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
776 buf.d[0] = buf.d[1] = 0;
778 conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]);
782 memcpy(mem, ®->b[i], write_size);
784 memcpy(mem + 8, ®->d[IS_BE], 8);
786 do_byte_reverse(mem, write_size);
788 do_byte_reverse(mem + 8, 8);
794 for (j = 0; j < size / 4; ++j) {
795 i = IS_LE ? 3 - j : j;
796 *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
802 for (j = 0; j < size / 2; ++j) {
803 i = IS_LE ? 7 - j : j;
804 *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
810 for (j = 0; j < size; ++j) {
811 i = IS_LE ? 15 - j : j;
817 EXPORT_SYMBOL_GPL(emulate_vsx_store);
818 NOKPROBE_SYMBOL(emulate_vsx_store);
820 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
821 unsigned long ea, struct pt_regs *regs,
827 int size = GETSIZE(op->type);
829 if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
832 emulate_vsx_load(op, &buf, mem, cross_endian);
835 /* FP regs + extensions */
836 if (regs->msr & MSR_FP) {
837 load_vsrn(reg, &buf);
839 current->thread.fp_state.fpr[reg][0] = buf.d[0];
840 current->thread.fp_state.fpr[reg][1] = buf.d[1];
843 if (regs->msr & MSR_VEC)
844 load_vsrn(reg, &buf);
846 current->thread.vr_state.vr[reg - 32] = buf.v;
852 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
853 unsigned long ea, struct pt_regs *regs,
859 int size = GETSIZE(op->type);
861 if (!address_ok(regs, ea, size))
866 /* FP regs + extensions */
867 if (regs->msr & MSR_FP) {
868 store_vsrn(reg, &buf);
870 buf.d[0] = current->thread.fp_state.fpr[reg][0];
871 buf.d[1] = current->thread.fp_state.fpr[reg][1];
874 if (regs->msr & MSR_VEC)
875 store_vsrn(reg, &buf);
877 buf.v = current->thread.vr_state.vr[reg - 32];
880 emulate_vsx_store(op, &buf, mem, cross_endian);
881 return copy_mem_out(mem, ea, size, regs);
883 #endif /* CONFIG_VSX */
885 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
888 unsigned long i, size;
891 size = ppc64_caches.l1d.block_size;
892 if (!(regs->msr & MSR_64BIT))
895 size = L1_CACHE_BYTES;
898 if (!address_ok(regs, ea, size))
900 for (i = 0; i < size; i += sizeof(long)) {
901 err = __put_user(0, (unsigned long __user *) (ea + i));
909 NOKPROBE_SYMBOL(emulate_dcbz);
911 #define __put_user_asmx(x, addr, err, op, cr) \
912 __asm__ __volatile__( \
913 "1: " op " %2,0,%3\n" \
916 ".section .fixup,\"ax\"\n" \
921 : "=r" (err), "=r" (cr) \
922 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
924 #define __get_user_asmx(x, addr, err, op) \
925 __asm__ __volatile__( \
926 "1: "op" %1,0,%2\n" \
928 ".section .fixup,\"ax\"\n" \
933 : "=r" (err), "=r" (x) \
934 : "r" (addr), "i" (-EFAULT), "0" (err))
936 #define __cacheop_user_asmx(addr, err, op) \
937 __asm__ __volatile__( \
940 ".section .fixup,\"ax\"\n" \
946 : "r" (addr), "i" (-EFAULT), "0" (err))
948 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
949 struct instruction_op *op)
954 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
956 if (!(regs->msr & MSR_64BIT))
960 op->ccval |= 0x80000000;
962 op->ccval |= 0x40000000;
964 op->ccval |= 0x20000000;
967 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val)
969 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
971 op->xerval |= XER_CA32;
973 op->xerval &= ~XER_CA32;
977 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
978 struct instruction_op *op, int rd,
979 unsigned long val1, unsigned long val2,
980 unsigned long carry_in)
982 unsigned long val = val1 + val2;
986 op->type = COMPUTE + SETREG + SETXER;
990 if (!(regs->msr & MSR_64BIT)) {
991 val = (unsigned int) val;
992 val1 = (unsigned int) val1;
995 op->xerval = regs->xer;
996 if (val < val1 || (carry_in && val == val1))
997 op->xerval |= XER_CA;
999 op->xerval &= ~XER_CA;
1001 set_ca32(op, (unsigned int)val < (unsigned int)val1 ||
1002 (carry_in && (unsigned int)val == (unsigned int)val1));
1005 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
1006 struct instruction_op *op,
1007 long v1, long v2, int crfld)
1009 unsigned int crval, shift;
1011 op->type = COMPUTE + SETCC;
1012 crval = (regs->xer >> 31) & 1; /* get SO bit */
1019 shift = (7 - crfld) * 4;
1020 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1023 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1024 struct instruction_op *op,
1026 unsigned long v2, int crfld)
1028 unsigned int crval, shift;
1030 op->type = COMPUTE + SETCC;
1031 crval = (regs->xer >> 31) & 1; /* get SO bit */
1038 shift = (7 - crfld) * 4;
1039 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1042 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1043 struct instruction_op *op,
1044 unsigned long v1, unsigned long v2)
1046 unsigned long long out_val, mask;
1050 for (i = 0; i < 8; i++) {
1051 mask = 0xffUL << (i * 8);
1052 if ((v1 & mask) == (v2 & mask))
1059 * The size parameter is used to adjust the equivalent popcnt instruction.
1060 * popcntb = 8, popcntw = 32, popcntd = 64
1062 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1063 struct instruction_op *op,
1064 unsigned long v1, int size)
1066 unsigned long long out = v1;
1068 out -= (out >> 1) & 0x5555555555555555ULL;
1069 out = (0x3333333333333333ULL & out) +
1070 (0x3333333333333333ULL & (out >> 2));
1071 out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1073 if (size == 8) { /* popcntb */
1079 if (size == 32) { /* popcntw */
1080 op->val = out & 0x0000003f0000003fULL;
1084 out = (out + (out >> 32)) & 0x7f;
1085 op->val = out; /* popcntd */
1089 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1090 struct instruction_op *op,
1091 unsigned long v1, unsigned long v2)
1093 unsigned char perm, idx;
1097 for (i = 0; i < 8; i++) {
1098 idx = (v1 >> (i * 8)) & 0xff;
1100 if (v2 & PPC_BIT(idx))
1105 #endif /* CONFIG_PPC64 */
1107 * The size parameter adjusts the equivalent prty instruction.
1108 * prtyw = 32, prtyd = 64
1110 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1111 struct instruction_op *op,
1112 unsigned long v, int size)
1114 unsigned long long res = v ^ (v >> 8);
1117 if (size == 32) { /* prtyw */
1118 op->val = res & 0x0000000100000001ULL;
1123 op->val = res & 1; /*prtyd */
1126 static nokprobe_inline int trap_compare(long v1, long v2)
1136 if ((unsigned long)v1 < (unsigned long)v2)
1138 else if ((unsigned long)v1 > (unsigned long)v2)
1144 * Elements of 32-bit rotate and mask instructions.
1146 #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \
1147 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1148 #ifdef __powerpc64__
1149 #define MASK64_L(mb) (~0UL >> (mb))
1150 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me))
1151 #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1152 #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1154 #define DATA32(x) (x)
1156 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1159 * Decode an instruction, and return information about it in *op
1160 * without changing *regs.
1161 * Integer arithmetic and logical instructions, branches, and barrier
1162 * instructions can be emulated just using the information in *op.
1164 * Return value is 1 if the instruction can be emulated just by
1165 * updating *regs with the information in *op, -1 if we need the
1166 * GPRs but *regs doesn't contain the full register set, or 0
1169 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1172 unsigned int opcode, ra, rb, rc, rd, spr, u;
1173 unsigned long int imm;
1174 unsigned long int val, val2;
1175 unsigned int mb, me, sh;
1180 opcode = instr >> 26;
1184 imm = (signed short)(instr & 0xfffc);
1185 if ((instr & 2) == 0)
1187 op->val = truncate_if_32bit(regs->msr, imm);
1190 if (branch_taken(instr, regs, op))
1191 op->type |= BRTAKEN;
1195 if ((instr & 0xfe2) == 2)
1202 op->type = BRANCH | BRTAKEN;
1203 imm = instr & 0x03fffffc;
1204 if (imm & 0x02000000)
1206 if ((instr & 2) == 0)
1208 op->val = truncate_if_32bit(regs->msr, imm);
1213 switch ((instr >> 1) & 0x3ff) {
1215 op->type = COMPUTE + SETCC;
1216 rd = 7 - ((instr >> 23) & 0x7);
1217 ra = 7 - ((instr >> 18) & 0x7);
1220 val = (regs->ccr >> ra) & 0xf;
1221 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1225 case 528: /* bcctr */
1227 imm = (instr & 0x400)? regs->ctr: regs->link;
1228 op->val = truncate_if_32bit(regs->msr, imm);
1231 if (branch_taken(instr, regs, op))
1232 op->type |= BRTAKEN;
1235 case 18: /* rfid, scary */
1236 if (regs->msr & MSR_PR)
1241 case 150: /* isync */
1242 op->type = BARRIER | BARRIER_ISYNC;
1245 case 33: /* crnor */
1246 case 129: /* crandc */
1247 case 193: /* crxor */
1248 case 225: /* crnand */
1249 case 257: /* crand */
1250 case 289: /* creqv */
1251 case 417: /* crorc */
1252 case 449: /* cror */
1253 op->type = COMPUTE + SETCC;
1254 ra = (instr >> 16) & 0x1f;
1255 rb = (instr >> 11) & 0x1f;
1256 rd = (instr >> 21) & 0x1f;
1257 ra = (regs->ccr >> (31 - ra)) & 1;
1258 rb = (regs->ccr >> (31 - rb)) & 1;
1259 val = (instr >> (6 + ra * 2 + rb)) & 1;
1260 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1266 switch ((instr >> 1) & 0x3ff) {
1267 case 598: /* sync */
1268 op->type = BARRIER + BARRIER_SYNC;
1269 #ifdef __powerpc64__
1270 switch ((instr >> 21) & 3) {
1271 case 1: /* lwsync */
1272 op->type = BARRIER + BARRIER_LWSYNC;
1274 case 2: /* ptesync */
1275 op->type = BARRIER + BARRIER_PTESYNC;
1281 case 854: /* eieio */
1282 op->type = BARRIER + BARRIER_EIEIO;
1288 /* Following cases refer to regs->gpr[], so we need all regs */
1289 if (!FULL_REGS(regs))
1292 rd = (instr >> 21) & 0x1f;
1293 ra = (instr >> 16) & 0x1f;
1294 rb = (instr >> 11) & 0x1f;
1295 rc = (instr >> 6) & 0x1f;
1298 #ifdef __powerpc64__
1300 if (rd & trap_compare(regs->gpr[ra], (short) instr))
1305 if (rd & trap_compare((int)regs->gpr[ra], (short) instr))
1309 #ifdef __powerpc64__
1311 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1314 switch (instr & 0x3f) {
1315 case 48: /* maddhd */
1316 asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
1317 "=r" (op->val) : "r" (regs->gpr[ra]),
1318 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1321 case 49: /* maddhdu */
1322 asm volatile(PPC_MADDHDU(%0, %1, %2, %3) :
1323 "=r" (op->val) : "r" (regs->gpr[ra]),
1324 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1327 case 51: /* maddld */
1328 asm volatile(PPC_MADDLD(%0, %1, %2, %3) :
1329 "=r" (op->val) : "r" (regs->gpr[ra]),
1330 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1335 * There are other instructions from ISA 3.0 with the same
1336 * primary opcode which do not have emulation support yet.
1342 op->val = regs->gpr[ra] * (short) instr;
1345 case 8: /* subfic */
1346 imm = (short) instr;
1347 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1350 case 10: /* cmpli */
1351 imm = (unsigned short) instr;
1352 val = regs->gpr[ra];
1353 #ifdef __powerpc64__
1355 val = (unsigned int) val;
1357 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1361 imm = (short) instr;
1362 val = regs->gpr[ra];
1363 #ifdef __powerpc64__
1367 do_cmp_signed(regs, op, val, imm, rd >> 2);
1370 case 12: /* addic */
1371 imm = (short) instr;
1372 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1375 case 13: /* addic. */
1376 imm = (short) instr;
1377 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1382 imm = (short) instr;
1384 imm += regs->gpr[ra];
1388 case 15: /* addis */
1389 imm = ((short) instr) << 16;
1391 imm += regs->gpr[ra];
1396 if (((instr >> 1) & 0x1f) == 2) {
1398 imm = (short) (instr & 0xffc1); /* d0 + d2 fields */
1399 imm |= (instr >> 15) & 0x3e; /* d1 field */
1400 op->val = regs->nip + (imm << 16) + 4;
1406 case 20: /* rlwimi */
1407 mb = (instr >> 6) & 0x1f;
1408 me = (instr >> 1) & 0x1f;
1409 val = DATA32(regs->gpr[rd]);
1410 imm = MASK32(mb, me);
1411 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1414 case 21: /* rlwinm */
1415 mb = (instr >> 6) & 0x1f;
1416 me = (instr >> 1) & 0x1f;
1417 val = DATA32(regs->gpr[rd]);
1418 op->val = ROTATE(val, rb) & MASK32(mb, me);
1421 case 23: /* rlwnm */
1422 mb = (instr >> 6) & 0x1f;
1423 me = (instr >> 1) & 0x1f;
1424 rb = regs->gpr[rb] & 0x1f;
1425 val = DATA32(regs->gpr[rd]);
1426 op->val = ROTATE(val, rb) & MASK32(mb, me);
1430 op->val = regs->gpr[rd] | (unsigned short) instr;
1431 goto logical_done_nocc;
1434 imm = (unsigned short) instr;
1435 op->val = regs->gpr[rd] | (imm << 16);
1436 goto logical_done_nocc;
1439 op->val = regs->gpr[rd] ^ (unsigned short) instr;
1440 goto logical_done_nocc;
1442 case 27: /* xoris */
1443 imm = (unsigned short) instr;
1444 op->val = regs->gpr[rd] ^ (imm << 16);
1445 goto logical_done_nocc;
1447 case 28: /* andi. */
1448 op->val = regs->gpr[rd] & (unsigned short) instr;
1450 goto logical_done_nocc;
1452 case 29: /* andis. */
1453 imm = (unsigned short) instr;
1454 op->val = regs->gpr[rd] & (imm << 16);
1456 goto logical_done_nocc;
1458 #ifdef __powerpc64__
1460 mb = ((instr >> 6) & 0x1f) | (instr & 0x20);
1461 val = regs->gpr[rd];
1462 if ((instr & 0x10) == 0) {
1463 sh = rb | ((instr & 2) << 4);
1464 val = ROTATE(val, sh);
1465 switch ((instr >> 2) & 3) {
1466 case 0: /* rldicl */
1467 val &= MASK64_L(mb);
1469 case 1: /* rldicr */
1470 val &= MASK64_R(mb);
1473 val &= MASK64(mb, 63 - sh);
1475 case 3: /* rldimi */
1476 imm = MASK64(mb, 63 - sh);
1477 val = (regs->gpr[ra] & ~imm) |
1483 sh = regs->gpr[rb] & 0x3f;
1484 val = ROTATE(val, sh);
1485 switch ((instr >> 1) & 7) {
1487 op->val = val & MASK64_L(mb);
1490 op->val = val & MASK64_R(mb);
1495 op->type = UNKNOWN; /* illegal instruction */
1499 /* isel occupies 32 minor opcodes */
1500 if (((instr >> 1) & 0x1f) == 15) {
1501 mb = (instr >> 6) & 0x1f; /* bc field */
1502 val = (regs->ccr >> (31 - mb)) & 1;
1503 val2 = (ra) ? regs->gpr[ra] : 0;
1505 op->val = (val) ? val2 : regs->gpr[rb];
1509 switch ((instr >> 1) & 0x3ff) {
1512 (rd & trap_compare((int)regs->gpr[ra],
1513 (int)regs->gpr[rb])))
1516 #ifdef __powerpc64__
1518 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1522 case 83: /* mfmsr */
1523 if (regs->msr & MSR_PR)
1528 case 146: /* mtmsr */
1529 if (regs->msr & MSR_PR)
1533 op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1536 case 178: /* mtmsrd */
1537 if (regs->msr & MSR_PR)
1541 /* only MSR_EE and MSR_RI get changed if bit 15 set */
1542 /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1543 imm = (instr & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1550 if ((instr >> 20) & 1) {
1552 for (sh = 0; sh < 8; ++sh) {
1553 if (instr & (0x80000 >> sh))
1558 op->val = regs->ccr & imm;
1561 case 144: /* mtcrf */
1562 op->type = COMPUTE + SETCC;
1564 val = regs->gpr[rd];
1565 op->ccval = regs->ccr;
1566 for (sh = 0; sh < 8; ++sh) {
1567 if (instr & (0x80000 >> sh))
1568 op->ccval = (op->ccval & ~imm) |
1574 case 339: /* mfspr */
1575 spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1579 if (spr == SPRN_XER || spr == SPRN_LR ||
1584 case 467: /* mtspr */
1585 spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1587 op->val = regs->gpr[rd];
1589 if (spr == SPRN_XER || spr == SPRN_LR ||
1595 * Compare instructions
1598 val = regs->gpr[ra];
1599 val2 = regs->gpr[rb];
1600 #ifdef __powerpc64__
1601 if ((rd & 1) == 0) {
1602 /* word (32-bit) compare */
1607 do_cmp_signed(regs, op, val, val2, rd >> 2);
1611 val = regs->gpr[ra];
1612 val2 = regs->gpr[rb];
1613 #ifdef __powerpc64__
1614 if ((rd & 1) == 0) {
1615 /* word (32-bit) compare */
1616 val = (unsigned int) val;
1617 val2 = (unsigned int) val2;
1620 do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1623 case 508: /* cmpb */
1624 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1625 goto logical_done_nocc;
1628 * Arithmetic instructions
1631 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1634 #ifdef __powerpc64__
1635 case 9: /* mulhdu */
1636 asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1637 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1641 add_with_carry(regs, op, rd, regs->gpr[ra],
1645 case 11: /* mulhwu */
1646 asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1647 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1651 op->val = regs->gpr[rb] - regs->gpr[ra];
1653 #ifdef __powerpc64__
1654 case 73: /* mulhd */
1655 asm("mulhd %0,%1,%2" : "=r" (op->val) :
1656 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1659 case 75: /* mulhw */
1660 asm("mulhw %0,%1,%2" : "=r" (op->val) :
1661 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1665 op->val = -regs->gpr[ra];
1668 case 136: /* subfe */
1669 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1670 regs->gpr[rb], regs->xer & XER_CA);
1673 case 138: /* adde */
1674 add_with_carry(regs, op, rd, regs->gpr[ra],
1675 regs->gpr[rb], regs->xer & XER_CA);
1678 case 200: /* subfze */
1679 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1680 regs->xer & XER_CA);
1683 case 202: /* addze */
1684 add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1685 regs->xer & XER_CA);
1688 case 232: /* subfme */
1689 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1690 regs->xer & XER_CA);
1692 #ifdef __powerpc64__
1693 case 233: /* mulld */
1694 op->val = regs->gpr[ra] * regs->gpr[rb];
1697 case 234: /* addme */
1698 add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1699 regs->xer & XER_CA);
1702 case 235: /* mullw */
1703 op->val = (long)(int) regs->gpr[ra] *
1704 (int) regs->gpr[rb];
1707 #ifdef __powerpc64__
1708 case 265: /* modud */
1709 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1711 op->val = regs->gpr[ra] % regs->gpr[rb];
1715 op->val = regs->gpr[ra] + regs->gpr[rb];
1718 case 267: /* moduw */
1719 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1721 op->val = (unsigned int) regs->gpr[ra] %
1722 (unsigned int) regs->gpr[rb];
1724 #ifdef __powerpc64__
1725 case 457: /* divdu */
1726 op->val = regs->gpr[ra] / regs->gpr[rb];
1729 case 459: /* divwu */
1730 op->val = (unsigned int) regs->gpr[ra] /
1731 (unsigned int) regs->gpr[rb];
1733 #ifdef __powerpc64__
1734 case 489: /* divd */
1735 op->val = (long int) regs->gpr[ra] /
1736 (long int) regs->gpr[rb];
1739 case 491: /* divw */
1740 op->val = (int) regs->gpr[ra] /
1741 (int) regs->gpr[rb];
1744 case 755: /* darn */
1745 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1749 /* 32-bit conditioned */
1750 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val));
1754 /* 64-bit conditioned */
1755 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val));
1760 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val));
1765 #ifdef __powerpc64__
1766 case 777: /* modsd */
1767 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1769 op->val = (long int) regs->gpr[ra] %
1770 (long int) regs->gpr[rb];
1773 case 779: /* modsw */
1774 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1776 op->val = (int) regs->gpr[ra] %
1777 (int) regs->gpr[rb];
1782 * Logical instructions
1784 case 26: /* cntlzw */
1785 val = (unsigned int) regs->gpr[rd];
1786 op->val = ( val ? __builtin_clz(val) : 32 );
1788 #ifdef __powerpc64__
1789 case 58: /* cntlzd */
1790 val = regs->gpr[rd];
1791 op->val = ( val ? __builtin_clzl(val) : 64 );
1795 op->val = regs->gpr[rd] & regs->gpr[rb];
1799 op->val = regs->gpr[rd] & ~regs->gpr[rb];
1802 case 122: /* popcntb */
1803 do_popcnt(regs, op, regs->gpr[rd], 8);
1804 goto logical_done_nocc;
1807 op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1810 case 154: /* prtyw */
1811 do_prty(regs, op, regs->gpr[rd], 32);
1812 goto logical_done_nocc;
1814 case 186: /* prtyd */
1815 do_prty(regs, op, regs->gpr[rd], 64);
1816 goto logical_done_nocc;
1818 case 252: /* bpermd */
1819 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1820 goto logical_done_nocc;
1823 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1827 op->val = regs->gpr[rd] ^ regs->gpr[rb];
1830 case 378: /* popcntw */
1831 do_popcnt(regs, op, regs->gpr[rd], 32);
1832 goto logical_done_nocc;
1835 op->val = regs->gpr[rd] | ~regs->gpr[rb];
1839 op->val = regs->gpr[rd] | regs->gpr[rb];
1842 case 476: /* nand */
1843 op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1846 case 506: /* popcntd */
1847 do_popcnt(regs, op, regs->gpr[rd], 64);
1848 goto logical_done_nocc;
1850 case 538: /* cnttzw */
1851 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1853 val = (unsigned int) regs->gpr[rd];
1854 op->val = (val ? __builtin_ctz(val) : 32);
1856 #ifdef __powerpc64__
1857 case 570: /* cnttzd */
1858 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1860 val = regs->gpr[rd];
1861 op->val = (val ? __builtin_ctzl(val) : 64);
1864 case 922: /* extsh */
1865 op->val = (signed short) regs->gpr[rd];
1868 case 954: /* extsb */
1869 op->val = (signed char) regs->gpr[rd];
1871 #ifdef __powerpc64__
1872 case 986: /* extsw */
1873 op->val = (signed int) regs->gpr[rd];
1878 * Shift instructions
1881 sh = regs->gpr[rb] & 0x3f;
1883 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
1889 sh = regs->gpr[rb] & 0x3f;
1891 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
1896 case 792: /* sraw */
1897 op->type = COMPUTE + SETREG + SETXER;
1898 sh = regs->gpr[rb] & 0x3f;
1899 ival = (signed int) regs->gpr[rd];
1900 op->val = ival >> (sh < 32 ? sh : 31);
1901 op->xerval = regs->xer;
1902 if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
1903 op->xerval |= XER_CA;
1905 op->xerval &= ~XER_CA;
1906 set_ca32(op, op->xerval & XER_CA);
1909 case 824: /* srawi */
1910 op->type = COMPUTE + SETREG + SETXER;
1912 ival = (signed int) regs->gpr[rd];
1913 op->val = ival >> sh;
1914 op->xerval = regs->xer;
1915 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1916 op->xerval |= XER_CA;
1918 op->xerval &= ~XER_CA;
1919 set_ca32(op, op->xerval & XER_CA);
1922 #ifdef __powerpc64__
1924 sh = regs->gpr[rb] & 0x7f;
1926 op->val = regs->gpr[rd] << sh;
1932 sh = regs->gpr[rb] & 0x7f;
1934 op->val = regs->gpr[rd] >> sh;
1939 case 794: /* srad */
1940 op->type = COMPUTE + SETREG + SETXER;
1941 sh = regs->gpr[rb] & 0x7f;
1942 ival = (signed long int) regs->gpr[rd];
1943 op->val = ival >> (sh < 64 ? sh : 63);
1944 op->xerval = regs->xer;
1945 if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
1946 op->xerval |= XER_CA;
1948 op->xerval &= ~XER_CA;
1949 set_ca32(op, op->xerval & XER_CA);
1952 case 826: /* sradi with sh_5 = 0 */
1953 case 827: /* sradi with sh_5 = 1 */
1954 op->type = COMPUTE + SETREG + SETXER;
1955 sh = rb | ((instr & 2) << 4);
1956 ival = (signed long int) regs->gpr[rd];
1957 op->val = ival >> sh;
1958 op->xerval = regs->xer;
1959 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1960 op->xerval |= XER_CA;
1962 op->xerval &= ~XER_CA;
1963 set_ca32(op, op->xerval & XER_CA);
1966 case 890: /* extswsli with sh_5 = 0 */
1967 case 891: /* extswsli with sh_5 = 1 */
1968 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1970 op->type = COMPUTE + SETREG;
1971 sh = rb | ((instr & 2) << 4);
1972 val = (signed int) regs->gpr[rd];
1974 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
1979 #endif /* __powerpc64__ */
1982 * Cache instructions
1984 case 54: /* dcbst */
1985 op->type = MKOP(CACHEOP, DCBST, 0);
1986 op->ea = xform_ea(instr, regs);
1990 op->type = MKOP(CACHEOP, DCBF, 0);
1991 op->ea = xform_ea(instr, regs);
1994 case 246: /* dcbtst */
1995 op->type = MKOP(CACHEOP, DCBTST, 0);
1996 op->ea = xform_ea(instr, regs);
2000 case 278: /* dcbt */
2001 op->type = MKOP(CACHEOP, DCBTST, 0);
2002 op->ea = xform_ea(instr, regs);
2006 case 982: /* icbi */
2007 op->type = MKOP(CACHEOP, ICBI, 0);
2008 op->ea = xform_ea(instr, regs);
2011 case 1014: /* dcbz */
2012 op->type = MKOP(CACHEOP, DCBZ, 0);
2013 op->ea = xform_ea(instr, regs);
2023 op->update_reg = ra;
2025 op->val = regs->gpr[rd];
2026 u = (instr >> 20) & UPDATE;
2032 op->ea = xform_ea(instr, regs);
2033 switch ((instr >> 1) & 0x3ff) {
2034 case 20: /* lwarx */
2035 op->type = MKOP(LARX, 0, 4);
2038 case 150: /* stwcx. */
2039 op->type = MKOP(STCX, 0, 4);
2042 #ifdef __powerpc64__
2043 case 84: /* ldarx */
2044 op->type = MKOP(LARX, 0, 8);
2047 case 214: /* stdcx. */
2048 op->type = MKOP(STCX, 0, 8);
2051 case 52: /* lbarx */
2052 op->type = MKOP(LARX, 0, 1);
2055 case 694: /* stbcx. */
2056 op->type = MKOP(STCX, 0, 1);
2059 case 116: /* lharx */
2060 op->type = MKOP(LARX, 0, 2);
2063 case 726: /* sthcx. */
2064 op->type = MKOP(STCX, 0, 2);
2067 case 276: /* lqarx */
2068 if (!((rd & 1) || rd == ra || rd == rb))
2069 op->type = MKOP(LARX, 0, 16);
2072 case 182: /* stqcx. */
2074 op->type = MKOP(STCX, 0, 16);
2079 case 55: /* lwzux */
2080 op->type = MKOP(LOAD, u, 4);
2084 case 119: /* lbzux */
2085 op->type = MKOP(LOAD, u, 1);
2088 #ifdef CONFIG_ALTIVEC
2090 * Note: for the load/store vector element instructions,
2091 * bits of the EA say which field of the VMX register to use.
2094 op->type = MKOP(LOAD_VMX, 0, 1);
2095 op->element_size = 1;
2098 case 39: /* lvehx */
2099 op->type = MKOP(LOAD_VMX, 0, 2);
2100 op->element_size = 2;
2103 case 71: /* lvewx */
2104 op->type = MKOP(LOAD_VMX, 0, 4);
2105 op->element_size = 4;
2109 case 359: /* lvxl */
2110 op->type = MKOP(LOAD_VMX, 0, 16);
2111 op->element_size = 16;
2114 case 135: /* stvebx */
2115 op->type = MKOP(STORE_VMX, 0, 1);
2116 op->element_size = 1;
2119 case 167: /* stvehx */
2120 op->type = MKOP(STORE_VMX, 0, 2);
2121 op->element_size = 2;
2124 case 199: /* stvewx */
2125 op->type = MKOP(STORE_VMX, 0, 4);
2126 op->element_size = 4;
2129 case 231: /* stvx */
2130 case 487: /* stvxl */
2131 op->type = MKOP(STORE_VMX, 0, 16);
2133 #endif /* CONFIG_ALTIVEC */
2135 #ifdef __powerpc64__
2138 op->type = MKOP(LOAD, u, 8);
2141 case 149: /* stdx */
2142 case 181: /* stdux */
2143 op->type = MKOP(STORE, u, 8);
2147 case 151: /* stwx */
2148 case 183: /* stwux */
2149 op->type = MKOP(STORE, u, 4);
2152 case 215: /* stbx */
2153 case 247: /* stbux */
2154 op->type = MKOP(STORE, u, 1);
2157 case 279: /* lhzx */
2158 case 311: /* lhzux */
2159 op->type = MKOP(LOAD, u, 2);
2162 #ifdef __powerpc64__
2163 case 341: /* lwax */
2164 case 373: /* lwaux */
2165 op->type = MKOP(LOAD, SIGNEXT | u, 4);
2169 case 343: /* lhax */
2170 case 375: /* lhaux */
2171 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2174 case 407: /* sthx */
2175 case 439: /* sthux */
2176 op->type = MKOP(STORE, u, 2);
2179 #ifdef __powerpc64__
2180 case 532: /* ldbrx */
2181 op->type = MKOP(LOAD, BYTEREV, 8);
2185 case 533: /* lswx */
2186 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2189 case 534: /* lwbrx */
2190 op->type = MKOP(LOAD, BYTEREV, 4);
2193 case 597: /* lswi */
2195 rb = 32; /* # bytes to load */
2196 op->type = MKOP(LOAD_MULTI, 0, rb);
2197 op->ea = ra ? regs->gpr[ra] : 0;
2200 #ifdef CONFIG_PPC_FPU
2201 case 535: /* lfsx */
2202 case 567: /* lfsux */
2203 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2206 case 599: /* lfdx */
2207 case 631: /* lfdux */
2208 op->type = MKOP(LOAD_FP, u, 8);
2211 case 663: /* stfsx */
2212 case 695: /* stfsux */
2213 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2216 case 727: /* stfdx */
2217 case 759: /* stfdux */
2218 op->type = MKOP(STORE_FP, u, 8);
2221 #ifdef __powerpc64__
2222 case 791: /* lfdpx */
2223 op->type = MKOP(LOAD_FP, 0, 16);
2226 case 855: /* lfiwax */
2227 op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2230 case 887: /* lfiwzx */
2231 op->type = MKOP(LOAD_FP, 0, 4);
2234 case 919: /* stfdpx */
2235 op->type = MKOP(STORE_FP, 0, 16);
2238 case 983: /* stfiwx */
2239 op->type = MKOP(STORE_FP, 0, 4);
2241 #endif /* __powerpc64 */
2242 #endif /* CONFIG_PPC_FPU */
2244 #ifdef __powerpc64__
2245 case 660: /* stdbrx */
2246 op->type = MKOP(STORE, BYTEREV, 8);
2247 op->val = byterev_8(regs->gpr[rd]);
2251 case 661: /* stswx */
2252 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2255 case 662: /* stwbrx */
2256 op->type = MKOP(STORE, BYTEREV, 4);
2257 op->val = byterev_4(regs->gpr[rd]);
2260 case 725: /* stswi */
2262 rb = 32; /* # bytes to store */
2263 op->type = MKOP(STORE_MULTI, 0, rb);
2264 op->ea = ra ? regs->gpr[ra] : 0;
2267 case 790: /* lhbrx */
2268 op->type = MKOP(LOAD, BYTEREV, 2);
2271 case 918: /* sthbrx */
2272 op->type = MKOP(STORE, BYTEREV, 2);
2273 op->val = byterev_2(regs->gpr[rd]);
2277 case 12: /* lxsiwzx */
2278 op->reg = rd | ((instr & 1) << 5);
2279 op->type = MKOP(LOAD_VSX, 0, 4);
2280 op->element_size = 8;
2283 case 76: /* lxsiwax */
2284 op->reg = rd | ((instr & 1) << 5);
2285 op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2286 op->element_size = 8;
2289 case 140: /* stxsiwx */
2290 op->reg = rd | ((instr & 1) << 5);
2291 op->type = MKOP(STORE_VSX, 0, 4);
2292 op->element_size = 8;
2295 case 268: /* lxvx */
2296 op->reg = rd | ((instr & 1) << 5);
2297 op->type = MKOP(LOAD_VSX, 0, 16);
2298 op->element_size = 16;
2299 op->vsx_flags = VSX_CHECK_VEC;
2302 case 269: /* lxvl */
2303 case 301: { /* lxvll */
2305 op->reg = rd | ((instr & 1) << 5);
2306 op->ea = ra ? regs->gpr[ra] : 0;
2307 nb = regs->gpr[rb] & 0xff;
2310 op->type = MKOP(LOAD_VSX, 0, nb);
2311 op->element_size = 16;
2312 op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2316 case 332: /* lxvdsx */
2317 op->reg = rd | ((instr & 1) << 5);
2318 op->type = MKOP(LOAD_VSX, 0, 8);
2319 op->element_size = 8;
2320 op->vsx_flags = VSX_SPLAT;
2323 case 364: /* lxvwsx */
2324 op->reg = rd | ((instr & 1) << 5);
2325 op->type = MKOP(LOAD_VSX, 0, 4);
2326 op->element_size = 4;
2327 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2330 case 396: /* stxvx */
2331 op->reg = rd | ((instr & 1) << 5);
2332 op->type = MKOP(STORE_VSX, 0, 16);
2333 op->element_size = 16;
2334 op->vsx_flags = VSX_CHECK_VEC;
2337 case 397: /* stxvl */
2338 case 429: { /* stxvll */
2340 op->reg = rd | ((instr & 1) << 5);
2341 op->ea = ra ? regs->gpr[ra] : 0;
2342 nb = regs->gpr[rb] & 0xff;
2345 op->type = MKOP(STORE_VSX, 0, nb);
2346 op->element_size = 16;
2347 op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2351 case 524: /* lxsspx */
2352 op->reg = rd | ((instr & 1) << 5);
2353 op->type = MKOP(LOAD_VSX, 0, 4);
2354 op->element_size = 8;
2355 op->vsx_flags = VSX_FPCONV;
2358 case 588: /* lxsdx */
2359 op->reg = rd | ((instr & 1) << 5);
2360 op->type = MKOP(LOAD_VSX, 0, 8);
2361 op->element_size = 8;
2364 case 652: /* stxsspx */
2365 op->reg = rd | ((instr & 1) << 5);
2366 op->type = MKOP(STORE_VSX, 0, 4);
2367 op->element_size = 8;
2368 op->vsx_flags = VSX_FPCONV;
2371 case 716: /* stxsdx */
2372 op->reg = rd | ((instr & 1) << 5);
2373 op->type = MKOP(STORE_VSX, 0, 8);
2374 op->element_size = 8;
2377 case 780: /* lxvw4x */
2378 op->reg = rd | ((instr & 1) << 5);
2379 op->type = MKOP(LOAD_VSX, 0, 16);
2380 op->element_size = 4;
2383 case 781: /* lxsibzx */
2384 op->reg = rd | ((instr & 1) << 5);
2385 op->type = MKOP(LOAD_VSX, 0, 1);
2386 op->element_size = 8;
2387 op->vsx_flags = VSX_CHECK_VEC;
2390 case 812: /* lxvh8x */
2391 op->reg = rd | ((instr & 1) << 5);
2392 op->type = MKOP(LOAD_VSX, 0, 16);
2393 op->element_size = 2;
2394 op->vsx_flags = VSX_CHECK_VEC;
2397 case 813: /* lxsihzx */
2398 op->reg = rd | ((instr & 1) << 5);
2399 op->type = MKOP(LOAD_VSX, 0, 2);
2400 op->element_size = 8;
2401 op->vsx_flags = VSX_CHECK_VEC;
2404 case 844: /* lxvd2x */
2405 op->reg = rd | ((instr & 1) << 5);
2406 op->type = MKOP(LOAD_VSX, 0, 16);
2407 op->element_size = 8;
2410 case 876: /* lxvb16x */
2411 op->reg = rd | ((instr & 1) << 5);
2412 op->type = MKOP(LOAD_VSX, 0, 16);
2413 op->element_size = 1;
2414 op->vsx_flags = VSX_CHECK_VEC;
2417 case 908: /* stxvw4x */
2418 op->reg = rd | ((instr & 1) << 5);
2419 op->type = MKOP(STORE_VSX, 0, 16);
2420 op->element_size = 4;
2423 case 909: /* stxsibx */
2424 op->reg = rd | ((instr & 1) << 5);
2425 op->type = MKOP(STORE_VSX, 0, 1);
2426 op->element_size = 8;
2427 op->vsx_flags = VSX_CHECK_VEC;
2430 case 940: /* stxvh8x */
2431 op->reg = rd | ((instr & 1) << 5);
2432 op->type = MKOP(STORE_VSX, 0, 16);
2433 op->element_size = 2;
2434 op->vsx_flags = VSX_CHECK_VEC;
2437 case 941: /* stxsihx */
2438 op->reg = rd | ((instr & 1) << 5);
2439 op->type = MKOP(STORE_VSX, 0, 2);
2440 op->element_size = 8;
2441 op->vsx_flags = VSX_CHECK_VEC;
2444 case 972: /* stxvd2x */
2445 op->reg = rd | ((instr & 1) << 5);
2446 op->type = MKOP(STORE_VSX, 0, 16);
2447 op->element_size = 8;
2450 case 1004: /* stxvb16x */
2451 op->reg = rd | ((instr & 1) << 5);
2452 op->type = MKOP(STORE_VSX, 0, 16);
2453 op->element_size = 1;
2454 op->vsx_flags = VSX_CHECK_VEC;
2457 #endif /* CONFIG_VSX */
2463 op->type = MKOP(LOAD, u, 4);
2464 op->ea = dform_ea(instr, regs);
2469 op->type = MKOP(LOAD, u, 1);
2470 op->ea = dform_ea(instr, regs);
2475 op->type = MKOP(STORE, u, 4);
2476 op->ea = dform_ea(instr, regs);
2481 op->type = MKOP(STORE, u, 1);
2482 op->ea = dform_ea(instr, regs);
2487 op->type = MKOP(LOAD, u, 2);
2488 op->ea = dform_ea(instr, regs);
2493 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2494 op->ea = dform_ea(instr, regs);
2499 op->type = MKOP(STORE, u, 2);
2500 op->ea = dform_ea(instr, regs);
2505 break; /* invalid form, ra in range to load */
2506 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2507 op->ea = dform_ea(instr, regs);
2511 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2512 op->ea = dform_ea(instr, regs);
2515 #ifdef CONFIG_PPC_FPU
2518 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2519 op->ea = dform_ea(instr, regs);
2524 op->type = MKOP(LOAD_FP, u, 8);
2525 op->ea = dform_ea(instr, regs);
2529 case 53: /* stfsu */
2530 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2531 op->ea = dform_ea(instr, regs);
2535 case 55: /* stfdu */
2536 op->type = MKOP(STORE_FP, u, 8);
2537 op->ea = dform_ea(instr, regs);
2541 #ifdef __powerpc64__
2543 if (!((rd & 1) || (rd == ra)))
2544 op->type = MKOP(LOAD, 0, 16);
2545 op->ea = dqform_ea(instr, regs);
2550 case 57: /* lfdp, lxsd, lxssp */
2551 op->ea = dsform_ea(instr, regs);
2552 switch (instr & 3) {
2555 break; /* reg must be even */
2556 op->type = MKOP(LOAD_FP, 0, 16);
2560 op->type = MKOP(LOAD_VSX, 0, 8);
2561 op->element_size = 8;
2562 op->vsx_flags = VSX_CHECK_VEC;
2566 op->type = MKOP(LOAD_VSX, 0, 4);
2567 op->element_size = 8;
2568 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2572 #endif /* CONFIG_VSX */
2574 #ifdef __powerpc64__
2575 case 58: /* ld[u], lwa */
2576 op->ea = dsform_ea(instr, regs);
2577 switch (instr & 3) {
2579 op->type = MKOP(LOAD, 0, 8);
2582 op->type = MKOP(LOAD, UPDATE, 8);
2585 op->type = MKOP(LOAD, SIGNEXT, 4);
2592 case 61: /* stfdp, lxv, stxsd, stxssp, stxv */
2593 switch (instr & 7) {
2594 case 0: /* stfdp with LSB of DS field = 0 */
2595 case 4: /* stfdp with LSB of DS field = 1 */
2596 op->ea = dsform_ea(instr, regs);
2597 op->type = MKOP(STORE_FP, 0, 16);
2601 op->ea = dqform_ea(instr, regs);
2604 op->type = MKOP(LOAD_VSX, 0, 16);
2605 op->element_size = 16;
2606 op->vsx_flags = VSX_CHECK_VEC;
2609 case 2: /* stxsd with LSB of DS field = 0 */
2610 case 6: /* stxsd with LSB of DS field = 1 */
2611 op->ea = dsform_ea(instr, regs);
2613 op->type = MKOP(STORE_VSX, 0, 8);
2614 op->element_size = 8;
2615 op->vsx_flags = VSX_CHECK_VEC;
2618 case 3: /* stxssp with LSB of DS field = 0 */
2619 case 7: /* stxssp with LSB of DS field = 1 */
2620 op->ea = dsform_ea(instr, regs);
2622 op->type = MKOP(STORE_VSX, 0, 4);
2623 op->element_size = 8;
2624 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2628 op->ea = dqform_ea(instr, regs);
2631 op->type = MKOP(STORE_VSX, 0, 16);
2632 op->element_size = 16;
2633 op->vsx_flags = VSX_CHECK_VEC;
2637 #endif /* CONFIG_VSX */
2639 #ifdef __powerpc64__
2640 case 62: /* std[u] */
2641 op->ea = dsform_ea(instr, regs);
2642 switch (instr & 3) {
2644 op->type = MKOP(STORE, 0, 8);
2647 op->type = MKOP(STORE, UPDATE, 8);
2651 op->type = MKOP(STORE, 0, 16);
2655 #endif /* __powerpc64__ */
2660 if ((GETTYPE(op->type) == LOAD_VSX ||
2661 GETTYPE(op->type) == STORE_VSX) &&
2662 !cpu_has_feature(CPU_FTR_VSX)) {
2665 #endif /* CONFIG_VSX */
2686 op->type = INTERRUPT | 0x700;
2687 op->val = SRR1_PROGPRIV;
2691 op->type = INTERRUPT | 0x700;
2692 op->val = SRR1_PROGTRAP;
2695 EXPORT_SYMBOL_GPL(analyse_instr);
2696 NOKPROBE_SYMBOL(analyse_instr);
2699 * For PPC32 we always use stwu with r1 to change the stack pointer.
2700 * So this emulated store may corrupt the exception frame, now we
2701 * have to provide the exception frame trampoline, which is pushed
2702 * below the kprobed function stack. So we only update gpr[1] but
2703 * don't emulate the real store operation. We will do real store
2704 * operation safely in exception return code by checking this flag.
2706 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
2710 * Check if we will touch kernel stack overflow
2712 if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
2713 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n");
2716 #endif /* CONFIG_PPC32 */
2718 * Check if we already set since that means we'll
2719 * lose the previous value.
2721 WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
2722 set_thread_flag(TIF_EMULATE_STACK_STORE);
2726 static nokprobe_inline void do_signext(unsigned long *valp, int size)
2730 *valp = (signed short) *valp;
2733 *valp = (signed int) *valp;
2738 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
2742 *valp = byterev_2(*valp);
2745 *valp = byterev_4(*valp);
2747 #ifdef __powerpc64__
2749 *valp = byterev_8(*valp);
2756 * Emulate an instruction that can be executed just by updating
2759 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
2761 unsigned long next_pc;
2763 next_pc = truncate_if_32bit(regs->msr, regs->nip + 4);
2764 switch (GETTYPE(op->type)) {
2766 if (op->type & SETREG)
2767 regs->gpr[op->reg] = op->val;
2768 if (op->type & SETCC)
2769 regs->ccr = op->ccval;
2770 if (op->type & SETXER)
2771 regs->xer = op->xerval;
2775 if (op->type & SETLK)
2776 regs->link = next_pc;
2777 if (op->type & BRTAKEN)
2779 if (op->type & DECCTR)
2784 switch (op->type & BARRIER_MASK) {
2794 case BARRIER_LWSYNC:
2795 asm volatile("lwsync" : : : "memory");
2797 case BARRIER_PTESYNC:
2798 asm volatile("ptesync" : : : "memory");
2806 regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
2809 regs->gpr[op->reg] = regs->link;
2812 regs->gpr[op->reg] = regs->ctr;
2822 regs->xer = op->val & 0xffffffffUL;
2825 regs->link = op->val;
2828 regs->ctr = op->val;
2838 regs->nip = next_pc;
2840 NOKPROBE_SYMBOL(emulate_update_regs);
2843 * Emulate a previously-analysed load or store instruction.
2844 * Return values are:
2845 * 0 = instruction emulated successfully
2846 * -EFAULT = address out of range or access faulted (regs->dar
2847 * contains the faulting address)
2848 * -EACCES = misaligned access, instruction requires alignment
2849 * -EINVAL = unknown operation in *op
2851 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
2853 int err, size, type;
2861 size = GETSIZE(op->type);
2862 type = GETTYPE(op->type);
2863 cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
2864 ea = truncate_if_32bit(regs->msr, op->ea);
2868 if (ea & (size - 1))
2869 return -EACCES; /* can't handle misaligned */
2870 if (!address_ok(regs, ea, size))
2875 #ifdef __powerpc64__
2877 __get_user_asmx(val, ea, err, "lbarx");
2880 __get_user_asmx(val, ea, err, "lharx");
2884 __get_user_asmx(val, ea, err, "lwarx");
2886 #ifdef __powerpc64__
2888 __get_user_asmx(val, ea, err, "ldarx");
2891 err = do_lqarx(ea, ®s->gpr[op->reg]);
2902 regs->gpr[op->reg] = val;
2906 if (ea & (size - 1))
2907 return -EACCES; /* can't handle misaligned */
2908 if (!address_ok(regs, ea, size))
2912 #ifdef __powerpc64__
2914 __put_user_asmx(op->val, ea, err, "stbcx.", cr);
2917 __put_user_asmx(op->val, ea, err, "stbcx.", cr);
2921 __put_user_asmx(op->val, ea, err, "stwcx.", cr);
2923 #ifdef __powerpc64__
2925 __put_user_asmx(op->val, ea, err, "stdcx.", cr);
2928 err = do_stqcx(ea, regs->gpr[op->reg],
2929 regs->gpr[op->reg + 1], &cr);
2936 regs->ccr = (regs->ccr & 0x0fffffff) |
2938 ((regs->xer >> 3) & 0x10000000);
2944 #ifdef __powerpc64__
2946 err = emulate_lq(regs, ea, op->reg, cross_endian);
2950 err = read_mem(®s->gpr[op->reg], ea, size, regs);
2952 if (op->type & SIGNEXT)
2953 do_signext(®s->gpr[op->reg], size);
2954 if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
2955 do_byterev(®s->gpr[op->reg], size);
2959 #ifdef CONFIG_PPC_FPU
2962 * If the instruction is in userspace, we can emulate it even
2963 * if the VMX state is not live, because we have the state
2964 * stored in the thread_struct. If the instruction is in
2965 * the kernel, we must not touch the state in the thread_struct.
2967 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
2969 err = do_fp_load(op, ea, regs, cross_endian);
2972 #ifdef CONFIG_ALTIVEC
2974 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
2976 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
2981 unsigned long msrbit = MSR_VSX;
2984 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
2985 * when the target of the instruction is a vector register.
2987 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
2989 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
2991 err = do_vsx_load(op, ea, regs, cross_endian);
2996 if (!address_ok(regs, ea, size))
2999 for (i = 0; i < size; i += 4) {
3000 unsigned int v32 = 0;
3005 err = copy_mem_in((u8 *) &v32, ea, nb, regs);
3008 if (unlikely(cross_endian))
3009 v32 = byterev_4(v32);
3010 regs->gpr[rd] = v32;
3012 /* reg number wraps from 31 to 0 for lsw[ix] */
3013 rd = (rd + 1) & 0x1f;
3018 #ifdef __powerpc64__
3020 err = emulate_stq(regs, ea, op->reg, cross_endian);
3024 if ((op->type & UPDATE) && size == sizeof(long) &&
3025 op->reg == 1 && op->update_reg == 1 &&
3026 !(regs->msr & MSR_PR) &&
3027 ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
3028 err = handle_stack_update(ea, regs);
3031 if (unlikely(cross_endian))
3032 do_byterev(&op->val, size);
3033 err = write_mem(op->val, ea, size, regs);
3036 #ifdef CONFIG_PPC_FPU
3038 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3040 err = do_fp_store(op, ea, regs, cross_endian);
3043 #ifdef CONFIG_ALTIVEC
3045 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3047 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
3052 unsigned long msrbit = MSR_VSX;
3055 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3056 * when the target of the instruction is a vector register.
3058 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3060 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3062 err = do_vsx_store(op, ea, regs, cross_endian);
3067 if (!address_ok(regs, ea, size))
3070 for (i = 0; i < size; i += 4) {
3071 unsigned int v32 = regs->gpr[rd];
3076 if (unlikely(cross_endian))
3077 v32 = byterev_4(v32);
3078 err = copy_mem_out((u8 *) &v32, ea, nb, regs);
3082 /* reg number wraps from 31 to 0 for stsw[ix] */
3083 rd = (rd + 1) & 0x1f;
3094 if (op->type & UPDATE)
3095 regs->gpr[op->update_reg] = op->ea;
3099 NOKPROBE_SYMBOL(emulate_loadstore);
3102 * Emulate instructions that cause a transfer of control,
3103 * loads and stores, and a few other instructions.
3104 * Returns 1 if the step was emulated, 0 if not,
3105 * or -1 if the instruction is one that should not be stepped,
3106 * such as an rfid, or a mtmsrd that would clear MSR_RI.
3108 int emulate_step(struct pt_regs *regs, unsigned int instr)
3110 struct instruction_op op;
3115 r = analyse_instr(&op, regs, instr);
3119 emulate_update_regs(regs, &op);
3124 type = GETTYPE(op.type);
3126 if (OP_IS_LOAD_STORE(type)) {
3127 err = emulate_loadstore(regs, &op);
3135 ea = truncate_if_32bit(regs->msr, op.ea);
3136 if (!address_ok(regs, ea, 8))
3138 switch (op.type & CACHEOP_MASK) {
3140 __cacheop_user_asmx(ea, err, "dcbst");
3143 __cacheop_user_asmx(ea, err, "dcbf");
3147 prefetchw((void *) ea);
3151 prefetch((void *) ea);
3154 __cacheop_user_asmx(ea, err, "icbi");
3157 err = emulate_dcbz(ea, regs);
3167 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3171 val = regs->gpr[op.reg];
3172 if ((val & MSR_RI) == 0)
3173 /* can't step mtmsr[d] that would clear MSR_RI */
3175 /* here op.val is the mask of bits to change */
3176 regs->msr = (regs->msr & ~op.val) | (val & op.val);
3180 case SYSCALL: /* sc */
3182 * N.B. this uses knowledge about how the syscall
3183 * entry code works. If that is changed, this will
3184 * need to be changed also.
3186 if (regs->gpr[0] == 0x1ebe &&
3187 cpu_has_feature(CPU_FTR_REAL_LE)) {
3188 regs->msr ^= MSR_LE;
3191 regs->gpr[9] = regs->gpr[13];
3192 regs->gpr[10] = MSR_KERNEL;
3193 regs->gpr[11] = regs->nip + 4;
3194 regs->gpr[12] = regs->msr & MSR_MASK;
3195 regs->gpr[13] = (unsigned long) get_paca();
3196 regs->nip = (unsigned long) &system_call_common;
3197 regs->msr = MSR_KERNEL;
3207 regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4);
3210 NOKPROBE_SYMBOL(emulate_step);