1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
7 #include <linux/kernel.h>
8 #include <linux/kprobes.h>
9 #include <linux/ptrace.h>
10 #include <linux/prefetch.h>
11 #include <asm/sstep.h>
12 #include <asm/processor.h>
13 #include <linux/uaccess.h>
14 #include <asm/cpu_has_feature.h>
15 #include <asm/cputable.h>
16 #include <asm/disassemble.h>
19 /* Bits in SRR1 that are copied from MSR */
20 #define MSR_MASK 0xffffffff87c0ffffUL
22 #define MSR_MASK 0x87c0ffff
26 #define XER_SO 0x80000000U
27 #define XER_OV 0x40000000U
28 #define XER_CA 0x20000000U
29 #define XER_OV32 0x00080000U
30 #define XER_CA32 0x00040000U
33 #define VSX_REGISTER_XTP(rd) ((((rd) & 1) << 5) | ((rd) & 0xfe))
38 * Functions in ldstfp.S
40 extern void get_fpr(int rn, double *p);
41 extern void put_fpr(int rn, const double *p);
42 extern void get_vr(int rn, __vector128 *p);
43 extern void put_vr(int rn, __vector128 *p);
44 extern void load_vsrn(int vsr, const void *p);
45 extern void store_vsrn(int vsr, void *p);
46 extern void conv_sp_to_dp(const float *sp, double *dp);
47 extern void conv_dp_to_sp(const double *dp, float *sp);
54 extern int do_lq(unsigned long ea, unsigned long *regs);
55 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
56 extern int do_lqarx(unsigned long ea, unsigned long *regs);
57 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
61 #ifdef __LITTLE_ENDIAN__
70 * Emulate the truncation of 64 bit values in 32-bit mode.
72 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
75 if ((msr & MSR_64BIT) == 0)
81 * Determine whether a conditional branch instruction would branch.
83 static nokprobe_inline int branch_taken(unsigned int instr,
84 const struct pt_regs *regs,
85 struct instruction_op *op)
87 unsigned int bo = (instr >> 21) & 0x1f;
91 /* decrement counter */
93 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
96 if ((bo & 0x10) == 0) {
97 /* check bit from CR */
98 bi = (instr >> 16) & 0x1f;
99 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
105 static nokprobe_inline long address_ok(struct pt_regs *regs,
106 unsigned long ea, int nb)
108 if (!user_mode(regs))
110 if (access_ok((void __user *)ea, nb))
112 if (access_ok((void __user *)ea, 1))
113 /* Access overlaps the end of the user region */
114 regs->dar = TASK_SIZE_MAX - 1;
121 * Calculate effective address for a D-form instruction
123 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
124 const struct pt_regs *regs)
129 ra = (instr >> 16) & 0x1f;
130 ea = (signed short) instr; /* sign-extend */
139 * Calculate effective address for a DS-form instruction
141 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
142 const struct pt_regs *regs)
147 ra = (instr >> 16) & 0x1f;
148 ea = (signed short) (instr & ~3); /* sign-extend */
156 * Calculate effective address for a DQ-form instruction
158 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
159 const struct pt_regs *regs)
164 ra = (instr >> 16) & 0x1f;
165 ea = (signed short) (instr & ~0xf); /* sign-extend */
171 #endif /* __powerpc64 */
174 * Calculate effective address for an X-form instruction
176 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
177 const struct pt_regs *regs)
182 ra = (instr >> 16) & 0x1f;
183 rb = (instr >> 11) & 0x1f;
192 * Calculate effective address for a MLS:D-form / 8LS:D-form
193 * prefixed instruction
195 static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
197 const struct pt_regs *regs)
201 unsigned long ea, d0, d1, d;
203 prefix_r = GET_PREFIX_R(instr);
204 ra = GET_PREFIX_RA(suffix);
206 d0 = instr & 0x3ffff;
207 d1 = suffix & 0xffff;
211 * sign extend a 34 bit number
213 dd = (unsigned int)(d >> 2);
215 ea = (ea << 2) | (d & 0x3);
219 else if (!prefix_r && !ra)
220 ; /* Leave ea as is */
225 * (prefix_r && ra) is an invalid form. Should already be
226 * checked for by caller!
233 * Return the largest power of 2, not greater than sizeof(unsigned long),
234 * such that x is a multiple of it.
236 static nokprobe_inline unsigned long max_align(unsigned long x)
238 x |= sizeof(unsigned long);
239 return x & -x; /* isolates rightmost bit */
242 static nokprobe_inline unsigned long byterev_2(unsigned long x)
244 return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
247 static nokprobe_inline unsigned long byterev_4(unsigned long x)
249 return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
250 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
254 static nokprobe_inline unsigned long byterev_8(unsigned long x)
256 return (byterev_4(x) << 32) | byterev_4(x >> 32);
260 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
264 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
267 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
271 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
274 unsigned long *up = (unsigned long *)ptr;
276 tmp = byterev_8(up[0]);
277 up[0] = byterev_8(up[1]);
282 unsigned long *up = (unsigned long *)ptr;
285 tmp = byterev_8(up[0]);
286 up[0] = byterev_8(up[3]);
288 tmp = byterev_8(up[2]);
289 up[2] = byterev_8(up[1]);
300 static __always_inline int
301 __read_mem_aligned(unsigned long *dest, unsigned long ea, int nb, struct pt_regs *regs)
307 unsafe_get_user(x, (unsigned char __user *)ea, Efault);
310 unsafe_get_user(x, (unsigned short __user *)ea, Efault);
313 unsafe_get_user(x, (unsigned int __user *)ea, Efault);
317 unsafe_get_user(x, (unsigned long __user *)ea, Efault);
329 static nokprobe_inline int
330 read_mem_aligned(unsigned long *dest, unsigned long ea, int nb, struct pt_regs *regs)
334 if (is_kernel_addr(ea))
335 return __read_mem_aligned(dest, ea, nb, regs);
337 if (user_read_access_begin((void __user *)ea, nb)) {
338 err = __read_mem_aligned(dest, ea, nb, regs);
339 user_read_access_end();
349 * Copy from userspace to a buffer, using the largest possible
350 * aligned accesses, up to sizeof(long).
352 static __always_inline int __copy_mem_in(u8 *dest, unsigned long ea, int nb, struct pt_regs *regs)
356 for (; nb > 0; nb -= c) {
362 unsafe_get_user(*dest, (u8 __user *)ea, Efault);
365 unsafe_get_user(*(u16 *)dest, (u16 __user *)ea, Efault);
368 unsafe_get_user(*(u32 *)dest, (u32 __user *)ea, Efault);
372 unsafe_get_user(*(u64 *)dest, (u64 __user *)ea, Efault);
386 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb, struct pt_regs *regs)
390 if (is_kernel_addr(ea))
391 return __copy_mem_in(dest, ea, nb, regs);
393 if (user_read_access_begin((void __user *)ea, nb)) {
394 err = __copy_mem_in(dest, ea, nb, regs);
395 user_read_access_end();
404 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
405 unsigned long ea, int nb,
406 struct pt_regs *regs)
410 u8 b[sizeof(unsigned long)];
416 i = IS_BE ? sizeof(unsigned long) - nb : 0;
417 err = copy_mem_in(&u.b[i], ea, nb, regs);
424 * Read memory at address ea for nb bytes, return 0 for success
425 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
426 * If nb < sizeof(long), the result is right-justified on BE systems.
428 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
429 struct pt_regs *regs)
431 if (!address_ok(regs, ea, nb))
433 if ((ea & (nb - 1)) == 0)
434 return read_mem_aligned(dest, ea, nb, regs);
435 return read_mem_unaligned(dest, ea, nb, regs);
437 NOKPROBE_SYMBOL(read_mem);
439 static __always_inline int
440 __write_mem_aligned(unsigned long val, unsigned long ea, int nb, struct pt_regs *regs)
444 unsafe_put_user(val, (unsigned char __user *)ea, Efault);
447 unsafe_put_user(val, (unsigned short __user *)ea, Efault);
450 unsafe_put_user(val, (unsigned int __user *)ea, Efault);
454 unsafe_put_user(val, (unsigned long __user *)ea, Efault);
465 static nokprobe_inline int
466 write_mem_aligned(unsigned long val, unsigned long ea, int nb, struct pt_regs *regs)
470 if (is_kernel_addr(ea))
471 return __write_mem_aligned(val, ea, nb, regs);
473 if (user_write_access_begin((void __user *)ea, nb)) {
474 err = __write_mem_aligned(val, ea, nb, regs);
475 user_write_access_end();
485 * Copy from a buffer to userspace, using the largest possible
486 * aligned accesses, up to sizeof(long).
488 static nokprobe_inline int __copy_mem_out(u8 *dest, unsigned long ea, int nb, struct pt_regs *regs)
492 for (; nb > 0; nb -= c) {
498 unsafe_put_user(*dest, (u8 __user *)ea, Efault);
501 unsafe_put_user(*(u16 *)dest, (u16 __user *)ea, Efault);
504 unsafe_put_user(*(u32 *)dest, (u32 __user *)ea, Efault);
508 unsafe_put_user(*(u64 *)dest, (u64 __user *)ea, Efault);
522 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb, struct pt_regs *regs)
526 if (is_kernel_addr(ea))
527 return __copy_mem_out(dest, ea, nb, regs);
529 if (user_write_access_begin((void __user *)ea, nb)) {
530 err = __copy_mem_out(dest, ea, nb, regs);
531 user_write_access_end();
540 static nokprobe_inline int write_mem_unaligned(unsigned long val,
541 unsigned long ea, int nb,
542 struct pt_regs *regs)
546 u8 b[sizeof(unsigned long)];
551 i = IS_BE ? sizeof(unsigned long) - nb : 0;
552 return copy_mem_out(&u.b[i], ea, nb, regs);
556 * Write memory at address ea for nb bytes, return 0 for success
557 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
559 static int write_mem(unsigned long val, unsigned long ea, int nb,
560 struct pt_regs *regs)
562 if (!address_ok(regs, ea, nb))
564 if ((ea & (nb - 1)) == 0)
565 return write_mem_aligned(val, ea, nb, regs);
566 return write_mem_unaligned(val, ea, nb, regs);
568 NOKPROBE_SYMBOL(write_mem);
570 #ifdef CONFIG_PPC_FPU
572 * These access either the real FP register or the image in the
573 * thread_struct, depending on regs->msr & MSR_FP.
575 static int do_fp_load(struct instruction_op *op, unsigned long ea,
576 struct pt_regs *regs, bool cross_endian)
585 u8 b[2 * sizeof(double)];
588 nb = GETSIZE(op->type);
589 if (!address_ok(regs, ea, nb))
592 err = copy_mem_in(u.b, ea, nb, regs);
595 if (unlikely(cross_endian)) {
596 do_byte_reverse(u.b, min(nb, 8));
598 do_byte_reverse(&u.b[8], 8);
602 if (op->type & FPCONV)
603 conv_sp_to_dp(&u.f, &u.d[0]);
604 else if (op->type & SIGNEXT)
609 if (regs->msr & MSR_FP)
610 put_fpr(rn, &u.d[0]);
612 current->thread.TS_FPR(rn) = u.l[0];
616 if (regs->msr & MSR_FP)
617 put_fpr(rn, &u.d[1]);
619 current->thread.TS_FPR(rn) = u.l[1];
624 NOKPROBE_SYMBOL(do_fp_load);
626 static int do_fp_store(struct instruction_op *op, unsigned long ea,
627 struct pt_regs *regs, bool cross_endian)
635 u8 b[2 * sizeof(double)];
638 nb = GETSIZE(op->type);
639 if (!address_ok(regs, ea, nb))
643 if (regs->msr & MSR_FP)
644 get_fpr(rn, &u.d[0]);
646 u.l[0] = current->thread.TS_FPR(rn);
648 if (op->type & FPCONV)
649 conv_dp_to_sp(&u.d[0], &u.f);
655 if (regs->msr & MSR_FP)
656 get_fpr(rn, &u.d[1]);
658 u.l[1] = current->thread.TS_FPR(rn);
661 if (unlikely(cross_endian)) {
662 do_byte_reverse(u.b, min(nb, 8));
664 do_byte_reverse(&u.b[8], 8);
666 return copy_mem_out(u.b, ea, nb, regs);
668 NOKPROBE_SYMBOL(do_fp_store);
671 #ifdef CONFIG_ALTIVEC
672 /* For Altivec/VMX, no need to worry about alignment */
673 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
674 int size, struct pt_regs *regs,
680 u8 b[sizeof(__vector128)];
683 if (!address_ok(regs, ea & ~0xfUL, 16))
685 /* align to multiple of size */
687 err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
690 if (unlikely(cross_endian))
691 do_byte_reverse(&u.b[ea & 0xf], size);
693 if (regs->msr & MSR_VEC)
696 current->thread.vr_state.vr[rn] = u.v;
701 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
702 int size, struct pt_regs *regs,
707 u8 b[sizeof(__vector128)];
710 if (!address_ok(regs, ea & ~0xfUL, 16))
712 /* align to multiple of size */
716 if (regs->msr & MSR_VEC)
719 u.v = current->thread.vr_state.vr[rn];
721 if (unlikely(cross_endian))
722 do_byte_reverse(&u.b[ea & 0xf], size);
723 return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
725 #endif /* CONFIG_ALTIVEC */
728 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
729 int reg, bool cross_endian)
733 if (!address_ok(regs, ea, 16))
735 /* if aligned, should be atomic */
736 if ((ea & 0xf) == 0) {
737 err = do_lq(ea, ®s->gpr[reg]);
739 err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs);
741 err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs);
743 if (!err && unlikely(cross_endian))
744 do_byte_reverse(®s->gpr[reg], 16);
748 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
749 int reg, bool cross_endian)
752 unsigned long vals[2];
754 if (!address_ok(regs, ea, 16))
756 vals[0] = regs->gpr[reg];
757 vals[1] = regs->gpr[reg + 1];
758 if (unlikely(cross_endian))
759 do_byte_reverse(vals, 16);
761 /* if aligned, should be atomic */
763 return do_stq(ea, vals[0], vals[1]);
765 err = write_mem(vals[IS_LE], ea, 8, regs);
767 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
770 #endif /* __powerpc64 */
773 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
774 const void *mem, bool rev)
778 const unsigned int *wp;
779 const unsigned short *hp;
780 const unsigned char *bp;
782 size = GETSIZE(op->type);
783 reg->d[0] = reg->d[1] = 0;
785 switch (op->element_size) {
789 /* whole vector; lxv[x] or lxvl[l] */
792 memcpy(reg, mem, size);
793 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
796 do_byte_reverse(reg, size);
799 /* scalar loads, lxvd2x, lxvdsx */
800 read_size = (size >= 8) ? 8 : size;
801 i = IS_LE ? 8 : 8 - read_size;
802 memcpy(®->b[i], mem, read_size);
804 do_byte_reverse(®->b[i], 8);
806 if (op->type & SIGNEXT) {
807 /* size == 4 is the only case here */
808 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
809 } else if (op->vsx_flags & VSX_FPCONV) {
811 conv_sp_to_dp(®->fp[1 + IS_LE],
817 unsigned long v = *(unsigned long *)(mem + 8);
818 reg->d[IS_BE] = !rev ? v : byterev_8(v);
819 } else if (op->vsx_flags & VSX_SPLAT)
820 reg->d[IS_BE] = reg->d[IS_LE];
826 for (j = 0; j < size / 4; ++j) {
827 i = IS_LE ? 3 - j : j;
828 reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
830 if (op->vsx_flags & VSX_SPLAT) {
831 u32 val = reg->w[IS_LE ? 3 : 0];
833 i = IS_LE ? 3 - j : j;
841 for (j = 0; j < size / 2; ++j) {
842 i = IS_LE ? 7 - j : j;
843 reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
849 for (j = 0; j < size; ++j) {
850 i = IS_LE ? 15 - j : j;
856 EXPORT_SYMBOL_GPL(emulate_vsx_load);
857 NOKPROBE_SYMBOL(emulate_vsx_load);
859 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
862 int size, write_size;
869 size = GETSIZE(op->type);
871 switch (op->element_size) {
877 /* reverse 32 bytes */
878 union vsx_reg buf32[2];
879 buf32[0].d[0] = byterev_8(reg[1].d[1]);
880 buf32[0].d[1] = byterev_8(reg[1].d[0]);
881 buf32[1].d[0] = byterev_8(reg[0].d[1]);
882 buf32[1].d[1] = byterev_8(reg[0].d[0]);
883 memcpy(mem, buf32, size);
885 memcpy(mem, reg, size);
889 /* stxv, stxvx, stxvl, stxvll */
892 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
895 /* reverse 16 bytes */
896 buf.d[0] = byterev_8(reg->d[1]);
897 buf.d[1] = byterev_8(reg->d[0]);
900 memcpy(mem, reg, size);
903 /* scalar stores, stxvd2x */
904 write_size = (size >= 8) ? 8 : size;
905 i = IS_LE ? 8 : 8 - write_size;
906 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
907 buf.d[0] = buf.d[1] = 0;
909 conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]);
913 memcpy(mem, ®->b[i], write_size);
915 memcpy(mem + 8, ®->d[IS_BE], 8);
917 do_byte_reverse(mem, write_size);
919 do_byte_reverse(mem + 8, 8);
925 for (j = 0; j < size / 4; ++j) {
926 i = IS_LE ? 3 - j : j;
927 *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
933 for (j = 0; j < size / 2; ++j) {
934 i = IS_LE ? 7 - j : j;
935 *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
941 for (j = 0; j < size; ++j) {
942 i = IS_LE ? 15 - j : j;
948 EXPORT_SYMBOL_GPL(emulate_vsx_store);
949 NOKPROBE_SYMBOL(emulate_vsx_store);
951 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
952 unsigned long ea, struct pt_regs *regs,
956 int i, j, nr_vsx_regs;
958 union vsx_reg buf[2];
959 int size = GETSIZE(op->type);
961 if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
964 nr_vsx_regs = max(1ul, size / sizeof(__vector128));
965 emulate_vsx_load(op, buf, mem, cross_endian);
968 /* FP regs + extensions */
969 if (regs->msr & MSR_FP) {
970 for (i = 0; i < nr_vsx_regs; i++) {
971 j = IS_LE ? nr_vsx_regs - i - 1 : i;
972 load_vsrn(reg + i, &buf[j].v);
975 for (i = 0; i < nr_vsx_regs; i++) {
976 j = IS_LE ? nr_vsx_regs - i - 1 : i;
977 current->thread.fp_state.fpr[reg + i][0] = buf[j].d[0];
978 current->thread.fp_state.fpr[reg + i][1] = buf[j].d[1];
982 if (regs->msr & MSR_VEC) {
983 for (i = 0; i < nr_vsx_regs; i++) {
984 j = IS_LE ? nr_vsx_regs - i - 1 : i;
985 load_vsrn(reg + i, &buf[j].v);
988 for (i = 0; i < nr_vsx_regs; i++) {
989 j = IS_LE ? nr_vsx_regs - i - 1 : i;
990 current->thread.vr_state.vr[reg - 32 + i] = buf[j].v;
998 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
999 unsigned long ea, struct pt_regs *regs,
1003 int i, j, nr_vsx_regs;
1005 union vsx_reg buf[2];
1006 int size = GETSIZE(op->type);
1008 if (!address_ok(regs, ea, size))
1011 nr_vsx_regs = max(1ul, size / sizeof(__vector128));
1014 /* FP regs + extensions */
1015 if (regs->msr & MSR_FP) {
1016 for (i = 0; i < nr_vsx_regs; i++) {
1017 j = IS_LE ? nr_vsx_regs - i - 1 : i;
1018 store_vsrn(reg + i, &buf[j].v);
1021 for (i = 0; i < nr_vsx_regs; i++) {
1022 j = IS_LE ? nr_vsx_regs - i - 1 : i;
1023 buf[j].d[0] = current->thread.fp_state.fpr[reg + i][0];
1024 buf[j].d[1] = current->thread.fp_state.fpr[reg + i][1];
1028 if (regs->msr & MSR_VEC) {
1029 for (i = 0; i < nr_vsx_regs; i++) {
1030 j = IS_LE ? nr_vsx_regs - i - 1 : i;
1031 store_vsrn(reg + i, &buf[j].v);
1034 for (i = 0; i < nr_vsx_regs; i++) {
1035 j = IS_LE ? nr_vsx_regs - i - 1 : i;
1036 buf[j].v = current->thread.vr_state.vr[reg - 32 + i];
1041 emulate_vsx_store(op, buf, mem, cross_endian);
1042 return copy_mem_out(mem, ea, size, regs);
1044 #endif /* CONFIG_VSX */
1046 static int __emulate_dcbz(unsigned long ea)
1049 unsigned long size = l1_dcache_bytes();
1051 for (i = 0; i < size; i += sizeof(long))
1052 unsafe_put_user(0, (unsigned long __user *)(ea + i), Efault);
1060 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
1063 unsigned long size = l1_dcache_bytes();
1065 ea = truncate_if_32bit(regs->msr, ea);
1067 if (!address_ok(regs, ea, size))
1070 if (is_kernel_addr(ea)) {
1071 err = __emulate_dcbz(ea);
1072 } else if (user_write_access_begin((void __user *)ea, size)) {
1073 err = __emulate_dcbz(ea);
1074 user_write_access_end();
1085 NOKPROBE_SYMBOL(emulate_dcbz);
1087 #define __put_user_asmx(x, addr, err, op, cr) \
1088 __asm__ __volatile__( \
1090 ".machine power8\n" \
1091 "1: " op " %2,0,%3\n" \
1095 ".section .fixup,\"ax\"\n" \
1100 : "=r" (err), "=r" (cr) \
1101 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
1103 #define __get_user_asmx(x, addr, err, op) \
1104 __asm__ __volatile__( \
1106 ".machine power8\n" \
1107 "1: "op" %1,0,%2\n" \
1110 ".section .fixup,\"ax\"\n" \
1115 : "=r" (err), "=r" (x) \
1116 : "r" (addr), "i" (-EFAULT), "0" (err))
1118 #define __cacheop_user_asmx(addr, err, op) \
1119 __asm__ __volatile__( \
1122 ".section .fixup,\"ax\"\n" \
1128 : "r" (addr), "i" (-EFAULT), "0" (err))
1130 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
1131 struct instruction_op *op)
1136 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
1137 if (!(regs->msr & MSR_64BIT))
1140 op->ccval |= 0x80000000;
1142 op->ccval |= 0x40000000;
1144 op->ccval |= 0x20000000;
1147 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val)
1149 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1151 op->xerval |= XER_CA32;
1153 op->xerval &= ~XER_CA32;
1157 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
1158 struct instruction_op *op, int rd,
1159 unsigned long val1, unsigned long val2,
1160 unsigned long carry_in)
1162 unsigned long val = val1 + val2;
1166 op->type = COMPUTE | SETREG | SETXER;
1169 val = truncate_if_32bit(regs->msr, val);
1170 val1 = truncate_if_32bit(regs->msr, val1);
1171 op->xerval = regs->xer;
1172 if (val < val1 || (carry_in && val == val1))
1173 op->xerval |= XER_CA;
1175 op->xerval &= ~XER_CA;
1177 set_ca32(op, (unsigned int)val < (unsigned int)val1 ||
1178 (carry_in && (unsigned int)val == (unsigned int)val1));
1181 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
1182 struct instruction_op *op,
1183 long v1, long v2, int crfld)
1185 unsigned int crval, shift;
1187 op->type = COMPUTE | SETCC;
1188 crval = (regs->xer >> 31) & 1; /* get SO bit */
1195 shift = (7 - crfld) * 4;
1196 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1199 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1200 struct instruction_op *op,
1202 unsigned long v2, int crfld)
1204 unsigned int crval, shift;
1206 op->type = COMPUTE | SETCC;
1207 crval = (regs->xer >> 31) & 1; /* get SO bit */
1214 shift = (7 - crfld) * 4;
1215 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1218 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1219 struct instruction_op *op,
1220 unsigned long v1, unsigned long v2)
1222 unsigned long long out_val, mask;
1226 for (i = 0; i < 8; i++) {
1227 mask = 0xffUL << (i * 8);
1228 if ((v1 & mask) == (v2 & mask))
1235 * The size parameter is used to adjust the equivalent popcnt instruction.
1236 * popcntb = 8, popcntw = 32, popcntd = 64
1238 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1239 struct instruction_op *op,
1240 unsigned long v1, int size)
1242 unsigned long long out = v1;
1244 out -= (out >> 1) & 0x5555555555555555ULL;
1245 out = (0x3333333333333333ULL & out) +
1246 (0x3333333333333333ULL & (out >> 2));
1247 out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1249 if (size == 8) { /* popcntb */
1255 if (size == 32) { /* popcntw */
1256 op->val = out & 0x0000003f0000003fULL;
1260 out = (out + (out >> 32)) & 0x7f;
1261 op->val = out; /* popcntd */
1265 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1266 struct instruction_op *op,
1267 unsigned long v1, unsigned long v2)
1269 unsigned char perm, idx;
1273 for (i = 0; i < 8; i++) {
1274 idx = (v1 >> (i * 8)) & 0xff;
1276 if (v2 & PPC_BIT(idx))
1281 #endif /* CONFIG_PPC64 */
1283 * The size parameter adjusts the equivalent prty instruction.
1284 * prtyw = 32, prtyd = 64
1286 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1287 struct instruction_op *op,
1288 unsigned long v, int size)
1290 unsigned long long res = v ^ (v >> 8);
1293 if (size == 32) { /* prtyw */
1294 op->val = res & 0x0000000100000001ULL;
1299 op->val = res & 1; /*prtyd */
1302 static nokprobe_inline int trap_compare(long v1, long v2)
1312 if ((unsigned long)v1 < (unsigned long)v2)
1314 else if ((unsigned long)v1 > (unsigned long)v2)
1320 * Elements of 32-bit rotate and mask instructions.
1322 #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \
1323 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1324 #ifdef __powerpc64__
1325 #define MASK64_L(mb) (~0UL >> (mb))
1326 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me))
1327 #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1328 #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1330 #define DATA32(x) (x)
1332 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1335 * Decode an instruction, and return information about it in *op
1336 * without changing *regs.
1337 * Integer arithmetic and logical instructions, branches, and barrier
1338 * instructions can be emulated just using the information in *op.
1340 * Return value is 1 if the instruction can be emulated just by
1341 * updating *regs with the information in *op, -1 if we need the
1342 * GPRs but *regs doesn't contain the full register set, or 0
1345 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1349 unsigned int suffixopcode, prefixtype, prefix_r;
1351 unsigned int opcode, ra, rb, rc, rd, spr, u;
1352 unsigned long int imm;
1353 unsigned long int val, val2;
1354 unsigned int mb, me, sh;
1355 unsigned int word, suffix;
1358 word = ppc_inst_val(instr);
1359 suffix = ppc_inst_suffix(instr);
1363 opcode = ppc_inst_primary_opcode(instr);
1367 imm = (signed short)(word & 0xfffc);
1368 if ((word & 2) == 0)
1370 op->val = truncate_if_32bit(regs->msr, imm);
1373 if (branch_taken(word, regs, op))
1374 op->type |= BRTAKEN;
1377 if ((word & 0xfe2) == 2)
1379 else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) &&
1380 (word & 0xfe3) == 1) { /* scv */
1381 op->type = SYSCALL_VECTORED_0;
1382 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1383 goto unknown_opcode;
1388 op->type = BRANCH | BRTAKEN;
1389 imm = word & 0x03fffffc;
1390 if (imm & 0x02000000)
1392 if ((word & 2) == 0)
1394 op->val = truncate_if_32bit(regs->msr, imm);
1399 switch ((word >> 1) & 0x3ff) {
1401 op->type = COMPUTE + SETCC;
1402 rd = 7 - ((word >> 23) & 0x7);
1403 ra = 7 - ((word >> 18) & 0x7);
1406 val = (regs->ccr >> ra) & 0xf;
1407 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1411 case 528: /* bcctr */
1413 imm = (word & 0x400)? regs->ctr: regs->link;
1414 op->val = truncate_if_32bit(regs->msr, imm);
1417 if (branch_taken(word, regs, op))
1418 op->type |= BRTAKEN;
1421 case 18: /* rfid, scary */
1422 if (regs->msr & MSR_PR)
1427 case 150: /* isync */
1428 op->type = BARRIER | BARRIER_ISYNC;
1431 case 33: /* crnor */
1432 case 129: /* crandc */
1433 case 193: /* crxor */
1434 case 225: /* crnand */
1435 case 257: /* crand */
1436 case 289: /* creqv */
1437 case 417: /* crorc */
1438 case 449: /* cror */
1439 op->type = COMPUTE + SETCC;
1440 ra = (word >> 16) & 0x1f;
1441 rb = (word >> 11) & 0x1f;
1442 rd = (word >> 21) & 0x1f;
1443 ra = (regs->ccr >> (31 - ra)) & 1;
1444 rb = (regs->ccr >> (31 - rb)) & 1;
1445 val = (word >> (6 + ra * 2 + rb)) & 1;
1446 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1452 switch ((word >> 1) & 0x3ff) {
1453 case 598: /* sync */
1454 op->type = BARRIER + BARRIER_SYNC;
1455 #ifdef __powerpc64__
1456 switch ((word >> 21) & 3) {
1457 case 1: /* lwsync */
1458 op->type = BARRIER + BARRIER_LWSYNC;
1460 case 2: /* ptesync */
1461 op->type = BARRIER + BARRIER_PTESYNC;
1467 case 854: /* eieio */
1468 op->type = BARRIER + BARRIER_EIEIO;
1474 rd = (word >> 21) & 0x1f;
1475 ra = (word >> 16) & 0x1f;
1476 rb = (word >> 11) & 0x1f;
1477 rc = (word >> 6) & 0x1f;
1480 #ifdef __powerpc64__
1482 if (!cpu_has_feature(CPU_FTR_ARCH_31))
1483 goto unknown_opcode;
1485 prefix_r = GET_PREFIX_R(word);
1486 ra = GET_PREFIX_RA(suffix);
1487 rd = (suffix >> 21) & 0x1f;
1489 op->val = regs->gpr[rd];
1490 suffixopcode = get_op(suffix);
1491 prefixtype = (word >> 24) & 0x3;
1492 switch (prefixtype) {
1496 switch (suffixopcode) {
1497 case 14: /* paddi */
1498 op->type = COMPUTE | PREFIXED;
1499 op->val = mlsd_8lsd_ea(word, suffix, regs);
1505 if (rd & trap_compare(regs->gpr[ra], (short) word))
1510 if (rd & trap_compare((int)regs->gpr[ra], (short) word))
1514 #ifdef __powerpc64__
1517 * There are very many instructions with this primary opcode
1518 * introduced in the ISA as early as v2.03. However, the ones
1519 * we currently emulate were all introduced with ISA 3.0
1521 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1522 goto unknown_opcode;
1524 switch (word & 0x3f) {
1525 case 48: /* maddhd */
1526 asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
1527 "=r" (op->val) : "r" (regs->gpr[ra]),
1528 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1531 case 49: /* maddhdu */
1532 asm volatile(PPC_MADDHDU(%0, %1, %2, %3) :
1533 "=r" (op->val) : "r" (regs->gpr[ra]),
1534 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1537 case 51: /* maddld */
1538 asm volatile(PPC_MADDLD(%0, %1, %2, %3) :
1539 "=r" (op->val) : "r" (regs->gpr[ra]),
1540 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1545 * There are other instructions from ISA 3.0 with the same
1546 * primary opcode which do not have emulation support yet.
1548 goto unknown_opcode;
1552 op->val = regs->gpr[ra] * (short) word;
1555 case 8: /* subfic */
1557 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1560 case 10: /* cmpli */
1561 imm = (unsigned short) word;
1562 val = regs->gpr[ra];
1563 #ifdef __powerpc64__
1565 val = (unsigned int) val;
1567 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1572 val = regs->gpr[ra];
1573 #ifdef __powerpc64__
1577 do_cmp_signed(regs, op, val, imm, rd >> 2);
1580 case 12: /* addic */
1582 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1585 case 13: /* addic. */
1587 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1594 imm += regs->gpr[ra];
1598 case 15: /* addis */
1599 imm = ((short) word) << 16;
1601 imm += regs->gpr[ra];
1606 if (((word >> 1) & 0x1f) == 2) {
1608 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1609 goto unknown_opcode;
1610 imm = (short) (word & 0xffc1); /* d0 + d2 fields */
1611 imm |= (word >> 15) & 0x3e; /* d1 field */
1612 op->val = regs->nip + (imm << 16) + 4;
1618 case 20: /* rlwimi */
1619 mb = (word >> 6) & 0x1f;
1620 me = (word >> 1) & 0x1f;
1621 val = DATA32(regs->gpr[rd]);
1622 imm = MASK32(mb, me);
1623 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1626 case 21: /* rlwinm */
1627 mb = (word >> 6) & 0x1f;
1628 me = (word >> 1) & 0x1f;
1629 val = DATA32(regs->gpr[rd]);
1630 op->val = ROTATE(val, rb) & MASK32(mb, me);
1633 case 23: /* rlwnm */
1634 mb = (word >> 6) & 0x1f;
1635 me = (word >> 1) & 0x1f;
1636 rb = regs->gpr[rb] & 0x1f;
1637 val = DATA32(regs->gpr[rd]);
1638 op->val = ROTATE(val, rb) & MASK32(mb, me);
1642 op->val = regs->gpr[rd] | (unsigned short) word;
1643 goto logical_done_nocc;
1646 imm = (unsigned short) word;
1647 op->val = regs->gpr[rd] | (imm << 16);
1648 goto logical_done_nocc;
1651 op->val = regs->gpr[rd] ^ (unsigned short) word;
1652 goto logical_done_nocc;
1654 case 27: /* xoris */
1655 imm = (unsigned short) word;
1656 op->val = regs->gpr[rd] ^ (imm << 16);
1657 goto logical_done_nocc;
1659 case 28: /* andi. */
1660 op->val = regs->gpr[rd] & (unsigned short) word;
1662 goto logical_done_nocc;
1664 case 29: /* andis. */
1665 imm = (unsigned short) word;
1666 op->val = regs->gpr[rd] & (imm << 16);
1668 goto logical_done_nocc;
1670 #ifdef __powerpc64__
1672 mb = ((word >> 6) & 0x1f) | (word & 0x20);
1673 val = regs->gpr[rd];
1674 if ((word & 0x10) == 0) {
1675 sh = rb | ((word & 2) << 4);
1676 val = ROTATE(val, sh);
1677 switch ((word >> 2) & 3) {
1678 case 0: /* rldicl */
1679 val &= MASK64_L(mb);
1681 case 1: /* rldicr */
1682 val &= MASK64_R(mb);
1685 val &= MASK64(mb, 63 - sh);
1687 case 3: /* rldimi */
1688 imm = MASK64(mb, 63 - sh);
1689 val = (regs->gpr[ra] & ~imm) |
1695 sh = regs->gpr[rb] & 0x3f;
1696 val = ROTATE(val, sh);
1697 switch ((word >> 1) & 7) {
1699 op->val = val & MASK64_L(mb);
1702 op->val = val & MASK64_R(mb);
1707 op->type = UNKNOWN; /* illegal instruction */
1711 /* isel occupies 32 minor opcodes */
1712 if (((word >> 1) & 0x1f) == 15) {
1713 mb = (word >> 6) & 0x1f; /* bc field */
1714 val = (regs->ccr >> (31 - mb)) & 1;
1715 val2 = (ra) ? regs->gpr[ra] : 0;
1717 op->val = (val) ? val2 : regs->gpr[rb];
1721 switch ((word >> 1) & 0x3ff) {
1724 (rd & trap_compare((int)regs->gpr[ra],
1725 (int)regs->gpr[rb])))
1728 #ifdef __powerpc64__
1730 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1734 case 83: /* mfmsr */
1735 if (regs->msr & MSR_PR)
1740 case 146: /* mtmsr */
1741 if (regs->msr & MSR_PR)
1745 op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1748 case 178: /* mtmsrd */
1749 if (regs->msr & MSR_PR)
1753 /* only MSR_EE and MSR_RI get changed if bit 15 set */
1754 /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1755 imm = (word & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1762 if ((word >> 20) & 1) {
1764 for (sh = 0; sh < 8; ++sh) {
1765 if (word & (0x80000 >> sh))
1770 op->val = regs->ccr & imm;
1773 case 128: /* setb */
1774 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1775 goto unknown_opcode;
1777 * 'ra' encodes the CR field number (bfa) in the top 3 bits.
1778 * Since each CR field is 4 bits,
1779 * we can simply mask off the bottom two bits (bfa * 4)
1780 * to yield the first bit in the CR field.
1783 /* 'val' stores bits of the CR field (bfa) */
1784 val = regs->ccr >> (CR0_SHIFT - ra);
1785 /* checks if the LT bit of CR field (bfa) is set */
1788 /* checks if the GT bit of CR field (bfa) is set */
1795 case 144: /* mtcrf */
1796 op->type = COMPUTE + SETCC;
1798 val = regs->gpr[rd];
1799 op->ccval = regs->ccr;
1800 for (sh = 0; sh < 8; ++sh) {
1801 if (word & (0x80000 >> sh))
1802 op->ccval = (op->ccval & ~imm) |
1808 case 339: /* mfspr */
1809 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1813 if (spr == SPRN_XER || spr == SPRN_LR ||
1818 case 467: /* mtspr */
1819 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1821 op->val = regs->gpr[rd];
1823 if (spr == SPRN_XER || spr == SPRN_LR ||
1829 * Compare instructions
1832 val = regs->gpr[ra];
1833 val2 = regs->gpr[rb];
1834 #ifdef __powerpc64__
1835 if ((rd & 1) == 0) {
1836 /* word (32-bit) compare */
1841 do_cmp_signed(regs, op, val, val2, rd >> 2);
1845 val = regs->gpr[ra];
1846 val2 = regs->gpr[rb];
1847 #ifdef __powerpc64__
1848 if ((rd & 1) == 0) {
1849 /* word (32-bit) compare */
1850 val = (unsigned int) val;
1851 val2 = (unsigned int) val2;
1854 do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1857 case 508: /* cmpb */
1858 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1859 goto logical_done_nocc;
1862 * Arithmetic instructions
1865 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1868 #ifdef __powerpc64__
1869 case 9: /* mulhdu */
1870 asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1871 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1875 add_with_carry(regs, op, rd, regs->gpr[ra],
1879 case 11: /* mulhwu */
1880 asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1881 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1885 op->val = regs->gpr[rb] - regs->gpr[ra];
1887 #ifdef __powerpc64__
1888 case 73: /* mulhd */
1889 asm("mulhd %0,%1,%2" : "=r" (op->val) :
1890 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1893 case 75: /* mulhw */
1894 asm("mulhw %0,%1,%2" : "=r" (op->val) :
1895 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1899 op->val = -regs->gpr[ra];
1902 case 136: /* subfe */
1903 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1904 regs->gpr[rb], regs->xer & XER_CA);
1907 case 138: /* adde */
1908 add_with_carry(regs, op, rd, regs->gpr[ra],
1909 regs->gpr[rb], regs->xer & XER_CA);
1912 case 200: /* subfze */
1913 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1914 regs->xer & XER_CA);
1917 case 202: /* addze */
1918 add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1919 regs->xer & XER_CA);
1922 case 232: /* subfme */
1923 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1924 regs->xer & XER_CA);
1926 #ifdef __powerpc64__
1927 case 233: /* mulld */
1928 op->val = regs->gpr[ra] * regs->gpr[rb];
1931 case 234: /* addme */
1932 add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1933 regs->xer & XER_CA);
1936 case 235: /* mullw */
1937 op->val = (long)(int) regs->gpr[ra] *
1938 (int) regs->gpr[rb];
1941 #ifdef __powerpc64__
1942 case 265: /* modud */
1943 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1944 goto unknown_opcode;
1945 op->val = regs->gpr[ra] % regs->gpr[rb];
1949 op->val = regs->gpr[ra] + regs->gpr[rb];
1952 case 267: /* moduw */
1953 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1954 goto unknown_opcode;
1955 op->val = (unsigned int) regs->gpr[ra] %
1956 (unsigned int) regs->gpr[rb];
1958 #ifdef __powerpc64__
1959 case 457: /* divdu */
1960 op->val = regs->gpr[ra] / regs->gpr[rb];
1963 case 459: /* divwu */
1964 op->val = (unsigned int) regs->gpr[ra] /
1965 (unsigned int) regs->gpr[rb];
1967 #ifdef __powerpc64__
1968 case 489: /* divd */
1969 op->val = (long int) regs->gpr[ra] /
1970 (long int) regs->gpr[rb];
1973 case 491: /* divw */
1974 op->val = (int) regs->gpr[ra] /
1975 (int) regs->gpr[rb];
1977 #ifdef __powerpc64__
1978 case 425: /* divde[.] */
1979 asm volatile(PPC_DIVDE(%0, %1, %2) :
1980 "=r" (op->val) : "r" (regs->gpr[ra]),
1981 "r" (regs->gpr[rb]));
1983 case 393: /* divdeu[.] */
1984 asm volatile(PPC_DIVDEU(%0, %1, %2) :
1985 "=r" (op->val) : "r" (regs->gpr[ra]),
1986 "r" (regs->gpr[rb]));
1989 case 755: /* darn */
1990 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1991 goto unknown_opcode;
1994 /* 32-bit conditioned */
1995 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val));
1999 /* 64-bit conditioned */
2000 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val));
2005 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val));
2009 goto unknown_opcode;
2010 #ifdef __powerpc64__
2011 case 777: /* modsd */
2012 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2013 goto unknown_opcode;
2014 op->val = (long int) regs->gpr[ra] %
2015 (long int) regs->gpr[rb];
2018 case 779: /* modsw */
2019 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2020 goto unknown_opcode;
2021 op->val = (int) regs->gpr[ra] %
2022 (int) regs->gpr[rb];
2027 * Logical instructions
2029 case 26: /* cntlzw */
2030 val = (unsigned int) regs->gpr[rd];
2031 op->val = ( val ? __builtin_clz(val) : 32 );
2033 #ifdef __powerpc64__
2034 case 58: /* cntlzd */
2035 val = regs->gpr[rd];
2036 op->val = ( val ? __builtin_clzl(val) : 64 );
2040 op->val = regs->gpr[rd] & regs->gpr[rb];
2044 op->val = regs->gpr[rd] & ~regs->gpr[rb];
2047 case 122: /* popcntb */
2048 do_popcnt(regs, op, regs->gpr[rd], 8);
2049 goto logical_done_nocc;
2052 op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
2055 case 154: /* prtyw */
2056 do_prty(regs, op, regs->gpr[rd], 32);
2057 goto logical_done_nocc;
2059 case 186: /* prtyd */
2060 do_prty(regs, op, regs->gpr[rd], 64);
2061 goto logical_done_nocc;
2063 case 252: /* bpermd */
2064 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
2065 goto logical_done_nocc;
2068 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
2072 op->val = regs->gpr[rd] ^ regs->gpr[rb];
2075 case 378: /* popcntw */
2076 do_popcnt(regs, op, regs->gpr[rd], 32);
2077 goto logical_done_nocc;
2080 op->val = regs->gpr[rd] | ~regs->gpr[rb];
2084 op->val = regs->gpr[rd] | regs->gpr[rb];
2087 case 476: /* nand */
2088 op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
2091 case 506: /* popcntd */
2092 do_popcnt(regs, op, regs->gpr[rd], 64);
2093 goto logical_done_nocc;
2095 case 538: /* cnttzw */
2096 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2097 goto unknown_opcode;
2098 val = (unsigned int) regs->gpr[rd];
2099 op->val = (val ? __builtin_ctz(val) : 32);
2101 #ifdef __powerpc64__
2102 case 570: /* cnttzd */
2103 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2104 goto unknown_opcode;
2105 val = regs->gpr[rd];
2106 op->val = (val ? __builtin_ctzl(val) : 64);
2109 case 922: /* extsh */
2110 op->val = (signed short) regs->gpr[rd];
2113 case 954: /* extsb */
2114 op->val = (signed char) regs->gpr[rd];
2116 #ifdef __powerpc64__
2117 case 986: /* extsw */
2118 op->val = (signed int) regs->gpr[rd];
2123 * Shift instructions
2126 sh = regs->gpr[rb] & 0x3f;
2128 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
2134 sh = regs->gpr[rb] & 0x3f;
2136 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
2141 case 792: /* sraw */
2142 op->type = COMPUTE + SETREG + SETXER;
2143 sh = regs->gpr[rb] & 0x3f;
2144 ival = (signed int) regs->gpr[rd];
2145 op->val = ival >> (sh < 32 ? sh : 31);
2146 op->xerval = regs->xer;
2147 if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
2148 op->xerval |= XER_CA;
2150 op->xerval &= ~XER_CA;
2151 set_ca32(op, op->xerval & XER_CA);
2154 case 824: /* srawi */
2155 op->type = COMPUTE + SETREG + SETXER;
2157 ival = (signed int) regs->gpr[rd];
2158 op->val = ival >> sh;
2159 op->xerval = regs->xer;
2160 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2161 op->xerval |= XER_CA;
2163 op->xerval &= ~XER_CA;
2164 set_ca32(op, op->xerval & XER_CA);
2167 #ifdef __powerpc64__
2169 sh = regs->gpr[rb] & 0x7f;
2171 op->val = regs->gpr[rd] << sh;
2177 sh = regs->gpr[rb] & 0x7f;
2179 op->val = regs->gpr[rd] >> sh;
2184 case 794: /* srad */
2185 op->type = COMPUTE + SETREG + SETXER;
2186 sh = regs->gpr[rb] & 0x7f;
2187 ival = (signed long int) regs->gpr[rd];
2188 op->val = ival >> (sh < 64 ? sh : 63);
2189 op->xerval = regs->xer;
2190 if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
2191 op->xerval |= XER_CA;
2193 op->xerval &= ~XER_CA;
2194 set_ca32(op, op->xerval & XER_CA);
2197 case 826: /* sradi with sh_5 = 0 */
2198 case 827: /* sradi with sh_5 = 1 */
2199 op->type = COMPUTE + SETREG + SETXER;
2200 sh = rb | ((word & 2) << 4);
2201 ival = (signed long int) regs->gpr[rd];
2202 op->val = ival >> sh;
2203 op->xerval = regs->xer;
2204 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2205 op->xerval |= XER_CA;
2207 op->xerval &= ~XER_CA;
2208 set_ca32(op, op->xerval & XER_CA);
2211 case 890: /* extswsli with sh_5 = 0 */
2212 case 891: /* extswsli with sh_5 = 1 */
2213 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2214 goto unknown_opcode;
2215 op->type = COMPUTE + SETREG;
2216 sh = rb | ((word & 2) << 4);
2217 val = (signed int) regs->gpr[rd];
2219 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
2224 #endif /* __powerpc64__ */
2227 * Cache instructions
2229 case 54: /* dcbst */
2230 op->type = MKOP(CACHEOP, DCBST, 0);
2231 op->ea = xform_ea(word, regs);
2235 op->type = MKOP(CACHEOP, DCBF, 0);
2236 op->ea = xform_ea(word, regs);
2239 case 246: /* dcbtst */
2240 op->type = MKOP(CACHEOP, DCBTST, 0);
2241 op->ea = xform_ea(word, regs);
2245 case 278: /* dcbt */
2246 op->type = MKOP(CACHEOP, DCBTST, 0);
2247 op->ea = xform_ea(word, regs);
2251 case 982: /* icbi */
2252 op->type = MKOP(CACHEOP, ICBI, 0);
2253 op->ea = xform_ea(word, regs);
2256 case 1014: /* dcbz */
2257 op->type = MKOP(CACHEOP, DCBZ, 0);
2258 op->ea = xform_ea(word, regs);
2268 op->update_reg = ra;
2270 op->val = regs->gpr[rd];
2271 u = (word >> 20) & UPDATE;
2277 op->ea = xform_ea(word, regs);
2278 switch ((word >> 1) & 0x3ff) {
2279 case 20: /* lwarx */
2280 op->type = MKOP(LARX, 0, 4);
2283 case 150: /* stwcx. */
2284 op->type = MKOP(STCX, 0, 4);
2287 #ifdef CONFIG_PPC_HAS_LBARX_LHARX
2288 case 52: /* lbarx */
2289 op->type = MKOP(LARX, 0, 1);
2292 case 694: /* stbcx. */
2293 op->type = MKOP(STCX, 0, 1);
2296 case 116: /* lharx */
2297 op->type = MKOP(LARX, 0, 2);
2300 case 726: /* sthcx. */
2301 op->type = MKOP(STCX, 0, 2);
2304 #ifdef __powerpc64__
2305 case 84: /* ldarx */
2306 op->type = MKOP(LARX, 0, 8);
2309 case 214: /* stdcx. */
2310 op->type = MKOP(STCX, 0, 8);
2313 case 276: /* lqarx */
2314 if (!((rd & 1) || rd == ra || rd == rb))
2315 op->type = MKOP(LARX, 0, 16);
2318 case 182: /* stqcx. */
2320 op->type = MKOP(STCX, 0, 16);
2325 case 55: /* lwzux */
2326 op->type = MKOP(LOAD, u, 4);
2330 case 119: /* lbzux */
2331 op->type = MKOP(LOAD, u, 1);
2334 #ifdef CONFIG_ALTIVEC
2336 * Note: for the load/store vector element instructions,
2337 * bits of the EA say which field of the VMX register to use.
2340 op->type = MKOP(LOAD_VMX, 0, 1);
2341 op->element_size = 1;
2344 case 39: /* lvehx */
2345 op->type = MKOP(LOAD_VMX, 0, 2);
2346 op->element_size = 2;
2349 case 71: /* lvewx */
2350 op->type = MKOP(LOAD_VMX, 0, 4);
2351 op->element_size = 4;
2355 case 359: /* lvxl */
2356 op->type = MKOP(LOAD_VMX, 0, 16);
2357 op->element_size = 16;
2360 case 135: /* stvebx */
2361 op->type = MKOP(STORE_VMX, 0, 1);
2362 op->element_size = 1;
2365 case 167: /* stvehx */
2366 op->type = MKOP(STORE_VMX, 0, 2);
2367 op->element_size = 2;
2370 case 199: /* stvewx */
2371 op->type = MKOP(STORE_VMX, 0, 4);
2372 op->element_size = 4;
2375 case 231: /* stvx */
2376 case 487: /* stvxl */
2377 op->type = MKOP(STORE_VMX, 0, 16);
2379 #endif /* CONFIG_ALTIVEC */
2381 #ifdef __powerpc64__
2384 op->type = MKOP(LOAD, u, 8);
2387 case 149: /* stdx */
2388 case 181: /* stdux */
2389 op->type = MKOP(STORE, u, 8);
2393 case 151: /* stwx */
2394 case 183: /* stwux */
2395 op->type = MKOP(STORE, u, 4);
2398 case 215: /* stbx */
2399 case 247: /* stbux */
2400 op->type = MKOP(STORE, u, 1);
2403 case 279: /* lhzx */
2404 case 311: /* lhzux */
2405 op->type = MKOP(LOAD, u, 2);
2408 #ifdef __powerpc64__
2409 case 341: /* lwax */
2410 case 373: /* lwaux */
2411 op->type = MKOP(LOAD, SIGNEXT | u, 4);
2415 case 343: /* lhax */
2416 case 375: /* lhaux */
2417 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2420 case 407: /* sthx */
2421 case 439: /* sthux */
2422 op->type = MKOP(STORE, u, 2);
2425 #ifdef __powerpc64__
2426 case 532: /* ldbrx */
2427 op->type = MKOP(LOAD, BYTEREV, 8);
2431 case 533: /* lswx */
2432 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2435 case 534: /* lwbrx */
2436 op->type = MKOP(LOAD, BYTEREV, 4);
2439 case 597: /* lswi */
2441 rb = 32; /* # bytes to load */
2442 op->type = MKOP(LOAD_MULTI, 0, rb);
2443 op->ea = ra ? regs->gpr[ra] : 0;
2446 #ifdef CONFIG_PPC_FPU
2447 case 535: /* lfsx */
2448 case 567: /* lfsux */
2449 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2452 case 599: /* lfdx */
2453 case 631: /* lfdux */
2454 op->type = MKOP(LOAD_FP, u, 8);
2457 case 663: /* stfsx */
2458 case 695: /* stfsux */
2459 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2462 case 727: /* stfdx */
2463 case 759: /* stfdux */
2464 op->type = MKOP(STORE_FP, u, 8);
2467 #ifdef __powerpc64__
2468 case 791: /* lfdpx */
2469 op->type = MKOP(LOAD_FP, 0, 16);
2472 case 855: /* lfiwax */
2473 op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2476 case 887: /* lfiwzx */
2477 op->type = MKOP(LOAD_FP, 0, 4);
2480 case 919: /* stfdpx */
2481 op->type = MKOP(STORE_FP, 0, 16);
2484 case 983: /* stfiwx */
2485 op->type = MKOP(STORE_FP, 0, 4);
2487 #endif /* __powerpc64 */
2488 #endif /* CONFIG_PPC_FPU */
2490 #ifdef __powerpc64__
2491 case 660: /* stdbrx */
2492 op->type = MKOP(STORE, BYTEREV, 8);
2493 op->val = byterev_8(regs->gpr[rd]);
2497 case 661: /* stswx */
2498 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2501 case 662: /* stwbrx */
2502 op->type = MKOP(STORE, BYTEREV, 4);
2503 op->val = byterev_4(regs->gpr[rd]);
2506 case 725: /* stswi */
2508 rb = 32; /* # bytes to store */
2509 op->type = MKOP(STORE_MULTI, 0, rb);
2510 op->ea = ra ? regs->gpr[ra] : 0;
2513 case 790: /* lhbrx */
2514 op->type = MKOP(LOAD, BYTEREV, 2);
2517 case 918: /* sthbrx */
2518 op->type = MKOP(STORE, BYTEREV, 2);
2519 op->val = byterev_2(regs->gpr[rd]);
2523 case 12: /* lxsiwzx */
2524 op->reg = rd | ((word & 1) << 5);
2525 op->type = MKOP(LOAD_VSX, 0, 4);
2526 op->element_size = 8;
2529 case 76: /* lxsiwax */
2530 op->reg = rd | ((word & 1) << 5);
2531 op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2532 op->element_size = 8;
2535 case 140: /* stxsiwx */
2536 op->reg = rd | ((word & 1) << 5);
2537 op->type = MKOP(STORE_VSX, 0, 4);
2538 op->element_size = 8;
2541 case 268: /* lxvx */
2542 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2543 goto unknown_opcode;
2544 op->reg = rd | ((word & 1) << 5);
2545 op->type = MKOP(LOAD_VSX, 0, 16);
2546 op->element_size = 16;
2547 op->vsx_flags = VSX_CHECK_VEC;
2550 case 269: /* lxvl */
2551 case 301: { /* lxvll */
2553 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2554 goto unknown_opcode;
2555 op->reg = rd | ((word & 1) << 5);
2556 op->ea = ra ? regs->gpr[ra] : 0;
2557 nb = regs->gpr[rb] & 0xff;
2560 op->type = MKOP(LOAD_VSX, 0, nb);
2561 op->element_size = 16;
2562 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2566 case 332: /* lxvdsx */
2567 op->reg = rd | ((word & 1) << 5);
2568 op->type = MKOP(LOAD_VSX, 0, 8);
2569 op->element_size = 8;
2570 op->vsx_flags = VSX_SPLAT;
2573 case 333: /* lxvpx */
2574 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2575 goto unknown_opcode;
2576 op->reg = VSX_REGISTER_XTP(rd);
2577 op->type = MKOP(LOAD_VSX, 0, 32);
2578 op->element_size = 32;
2581 case 364: /* lxvwsx */
2582 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2583 goto unknown_opcode;
2584 op->reg = rd | ((word & 1) << 5);
2585 op->type = MKOP(LOAD_VSX, 0, 4);
2586 op->element_size = 4;
2587 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2590 case 396: /* stxvx */
2591 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2592 goto unknown_opcode;
2593 op->reg = rd | ((word & 1) << 5);
2594 op->type = MKOP(STORE_VSX, 0, 16);
2595 op->element_size = 16;
2596 op->vsx_flags = VSX_CHECK_VEC;
2599 case 397: /* stxvl */
2600 case 429: { /* stxvll */
2602 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2603 goto unknown_opcode;
2604 op->reg = rd | ((word & 1) << 5);
2605 op->ea = ra ? regs->gpr[ra] : 0;
2606 nb = regs->gpr[rb] & 0xff;
2609 op->type = MKOP(STORE_VSX, 0, nb);
2610 op->element_size = 16;
2611 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2615 case 461: /* stxvpx */
2616 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2617 goto unknown_opcode;
2618 op->reg = VSX_REGISTER_XTP(rd);
2619 op->type = MKOP(STORE_VSX, 0, 32);
2620 op->element_size = 32;
2622 case 524: /* lxsspx */
2623 op->reg = rd | ((word & 1) << 5);
2624 op->type = MKOP(LOAD_VSX, 0, 4);
2625 op->element_size = 8;
2626 op->vsx_flags = VSX_FPCONV;
2629 case 588: /* lxsdx */
2630 op->reg = rd | ((word & 1) << 5);
2631 op->type = MKOP(LOAD_VSX, 0, 8);
2632 op->element_size = 8;
2635 case 652: /* stxsspx */
2636 op->reg = rd | ((word & 1) << 5);
2637 op->type = MKOP(STORE_VSX, 0, 4);
2638 op->element_size = 8;
2639 op->vsx_flags = VSX_FPCONV;
2642 case 716: /* stxsdx */
2643 op->reg = rd | ((word & 1) << 5);
2644 op->type = MKOP(STORE_VSX, 0, 8);
2645 op->element_size = 8;
2648 case 780: /* lxvw4x */
2649 op->reg = rd | ((word & 1) << 5);
2650 op->type = MKOP(LOAD_VSX, 0, 16);
2651 op->element_size = 4;
2654 case 781: /* lxsibzx */
2655 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2656 goto unknown_opcode;
2657 op->reg = rd | ((word & 1) << 5);
2658 op->type = MKOP(LOAD_VSX, 0, 1);
2659 op->element_size = 8;
2660 op->vsx_flags = VSX_CHECK_VEC;
2663 case 812: /* lxvh8x */
2664 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2665 goto unknown_opcode;
2666 op->reg = rd | ((word & 1) << 5);
2667 op->type = MKOP(LOAD_VSX, 0, 16);
2668 op->element_size = 2;
2669 op->vsx_flags = VSX_CHECK_VEC;
2672 case 813: /* lxsihzx */
2673 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2674 goto unknown_opcode;
2675 op->reg = rd | ((word & 1) << 5);
2676 op->type = MKOP(LOAD_VSX, 0, 2);
2677 op->element_size = 8;
2678 op->vsx_flags = VSX_CHECK_VEC;
2681 case 844: /* lxvd2x */
2682 op->reg = rd | ((word & 1) << 5);
2683 op->type = MKOP(LOAD_VSX, 0, 16);
2684 op->element_size = 8;
2687 case 876: /* lxvb16x */
2688 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2689 goto unknown_opcode;
2690 op->reg = rd | ((word & 1) << 5);
2691 op->type = MKOP(LOAD_VSX, 0, 16);
2692 op->element_size = 1;
2693 op->vsx_flags = VSX_CHECK_VEC;
2696 case 908: /* stxvw4x */
2697 op->reg = rd | ((word & 1) << 5);
2698 op->type = MKOP(STORE_VSX, 0, 16);
2699 op->element_size = 4;
2702 case 909: /* stxsibx */
2703 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2704 goto unknown_opcode;
2705 op->reg = rd | ((word & 1) << 5);
2706 op->type = MKOP(STORE_VSX, 0, 1);
2707 op->element_size = 8;
2708 op->vsx_flags = VSX_CHECK_VEC;
2711 case 940: /* stxvh8x */
2712 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2713 goto unknown_opcode;
2714 op->reg = rd | ((word & 1) << 5);
2715 op->type = MKOP(STORE_VSX, 0, 16);
2716 op->element_size = 2;
2717 op->vsx_flags = VSX_CHECK_VEC;
2720 case 941: /* stxsihx */
2721 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2722 goto unknown_opcode;
2723 op->reg = rd | ((word & 1) << 5);
2724 op->type = MKOP(STORE_VSX, 0, 2);
2725 op->element_size = 8;
2726 op->vsx_flags = VSX_CHECK_VEC;
2729 case 972: /* stxvd2x */
2730 op->reg = rd | ((word & 1) << 5);
2731 op->type = MKOP(STORE_VSX, 0, 16);
2732 op->element_size = 8;
2735 case 1004: /* stxvb16x */
2736 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2737 goto unknown_opcode;
2738 op->reg = rd | ((word & 1) << 5);
2739 op->type = MKOP(STORE_VSX, 0, 16);
2740 op->element_size = 1;
2741 op->vsx_flags = VSX_CHECK_VEC;
2744 #endif /* CONFIG_VSX */
2750 op->type = MKOP(LOAD, u, 4);
2751 op->ea = dform_ea(word, regs);
2756 op->type = MKOP(LOAD, u, 1);
2757 op->ea = dform_ea(word, regs);
2762 op->type = MKOP(STORE, u, 4);
2763 op->ea = dform_ea(word, regs);
2768 op->type = MKOP(STORE, u, 1);
2769 op->ea = dform_ea(word, regs);
2774 op->type = MKOP(LOAD, u, 2);
2775 op->ea = dform_ea(word, regs);
2780 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2781 op->ea = dform_ea(word, regs);
2786 op->type = MKOP(STORE, u, 2);
2787 op->ea = dform_ea(word, regs);
2792 break; /* invalid form, ra in range to load */
2793 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2794 op->ea = dform_ea(word, regs);
2798 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2799 op->ea = dform_ea(word, regs);
2802 #ifdef CONFIG_PPC_FPU
2805 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2806 op->ea = dform_ea(word, regs);
2811 op->type = MKOP(LOAD_FP, u, 8);
2812 op->ea = dform_ea(word, regs);
2816 case 53: /* stfsu */
2817 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2818 op->ea = dform_ea(word, regs);
2822 case 55: /* stfdu */
2823 op->type = MKOP(STORE_FP, u, 8);
2824 op->ea = dform_ea(word, regs);
2828 #ifdef __powerpc64__
2830 if (!((rd & 1) || (rd == ra)))
2831 op->type = MKOP(LOAD, 0, 16);
2832 op->ea = dqform_ea(word, regs);
2837 case 57: /* lfdp, lxsd, lxssp */
2838 op->ea = dsform_ea(word, regs);
2842 break; /* reg must be even */
2843 op->type = MKOP(LOAD_FP, 0, 16);
2846 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2847 goto unknown_opcode;
2849 op->type = MKOP(LOAD_VSX, 0, 8);
2850 op->element_size = 8;
2851 op->vsx_flags = VSX_CHECK_VEC;
2854 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2855 goto unknown_opcode;
2857 op->type = MKOP(LOAD_VSX, 0, 4);
2858 op->element_size = 8;
2859 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2863 #endif /* CONFIG_VSX */
2865 #ifdef __powerpc64__
2866 case 58: /* ld[u], lwa */
2867 op->ea = dsform_ea(word, regs);
2870 op->type = MKOP(LOAD, 0, 8);
2873 op->type = MKOP(LOAD, UPDATE, 8);
2876 op->type = MKOP(LOAD, SIGNEXT, 4);
2884 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2885 goto unknown_opcode;
2886 op->ea = dqform_ea(word, regs);
2887 op->reg = VSX_REGISTER_XTP(rd);
2888 op->element_size = 32;
2889 switch (word & 0xf) {
2891 op->type = MKOP(LOAD_VSX, 0, 32);
2894 op->type = MKOP(STORE_VSX, 0, 32);
2899 case 61: /* stfdp, lxv, stxsd, stxssp, stxv */
2901 case 0: /* stfdp with LSB of DS field = 0 */
2902 case 4: /* stfdp with LSB of DS field = 1 */
2903 op->ea = dsform_ea(word, regs);
2904 op->type = MKOP(STORE_FP, 0, 16);
2908 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2909 goto unknown_opcode;
2910 op->ea = dqform_ea(word, regs);
2913 op->type = MKOP(LOAD_VSX, 0, 16);
2914 op->element_size = 16;
2915 op->vsx_flags = VSX_CHECK_VEC;
2918 case 2: /* stxsd with LSB of DS field = 0 */
2919 case 6: /* stxsd with LSB of DS field = 1 */
2920 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2921 goto unknown_opcode;
2922 op->ea = dsform_ea(word, regs);
2924 op->type = MKOP(STORE_VSX, 0, 8);
2925 op->element_size = 8;
2926 op->vsx_flags = VSX_CHECK_VEC;
2929 case 3: /* stxssp with LSB of DS field = 0 */
2930 case 7: /* stxssp with LSB of DS field = 1 */
2931 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2932 goto unknown_opcode;
2933 op->ea = dsform_ea(word, regs);
2935 op->type = MKOP(STORE_VSX, 0, 4);
2936 op->element_size = 8;
2937 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2941 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2942 goto unknown_opcode;
2943 op->ea = dqform_ea(word, regs);
2946 op->type = MKOP(STORE_VSX, 0, 16);
2947 op->element_size = 16;
2948 op->vsx_flags = VSX_CHECK_VEC;
2952 #endif /* CONFIG_VSX */
2954 #ifdef __powerpc64__
2955 case 62: /* std[u] */
2956 op->ea = dsform_ea(word, regs);
2959 op->type = MKOP(STORE, 0, 8);
2962 op->type = MKOP(STORE, UPDATE, 8);
2966 op->type = MKOP(STORE, 0, 16);
2970 case 1: /* Prefixed instructions */
2971 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2972 goto unknown_opcode;
2974 prefix_r = GET_PREFIX_R(word);
2975 ra = GET_PREFIX_RA(suffix);
2976 op->update_reg = ra;
2977 rd = (suffix >> 21) & 0x1f;
2979 op->val = regs->gpr[rd];
2981 suffixopcode = get_op(suffix);
2982 prefixtype = (word >> 24) & 0x3;
2983 switch (prefixtype) {
2984 case 0: /* Type 00 Eight-Byte Load/Store */
2987 op->ea = mlsd_8lsd_ea(word, suffix, regs);
2988 switch (suffixopcode) {
2990 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
2993 case 42: /* plxsd */
2995 op->type = MKOP(LOAD_VSX, PREFIXED, 8);
2996 op->element_size = 8;
2997 op->vsx_flags = VSX_CHECK_VEC;
2999 case 43: /* plxssp */
3001 op->type = MKOP(LOAD_VSX, PREFIXED, 4);
3002 op->element_size = 8;
3003 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
3005 case 46: /* pstxsd */
3007 op->type = MKOP(STORE_VSX, PREFIXED, 8);
3008 op->element_size = 8;
3009 op->vsx_flags = VSX_CHECK_VEC;
3011 case 47: /* pstxssp */
3013 op->type = MKOP(STORE_VSX, PREFIXED, 4);
3014 op->element_size = 8;
3015 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
3017 case 51: /* plxv1 */
3020 case 50: /* plxv0 */
3021 op->type = MKOP(LOAD_VSX, PREFIXED, 16);
3022 op->element_size = 16;
3023 op->vsx_flags = VSX_CHECK_VEC;
3025 case 55: /* pstxv1 */
3028 case 54: /* pstxv0 */
3029 op->type = MKOP(STORE_VSX, PREFIXED, 16);
3030 op->element_size = 16;
3031 op->vsx_flags = VSX_CHECK_VEC;
3033 #endif /* CONFIG_VSX */
3035 op->type = MKOP(LOAD, PREFIXED, 16);
3038 op->type = MKOP(LOAD, PREFIXED, 8);
3041 case 58: /* plxvp */
3042 op->reg = VSX_REGISTER_XTP(rd);
3043 op->type = MKOP(LOAD_VSX, PREFIXED, 32);
3044 op->element_size = 32;
3046 #endif /* CONFIG_VSX */
3048 op->type = MKOP(STORE, PREFIXED, 16);
3051 op->type = MKOP(STORE, PREFIXED, 8);
3054 case 62: /* pstxvp */
3055 op->reg = VSX_REGISTER_XTP(rd);
3056 op->type = MKOP(STORE_VSX, PREFIXED, 32);
3057 op->element_size = 32;
3059 #endif /* CONFIG_VSX */
3062 case 1: /* Type 01 Eight-Byte Register-to-Register */
3064 case 2: /* Type 10 Modified Load/Store */
3067 op->ea = mlsd_8lsd_ea(word, suffix, regs);
3068 switch (suffixopcode) {
3070 op->type = MKOP(LOAD, PREFIXED, 4);
3073 op->type = MKOP(LOAD, PREFIXED, 1);
3076 op->type = MKOP(STORE, PREFIXED, 4);
3079 op->type = MKOP(STORE, PREFIXED, 1);
3082 op->type = MKOP(LOAD, PREFIXED, 2);
3085 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2);
3088 op->type = MKOP(STORE, PREFIXED, 2);
3091 op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4);
3094 op->type = MKOP(LOAD_FP, PREFIXED, 8);
3096 case 52: /* pstfs */
3097 op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4);
3099 case 54: /* pstfd */
3100 op->type = MKOP(STORE_FP, PREFIXED, 8);
3104 case 3: /* Type 11 Modified Register-to-Register */
3107 #endif /* __powerpc64__ */
3111 if (OP_IS_LOAD_STORE(op->type) && (op->type & UPDATE)) {
3112 switch (GETTYPE(op->type)) {
3115 goto unknown_opcode;
3121 goto unknown_opcode;
3126 if ((GETTYPE(op->type) == LOAD_VSX ||
3127 GETTYPE(op->type) == STORE_VSX) &&
3128 !cpu_has_feature(CPU_FTR_VSX)) {
3131 #endif /* CONFIG_VSX */
3156 op->type = INTERRUPT | 0x700;
3157 op->val = SRR1_PROGPRIV;
3161 op->type = INTERRUPT | 0x700;
3162 op->val = SRR1_PROGTRAP;
3165 EXPORT_SYMBOL_GPL(analyse_instr);
3166 NOKPROBE_SYMBOL(analyse_instr);
3169 * For PPC32 we always use stwu with r1 to change the stack pointer.
3170 * So this emulated store may corrupt the exception frame, now we
3171 * have to provide the exception frame trampoline, which is pushed
3172 * below the kprobed function stack. So we only update gpr[1] but
3173 * don't emulate the real store operation. We will do real store
3174 * operation safely in exception return code by checking this flag.
3176 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
3179 * Check if we already set since that means we'll
3180 * lose the previous value.
3182 WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
3183 set_thread_flag(TIF_EMULATE_STACK_STORE);
3187 static nokprobe_inline void do_signext(unsigned long *valp, int size)
3191 *valp = (signed short) *valp;
3194 *valp = (signed int) *valp;
3199 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
3203 *valp = byterev_2(*valp);
3206 *valp = byterev_4(*valp);
3208 #ifdef __powerpc64__
3210 *valp = byterev_8(*valp);
3217 * Emulate an instruction that can be executed just by updating
3220 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
3222 unsigned long next_pc;
3224 next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type));
3225 switch (GETTYPE(op->type)) {
3227 if (op->type & SETREG)
3228 regs->gpr[op->reg] = op->val;
3229 if (op->type & SETCC)
3230 regs->ccr = op->ccval;
3231 if (op->type & SETXER)
3232 regs->xer = op->xerval;
3236 if (op->type & SETLK)
3237 regs->link = next_pc;
3238 if (op->type & BRTAKEN)
3240 if (op->type & DECCTR)
3245 switch (op->type & BARRIER_MASK) {
3256 case BARRIER_LWSYNC:
3257 asm volatile("lwsync" : : : "memory");
3259 case BARRIER_PTESYNC:
3260 asm volatile("ptesync" : : : "memory");
3269 regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
3272 regs->gpr[op->reg] = regs->link;
3275 regs->gpr[op->reg] = regs->ctr;
3285 regs->xer = op->val & 0xffffffffUL;
3288 regs->link = op->val;
3291 regs->ctr = op->val;
3301 regs_set_return_ip(regs, next_pc);
3303 NOKPROBE_SYMBOL(emulate_update_regs);
3306 * Emulate a previously-analysed load or store instruction.
3307 * Return values are:
3308 * 0 = instruction emulated successfully
3309 * -EFAULT = address out of range or access faulted (regs->dar
3310 * contains the faulting address)
3311 * -EACCES = misaligned access, instruction requires alignment
3312 * -EINVAL = unknown operation in *op
3314 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
3316 int err, size, type;
3324 size = GETSIZE(op->type);
3325 type = GETTYPE(op->type);
3326 cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
3327 ea = truncate_if_32bit(regs->msr, op->ea);
3331 if (ea & (size - 1))
3332 return -EACCES; /* can't handle misaligned */
3333 if (!address_ok(regs, ea, size))
3338 #ifdef CONFIG_PPC_HAS_LBARX_LHARX
3340 __get_user_asmx(val, ea, err, "lbarx");
3343 __get_user_asmx(val, ea, err, "lharx");
3347 __get_user_asmx(val, ea, err, "lwarx");
3349 #ifdef __powerpc64__
3351 __get_user_asmx(val, ea, err, "ldarx");
3354 err = do_lqarx(ea, ®s->gpr[op->reg]);
3365 regs->gpr[op->reg] = val;
3369 if (ea & (size - 1))
3370 return -EACCES; /* can't handle misaligned */
3371 if (!address_ok(regs, ea, size))
3375 #ifdef __powerpc64__
3377 __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3380 __put_user_asmx(op->val, ea, err, "sthcx.", cr);
3384 __put_user_asmx(op->val, ea, err, "stwcx.", cr);
3386 #ifdef __powerpc64__
3388 __put_user_asmx(op->val, ea, err, "stdcx.", cr);
3391 err = do_stqcx(ea, regs->gpr[op->reg],
3392 regs->gpr[op->reg + 1], &cr);
3399 regs->ccr = (regs->ccr & 0x0fffffff) |
3401 ((regs->xer >> 3) & 0x10000000);
3407 #ifdef __powerpc64__
3409 err = emulate_lq(regs, ea, op->reg, cross_endian);
3413 err = read_mem(®s->gpr[op->reg], ea, size, regs);
3415 if (op->type & SIGNEXT)
3416 do_signext(®s->gpr[op->reg], size);
3417 if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
3418 do_byterev(®s->gpr[op->reg], size);
3422 #ifdef CONFIG_PPC_FPU
3425 * If the instruction is in userspace, we can emulate it even
3426 * if the VMX state is not live, because we have the state
3427 * stored in the thread_struct. If the instruction is in
3428 * the kernel, we must not touch the state in the thread_struct.
3430 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3432 err = do_fp_load(op, ea, regs, cross_endian);
3435 #ifdef CONFIG_ALTIVEC
3437 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3439 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
3444 unsigned long msrbit = MSR_VSX;
3447 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3448 * when the target of the instruction is a vector register.
3450 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3452 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3454 err = do_vsx_load(op, ea, regs, cross_endian);
3459 if (!address_ok(regs, ea, size))
3462 for (i = 0; i < size; i += 4) {
3463 unsigned int v32 = 0;
3468 err = copy_mem_in((u8 *) &v32, ea, nb, regs);
3471 if (unlikely(cross_endian))
3472 v32 = byterev_4(v32);
3473 regs->gpr[rd] = v32;
3475 /* reg number wraps from 31 to 0 for lsw[ix] */
3476 rd = (rd + 1) & 0x1f;
3481 #ifdef __powerpc64__
3483 err = emulate_stq(regs, ea, op->reg, cross_endian);
3487 if ((op->type & UPDATE) && size == sizeof(long) &&
3488 op->reg == 1 && op->update_reg == 1 &&
3489 !(regs->msr & MSR_PR) &&
3490 ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
3491 err = handle_stack_update(ea, regs);
3494 if (unlikely(cross_endian))
3495 do_byterev(&op->val, size);
3496 err = write_mem(op->val, ea, size, regs);
3499 #ifdef CONFIG_PPC_FPU
3501 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3503 err = do_fp_store(op, ea, regs, cross_endian);
3506 #ifdef CONFIG_ALTIVEC
3508 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3510 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
3515 unsigned long msrbit = MSR_VSX;
3518 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3519 * when the target of the instruction is a vector register.
3521 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3523 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3525 err = do_vsx_store(op, ea, regs, cross_endian);
3530 if (!address_ok(regs, ea, size))
3533 for (i = 0; i < size; i += 4) {
3534 unsigned int v32 = regs->gpr[rd];
3539 if (unlikely(cross_endian))
3540 v32 = byterev_4(v32);
3541 err = copy_mem_out((u8 *) &v32, ea, nb, regs);
3545 /* reg number wraps from 31 to 0 for stsw[ix] */
3546 rd = (rd + 1) & 0x1f;
3557 if (op->type & UPDATE)
3558 regs->gpr[op->update_reg] = op->ea;
3562 NOKPROBE_SYMBOL(emulate_loadstore);
3565 * Emulate instructions that cause a transfer of control,
3566 * loads and stores, and a few other instructions.
3567 * Returns 1 if the step was emulated, 0 if not,
3568 * or -1 if the instruction is one that should not be stepped,
3569 * such as an rfid, or a mtmsrd that would clear MSR_RI.
3571 int emulate_step(struct pt_regs *regs, ppc_inst_t instr)
3573 struct instruction_op op;
3578 r = analyse_instr(&op, regs, instr);
3582 emulate_update_regs(regs, &op);
3587 type = GETTYPE(op.type);
3589 if (OP_IS_LOAD_STORE(type)) {
3590 err = emulate_loadstore(regs, &op);
3598 ea = truncate_if_32bit(regs->msr, op.ea);
3599 if (!address_ok(regs, ea, 8))
3601 switch (op.type & CACHEOP_MASK) {
3603 __cacheop_user_asmx(ea, err, "dcbst");
3606 __cacheop_user_asmx(ea, err, "dcbf");
3610 prefetchw((void *) ea);
3614 prefetch((void *) ea);
3617 __cacheop_user_asmx(ea, err, "icbi");
3620 err = emulate_dcbz(ea, regs);
3630 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3634 val = regs->gpr[op.reg];
3635 if ((val & MSR_RI) == 0)
3636 /* can't step mtmsr[d] that would clear MSR_RI */
3638 /* here op.val is the mask of bits to change */
3639 regs_set_return_msr(regs, (regs->msr & ~op.val) | (val & op.val));
3642 case SYSCALL: /* sc */
3644 * Per ISA v3.1, section 7.5.15 'Trace Interrupt', we can't
3645 * single step a system call instruction:
3647 * Successful completion for an instruction means that the
3648 * instruction caused no other interrupt. Thus a Trace
3649 * interrupt never occurs for a System Call or System Call
3650 * Vectored instruction, or for a Trap instruction that
3654 case SYSCALL_VECTORED_0: /* scv 0 */
3662 regs_set_return_ip(regs,
3663 truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type)));
3666 NOKPROBE_SYMBOL(emulate_step);