arch/powerpc/lib/sstep.c

   1 /*
   2  * Single-step support.
   3  *
   4  * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/kprobes.h>
  13 #include <linux/ptrace.h>
  14 #include <linux/prefetch.h>
  15 #include <asm/sstep.h>
  16 #include <asm/processor.h>
  17 #include <linux/uaccess.h>
  18 #include <asm/cpu_has_feature.h>
  19 #include <asm/cputable.h>
  20
  21 extern char system_call_common[];
  22
  23 #ifdef CONFIG_PPC64
  24 /* Bits in SRR1 that are copied from MSR */
  25 #define MSR_MASK        0xffffffff87c0ffffUL
  26 #else
  27 #define MSR_MASK        0x87c0ffff
  28 #endif
  29
  30 /* Bits in XER */
  31 #define XER_SO          0x80000000U
  32 #define XER_OV          0x40000000U
  33 #define XER_CA          0x20000000U
  34
  35 #ifdef CONFIG_PPC_FPU
  36 /*
  37  * Functions in ldstfp.S
  38  */
  39 extern int do_lfs(int rn, unsigned long ea);
  40 extern int do_lfd(int rn, unsigned long ea);
  41 extern int do_stfs(int rn, unsigned long ea);
  42 extern int do_stfd(int rn, unsigned long ea);
  43 extern int do_lvx(int rn, unsigned long ea);
  44 extern int do_stvx(int rn, unsigned long ea);
  45 extern void load_vsrn(int vsr, const void *p);
  46 extern void store_vsrn(int vsr, void *p);
  47 extern void conv_sp_to_dp(const float *sp, double *dp);
  48 extern void conv_dp_to_sp(const double *dp, float *sp);
  49 #endif
  50
  51 #ifdef __powerpc64__
  52 /*
  53  * Functions in quad.S
  54  */
  55 extern int do_lq(unsigned long ea, unsigned long *regs);
  56 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
  57 extern int do_lqarx(unsigned long ea, unsigned long *regs);
  58 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
  59                     unsigned int *crp);
  60 #endif
  61
  62 #ifdef __LITTLE_ENDIAN__
  63 #define IS_LE   1
  64 #define IS_BE   0
  65 #else
  66 #define IS_LE   0
  67 #define IS_BE   1
  68 #endif
  69
  70 /*
  71  * Emulate the truncation of 64 bit values in 32-bit mode.
  72  */
  73 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
  74                                                         unsigned long val)
  75 {
  76 #ifdef __powerpc64__
  77         if ((msr & MSR_64BIT) == 0)
  78                 val &= 0xffffffffUL;
  79 #endif
  80         return val;
  81 }
  82
  83 /*
  84  * Determine whether a conditional branch instruction would branch.
  85  */
  86 static nokprobe_inline int branch_taken(unsigned int instr,
  87                                         const struct pt_regs *regs,
  88                                         struct instruction_op *op)
  89 {
  90         unsigned int bo = (instr >> 21) & 0x1f;
  91         unsigned int bi;
  92
  93         if ((bo & 4) == 0) {
  94                 /* decrement counter */
  95                 op->type |= DECCTR;
  96                 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
  97                         return 0;
  98         }
  99         if ((bo & 0x10) == 0) {
 100                 /* check bit from CR */
 101                 bi = (instr >> 16) & 0x1f;
 102                 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
 103                         return 0;
 104         }
 105         return 1;
 106 }
 107
 108 static nokprobe_inline long address_ok(struct pt_regs *regs, unsigned long ea, int nb)
 109 {
 110         if (!user_mode(regs))
 111                 return 1;
 112         return __access_ok(ea, nb, USER_DS);
 113 }
 114
 115 /*
 116  * Calculate effective address for a D-form instruction
 117  */
 118 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
 119                                               const struct pt_regs *regs)
 120 {
 121         int ra;
 122         unsigned long ea;
 123
 124         ra = (instr >> 16) & 0x1f;
 125         ea = (signed short) instr;              /* sign-extend */
 126         if (ra)
 127                 ea += regs->gpr[ra];
 128
 129         return ea;
 130 }
 131
 132 #ifdef __powerpc64__
 133 /*
 134  * Calculate effective address for a DS-form instruction
 135  */
 136 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
 137                                                const struct pt_regs *regs)
 138 {
 139         int ra;
 140         unsigned long ea;
 141
 142         ra = (instr >> 16) & 0x1f;
 143         ea = (signed short) (instr & ~3);       /* sign-extend */
 144         if (ra)
 145                 ea += regs->gpr[ra];
 146
 147         return ea;
 148 }
 149
 150 /*
 151  * Calculate effective address for a DQ-form instruction
 152  */
 153 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
 154                                                const struct pt_regs *regs)
 155 {
 156         int ra;
 157         unsigned long ea;
 158
 159         ra = (instr >> 16) & 0x1f;
 160         ea = (signed short) (instr & ~0xf);     /* sign-extend */
 161         if (ra)
 162                 ea += regs->gpr[ra];
 163
 164         return ea;
 165 }
 166 #endif /* __powerpc64 */
 167
 168 /*
 169  * Calculate effective address for an X-form instruction
 170  */
 171 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
 172                                               const struct pt_regs *regs)
 173 {
 174         int ra, rb;
 175         unsigned long ea;
 176
 177         ra = (instr >> 16) & 0x1f;
 178         rb = (instr >> 11) & 0x1f;
 179         ea = regs->gpr[rb];
 180         if (ra)
 181                 ea += regs->gpr[ra];
 182
 183         return ea;
 184 }
 185
 186 /*
 187  * Return the largest power of 2, not greater than sizeof(unsigned long),
 188  * such that x is a multiple of it.
 189  */
 190 static nokprobe_inline unsigned long max_align(unsigned long x)
 191 {
 192         x |= sizeof(unsigned long);
 193         return x & -x;          /* isolates rightmost bit */
 194 }
 195
 196 static nokprobe_inline unsigned long byterev_2(unsigned long x)
 197 {
 198         return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
 199 }
 200
 201 static nokprobe_inline unsigned long byterev_4(unsigned long x)
 202 {
 203         return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
 204                 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
 205 }
 206
 207 #ifdef __powerpc64__
 208 static nokprobe_inline unsigned long byterev_8(unsigned long x)
 209 {
 210         return (byterev_4(x) << 32) | byterev_4(x >> 32);
 211 }
 212 #endif
 213
 214 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
 215                                         unsigned long ea, int nb)
 216 {
 217         int err = 0;
 218         unsigned long x = 0;
 219
 220         switch (nb) {
 221         case 1:
 222                 err = __get_user(x, (unsigned char __user *) ea);
 223                 break;
 224         case 2:
 225                 err = __get_user(x, (unsigned short __user *) ea);
 226                 break;
 227         case 4:
 228                 err = __get_user(x, (unsigned int __user *) ea);
 229                 break;
 230 #ifdef __powerpc64__
 231         case 8:
 232                 err = __get_user(x, (unsigned long __user *) ea);
 233                 break;
 234 #endif
 235         }
 236         if (!err)
 237                 *dest = x;
 238         return err;
 239 }
 240
 241 /*
 242  * Copy from userspace to a buffer, using the largest possible
 243  * aligned accesses, up to sizeof(long).
 244  */
 245 static int nokprobe_inline copy_mem_in(u8 *dest, unsigned long ea, int nb)
 246 {
 247         int err = 0;
 248         int c;
 249
 250         for (; nb > 0; nb -= c) {
 251                 c = max_align(ea);
 252                 if (c > nb)
 253                         c = max_align(nb);
 254                 switch (c) {
 255                 case 1:
 256                         err = __get_user(*dest, (unsigned char __user *) ea);
 257                         break;
 258                 case 2:
 259                         err = __get_user(*(u16 *)dest,
 260                                          (unsigned short __user *) ea);
 261                         break;
 262                 case 4:
 263                         err = __get_user(*(u32 *)dest,
 264                                          (unsigned int __user *) ea);
 265                         break;
 266 #ifdef __powerpc64__
 267                 case 8:
 268                         err = __get_user(*(unsigned long *)dest,
 269                                          (unsigned long __user *) ea);
 270                         break;
 271 #endif
 272                 }
 273                 if (err)
 274                         return err;
 275                 dest += c;
 276                 ea += c;
 277         }
 278         return 0;
 279 }
 280
 281 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
 282                                               unsigned long ea, int nb,
 283                                               struct pt_regs *regs)
 284 {
 285         union {
 286                 unsigned long ul;
 287                 u8 b[sizeof(unsigned long)];
 288         } u;
 289         int i;
 290         int err;
 291
 292         u.ul = 0;
 293         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 294         err = copy_mem_in(&u.b[i], ea, nb);
 295         if (!err)
 296                 *dest = u.ul;
 297         return err;
 298 }
 299
 300 /*
 301  * Read memory at address ea for nb bytes, return 0 for success
 302  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 303  * If nb < sizeof(long), the result is right-justified on BE systems.
 304  */
 305 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
 306                               struct pt_regs *regs)
 307 {
 308         if (!address_ok(regs, ea, nb))
 309                 return -EFAULT;
 310         if ((ea & (nb - 1)) == 0)
 311                 return read_mem_aligned(dest, ea, nb);
 312         return read_mem_unaligned(dest, ea, nb, regs);
 313 }
 314 NOKPROBE_SYMBOL(read_mem);
 315
 316 static nokprobe_inline int write_mem_aligned(unsigned long val,
 317                                         unsigned long ea, int nb)
 318 {
 319         int err = 0;
 320
 321         switch (nb) {
 322         case 1:
 323                 err = __put_user(val, (unsigned char __user *) ea);
 324                 break;
 325         case 2:
 326                 err = __put_user(val, (unsigned short __user *) ea);
 327                 break;
 328         case 4:
 329                 err = __put_user(val, (unsigned int __user *) ea);
 330                 break;
 331 #ifdef __powerpc64__
 332         case 8:
 333                 err = __put_user(val, (unsigned long __user *) ea);
 334                 break;
 335 #endif
 336         }
 337         return err;
 338 }
 339
 340 /*
 341  * Copy from a buffer to userspace, using the largest possible
 342  * aligned accesses, up to sizeof(long).
 343  */
 344 static int nokprobe_inline copy_mem_out(u8 *dest, unsigned long ea, int nb)
 345 {
 346         int err = 0;
 347         int c;
 348
 349         for (; nb > 0; nb -= c) {
 350                 c = max_align(ea);
 351                 if (c > nb)
 352                         c = max_align(nb);
 353                 switch (c) {
 354                 case 1:
 355                         err = __put_user(*dest, (unsigned char __user *) ea);
 356                         break;
 357                 case 2:
 358                         err = __put_user(*(u16 *)dest,
 359                                          (unsigned short __user *) ea);
 360                         break;
 361                 case 4:
 362                         err = __put_user(*(u32 *)dest,
 363                                          (unsigned int __user *) ea);
 364                         break;
 365 #ifdef __powerpc64__
 366                 case 8:
 367                         err = __put_user(*(unsigned long *)dest,
 368                                          (unsigned long __user *) ea);
 369                         break;
 370 #endif
 371                 }
 372                 if (err)
 373                         return err;
 374                 dest += c;
 375                 ea += c;
 376         }
 377         return 0;
 378 }
 379
 380 static nokprobe_inline int write_mem_unaligned(unsigned long val,
 381                                                unsigned long ea, int nb,
 382                                                struct pt_regs *regs)
 383 {
 384         union {
 385                 unsigned long ul;
 386                 u8 b[sizeof(unsigned long)];
 387         } u;
 388         int i;
 389
 390         u.ul = val;
 391         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 392         return copy_mem_out(&u.b[i], ea, nb);
 393 }
 394
 395 /*
 396  * Write memory at address ea for nb bytes, return 0 for success
 397  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 398  */
 399 static int write_mem(unsigned long val, unsigned long ea, int nb,
 400                                struct pt_regs *regs)
 401 {
 402         if (!address_ok(regs, ea, nb))
 403                 return -EFAULT;
 404         if ((ea & (nb - 1)) == 0)
 405                 return write_mem_aligned(val, ea, nb);
 406         return write_mem_unaligned(val, ea, nb, regs);
 407 }
 408 NOKPROBE_SYMBOL(write_mem);
 409
 410 #ifdef CONFIG_PPC_FPU
 411 /*
 412  * Check the address and alignment, and call func to do the actual
 413  * load or store.
 414  */
 415 static int do_fp_load(int rn, int (*func)(int, unsigned long),
 416                                 unsigned long ea, int nb,
 417                                 struct pt_regs *regs)
 418 {
 419         int err;
 420         u8 buf[sizeof(double)] __attribute__((aligned(sizeof(double))));
 421
 422         if (!address_ok(regs, ea, nb))
 423                 return -EFAULT;
 424         if (ea & 3) {
 425                 err = copy_mem_in(buf, ea, nb);
 426                 if (err)
 427                         return err;
 428                 ea = (unsigned long) buf;
 429         }
 430         return (*func)(rn, ea);
 431 }
 432 NOKPROBE_SYMBOL(do_fp_load);
 433
 434 static int do_fp_store(int rn, int (*func)(int, unsigned long),
 435                                  unsigned long ea, int nb,
 436                                  struct pt_regs *regs)
 437 {
 438         int err;
 439         u8 buf[sizeof(double)] __attribute__((aligned(sizeof(double))));
 440
 441         if (!address_ok(regs, ea, nb))
 442                 return -EFAULT;
 443         if ((ea & 3) == 0)
 444                 return (*func)(rn, ea);
 445         err = (*func)(rn, (unsigned long) buf);
 446         if (!err)
 447                 err = copy_mem_out(buf, ea, nb);
 448         return err;
 449 }
 450 NOKPROBE_SYMBOL(do_fp_store);
 451 #endif
 452
 453 #ifdef CONFIG_ALTIVEC
 454 /* For Altivec/VMX, no need to worry about alignment */
 455 static nokprobe_inline int do_vec_load(int rn, int (*func)(int, unsigned long),
 456                                  unsigned long ea, struct pt_regs *regs)
 457 {
 458         if (!address_ok(regs, ea & ~0xfUL, 16))
 459                 return -EFAULT;
 460         return (*func)(rn, ea);
 461 }
 462
 463 static nokprobe_inline int do_vec_store(int rn, int (*func)(int, unsigned long),
 464                                   unsigned long ea, struct pt_regs *regs)
 465 {
 466         if (!address_ok(regs, ea & ~0xfUL, 16))
 467                 return -EFAULT;
 468         return (*func)(rn, ea);
 469 }
 470 #endif /* CONFIG_ALTIVEC */
 471
 472 #ifdef __powerpc64__
 473 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
 474                                       int reg)
 475 {
 476         int err;
 477
 478         if (!address_ok(regs, ea, 16))
 479                 return -EFAULT;
 480         /* if aligned, should be atomic */
 481         if ((ea & 0xf) == 0)
 482                 return do_lq(ea, &regs->gpr[reg]);
 483
 484         err = read_mem(&regs->gpr[reg + IS_LE], ea, 8, regs);
 485         if (!err)
 486                 err = read_mem(&regs->gpr[reg + IS_BE], ea + 8, 8, regs);
 487         return err;
 488 }
 489
 490 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
 491                                        int reg)
 492 {
 493         int err;
 494
 495         if (!address_ok(regs, ea, 16))
 496                 return -EFAULT;
 497         /* if aligned, should be atomic */
 498         if ((ea & 0xf) == 0)
 499                 return do_stq(ea, regs->gpr[reg], regs->gpr[reg + 1]);
 500
 501         err = write_mem(regs->gpr[reg + IS_LE], ea, 8, regs);
 502         if (!err)
 503                 err = write_mem(regs->gpr[reg + IS_BE], ea + 8, 8, regs);
 504         return err;
 505 }
 506 #endif /* __powerpc64 */
 507
 508 #ifdef CONFIG_VSX
 509 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
 510                       const void *mem)
 511 {
 512         int size, read_size;
 513         int i, j;
 514         const unsigned int *wp;
 515         const unsigned short *hp;
 516         const unsigned char *bp;
 517
 518         size = GETSIZE(op->type);
 519         reg->d[0] = reg->d[1] = 0;
 520
 521         switch (op->element_size) {
 522         case 16:
 523                 /* whole vector; lxv[x] or lxvl[l] */
 524                 if (size == 0)
 525                         break;
 526                 memcpy(reg, mem, size);
 527                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) {
 528                         /* reverse 16 bytes */
 529                         unsigned long tmp;
 530                         tmp = byterev_8(reg->d[0]);
 531                         reg->d[0] = byterev_8(reg->d[1]);
 532                         reg->d[1] = tmp;
 533                 }
 534                 break;
 535         case 8:
 536                 /* scalar loads, lxvd2x, lxvdsx */
 537                 read_size = (size >= 8) ? 8 : size;
 538                 i = IS_LE ? 8 : 8 - read_size;
 539                 memcpy(&reg->b[i], mem, read_size);
 540                 if (size < 8) {
 541                         if (op->type & SIGNEXT) {
 542                                 /* size == 4 is the only case here */
 543                                 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
 544                         } else if (op->vsx_flags & VSX_FPCONV) {
 545                                 preempt_disable();
 546                                 conv_sp_to_dp(&reg->fp[1 + IS_LE],
 547                                               &reg->dp[IS_LE]);
 548                                 preempt_enable();
 549                         }
 550                 } else {
 551                         if (size == 16)
 552                                 reg->d[IS_BE] = *(unsigned long *)(mem + 8);
 553                         else if (op->vsx_flags & VSX_SPLAT)
 554                                 reg->d[IS_BE] = reg->d[IS_LE];
 555                 }
 556                 break;
 557         case 4:
 558                 /* lxvw4x, lxvwsx */
 559                 wp = mem;
 560                 for (j = 0; j < size / 4; ++j) {
 561                         i = IS_LE ? 3 - j : j;
 562                         reg->w[i] = *wp++;
 563                 }
 564                 if (op->vsx_flags & VSX_SPLAT) {
 565                         u32 val = reg->w[IS_LE ? 3 : 0];
 566                         for (; j < 4; ++j) {
 567                                 i = IS_LE ? 3 - j : j;
 568                                 reg->w[i] = val;
 569                         }
 570                 }
 571                 break;
 572         case 2:
 573                 /* lxvh8x */
 574                 hp = mem;
 575                 for (j = 0; j < size / 2; ++j) {
 576                         i = IS_LE ? 7 - j : j;
 577                         reg->h[i] = *hp++;
 578                 }
 579                 break;
 580         case 1:
 581                 /* lxvb16x */
 582                 bp = mem;
 583                 for (j = 0; j < size; ++j) {
 584                         i = IS_LE ? 15 - j : j;
 585                         reg->b[i] = *bp++;
 586                 }
 587                 break;
 588         }
 589 }
 590 EXPORT_SYMBOL_GPL(emulate_vsx_load);
 591 NOKPROBE_SYMBOL(emulate_vsx_load);
 592
 593 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
 594                        void *mem)
 595 {
 596         int size, write_size;
 597         int i, j;
 598         union vsx_reg buf;
 599         unsigned int *wp;
 600         unsigned short *hp;
 601         unsigned char *bp;
 602
 603         size = GETSIZE(op->type);
 604
 605         switch (op->element_size) {
 606         case 16:
 607                 /* stxv, stxvx, stxvl, stxvll */
 608                 if (size == 0)
 609                         break;
 610                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) {
 611                         /* reverse 16 bytes */
 612                         buf.d[0] = byterev_8(reg->d[1]);
 613                         buf.d[1] = byterev_8(reg->d[0]);
 614                         reg = &buf;
 615                 }
 616                 memcpy(mem, reg, size);
 617                 break;
 618         case 8:
 619                 /* scalar stores, stxvd2x */
 620                 write_size = (size >= 8) ? 8 : size;
 621                 i = IS_LE ? 8 : 8 - write_size;
 622                 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
 623                         buf.d[0] = buf.d[1] = 0;
 624                         preempt_disable();
 625                         conv_dp_to_sp(&reg->dp[IS_LE], &buf.fp[1 + IS_LE]);
 626                         preempt_enable();
 627                         reg = &buf;
 628                 }
 629                 memcpy(mem, &reg->b[i], write_size);
 630                 if (size == 16)
 631                         memcpy(mem + 8, &reg->d[IS_BE], 8);
 632                 break;
 633         case 4:
 634                 /* stxvw4x */
 635                 wp = mem;
 636                 for (j = 0; j < size / 4; ++j) {
 637                         i = IS_LE ? 3 - j : j;
 638                         *wp++ = reg->w[i];
 639                 }
 640                 break;
 641         case 2:
 642                 /* stxvh8x */
 643                 hp = mem;
 644                 for (j = 0; j < size / 2; ++j) {
 645                         i = IS_LE ? 7 - j : j;
 646                         *hp++ = reg->h[i];
 647                 }
 648                 break;
 649         case 1:
 650                 /* stvxb16x */
 651                 bp = mem;
 652                 for (j = 0; j < size; ++j) {
 653                         i = IS_LE ? 15 - j : j;
 654                         *bp++ = reg->b[i];
 655                 }
 656                 break;
 657         }
 658 }
 659 EXPORT_SYMBOL_GPL(emulate_vsx_store);
 660 NOKPROBE_SYMBOL(emulate_vsx_store);
 661 #endif /* CONFIG_VSX */
 662
 663 #define __put_user_asmx(x, addr, err, op, cr)           \
 664         __asm__ __volatile__(                           \
 665                 "1:     " op " %2,0,%3\n"               \
 666                 "       mfcr    %1\n"                   \
 667                 "2:\n"                                  \
 668                 ".section .fixup,\"ax\"\n"              \
 669                 "3:     li      %0,%4\n"                \
 670                 "       b       2b\n"                   \
 671                 ".previous\n"                           \
 672                 EX_TABLE(1b, 3b)                        \
 673                 : "=r" (err), "=r" (cr)                 \
 674                 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
 675
 676 #define __get_user_asmx(x, addr, err, op)               \
 677         __asm__ __volatile__(                           \
 678                 "1:     "op" %1,0,%2\n"                 \
 679                 "2:\n"                                  \
 680                 ".section .fixup,\"ax\"\n"              \
 681                 "3:     li      %0,%3\n"                \
 682                 "       b       2b\n"                   \
 683                 ".previous\n"                           \
 684                 EX_TABLE(1b, 3b)                        \
 685                 : "=r" (err), "=r" (x)                  \
 686                 : "r" (addr), "i" (-EFAULT), "0" (err))
 687
 688 #define __cacheop_user_asmx(addr, err, op)              \
 689         __asm__ __volatile__(                           \
 690                 "1:     "op" 0,%1\n"                    \
 691                 "2:\n"                                  \
 692                 ".section .fixup,\"ax\"\n"              \
 693                 "3:     li      %0,%3\n"                \
 694                 "       b       2b\n"                   \
 695                 ".previous\n"                           \
 696                 EX_TABLE(1b, 3b)                        \
 697                 : "=r" (err)                            \
 698                 : "r" (addr), "i" (-EFAULT), "0" (err))
 699
 700 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
 701                                     struct instruction_op *op, int rd)
 702 {
 703         long val = regs->gpr[rd];
 704
 705         op->type |= SETCC;
 706         op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
 707 #ifdef __powerpc64__
 708         if (!(regs->msr & MSR_64BIT))
 709                 val = (int) val;
 710 #endif
 711         if (val < 0)
 712                 op->ccval |= 0x80000000;
 713         else if (val > 0)
 714                 op->ccval |= 0x40000000;
 715         else
 716                 op->ccval |= 0x20000000;
 717 }
 718
 719 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
 720                                      struct instruction_op *op, int rd,
 721                                      unsigned long val1, unsigned long val2,
 722                                      unsigned long carry_in)
 723 {
 724         unsigned long val = val1 + val2;
 725
 726         if (carry_in)
 727                 ++val;
 728         op->type = COMPUTE + SETREG + SETXER;
 729         op->reg = rd;
 730         op->val = val;
 731 #ifdef __powerpc64__
 732         if (!(regs->msr & MSR_64BIT)) {
 733                 val = (unsigned int) val;
 734                 val1 = (unsigned int) val1;
 735         }
 736 #endif
 737         op->xerval = regs->xer;
 738         if (val < val1 || (carry_in && val == val1))
 739                 op->xerval |= XER_CA;
 740         else
 741                 op->xerval &= ~XER_CA;
 742 }
 743
 744 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
 745                                           struct instruction_op *op,
 746                                           long v1, long v2, int crfld)
 747 {
 748         unsigned int crval, shift;
 749
 750         op->type = COMPUTE + SETCC;
 751         crval = (regs->xer >> 31) & 1;          /* get SO bit */
 752         if (v1 < v2)
 753                 crval |= 8;
 754         else if (v1 > v2)
 755                 crval |= 4;
 756         else
 757                 crval |= 2;
 758         shift = (7 - crfld) * 4;
 759         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
 760 }
 761
 762 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
 763                                             struct instruction_op *op,
 764                                             unsigned long v1,
 765                                             unsigned long v2, int crfld)
 766 {
 767         unsigned int crval, shift;
 768
 769         op->type = COMPUTE + SETCC;
 770         crval = (regs->xer >> 31) & 1;          /* get SO bit */
 771         if (v1 < v2)
 772                 crval |= 8;
 773         else if (v1 > v2)
 774                 crval |= 4;
 775         else
 776                 crval |= 2;
 777         shift = (7 - crfld) * 4;
 778         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
 779 }
 780
 781 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
 782                                     struct instruction_op *op,
 783                                     unsigned long v1, unsigned long v2)
 784 {
 785         unsigned long long out_val, mask;
 786         int i;
 787
 788         out_val = 0;
 789         for (i = 0; i < 8; i++) {
 790                 mask = 0xffUL << (i * 8);
 791                 if ((v1 & mask) == (v2 & mask))
 792                         out_val |= mask;
 793         }
 794         op->val = out_val;
 795 }
 796
 797 /*
 798  * The size parameter is used to adjust the equivalent popcnt instruction.
 799  * popcntb = 8, popcntw = 32, popcntd = 64
 800  */
 801 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
 802                                       struct instruction_op *op,
 803                                       unsigned long v1, int size)
 804 {
 805         unsigned long long out = v1;
 806
 807         out -= (out >> 1) & 0x5555555555555555;
 808         out = (0x3333333333333333 & out) + (0x3333333333333333 & (out >> 2));
 809         out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0f;
 810
 811         if (size == 8) {        /* popcntb */
 812                 op->val = out;
 813                 return;
 814         }
 815         out += out >> 8;
 816         out += out >> 16;
 817         if (size == 32) {       /* popcntw */
 818                 op->val = out & 0x0000003f0000003f;
 819                 return;
 820         }
 821
 822         out = (out + (out >> 32)) & 0x7f;
 823         op->val = out;  /* popcntd */
 824 }
 825
 826 #ifdef CONFIG_PPC64
 827 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
 828                                       struct instruction_op *op,
 829                                       unsigned long v1, unsigned long v2)
 830 {
 831         unsigned char perm, idx;
 832         unsigned int i;
 833
 834         perm = 0;
 835         for (i = 0; i < 8; i++) {
 836                 idx = (v1 >> (i * 8)) & 0xff;
 837                 if (idx < 64)
 838                         if (v2 & PPC_BIT(idx))
 839                                 perm |= 1 << i;
 840         }
 841         op->val = perm;
 842 }
 843 #endif /* CONFIG_PPC64 */
 844 /*
 845  * The size parameter adjusts the equivalent prty instruction.
 846  * prtyw = 32, prtyd = 64
 847  */
 848 static nokprobe_inline void do_prty(const struct pt_regs *regs,
 849                                     struct instruction_op *op,
 850                                     unsigned long v, int size)
 851 {
 852         unsigned long long res = v ^ (v >> 8);
 853
 854         res ^= res >> 16;
 855         if (size == 32) {               /* prtyw */
 856                 op->val = res & 0x0000000100000001;
 857                 return;
 858         }
 859
 860         res ^= res >> 32;
 861         op->val = res & 1;      /*prtyd */
 862 }
 863
 864 static nokprobe_inline int trap_compare(long v1, long v2)
 865 {
 866         int ret = 0;
 867
 868         if (v1 < v2)
 869                 ret |= 0x10;
 870         else if (v1 > v2)
 871                 ret |= 0x08;
 872         else
 873                 ret |= 0x04;
 874         if ((unsigned long)v1 < (unsigned long)v2)
 875                 ret |= 0x02;
 876         else if ((unsigned long)v1 > (unsigned long)v2)
 877                 ret |= 0x01;
 878         return ret;
 879 }
 880
 881 /*
 882  * Elements of 32-bit rotate and mask instructions.
 883  */
 884 #define MASK32(mb, me)  ((0xffffffffUL >> (mb)) + \
 885                          ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
 886 #ifdef __powerpc64__
 887 #define MASK64_L(mb)    (~0UL >> (mb))
 888 #define MASK64_R(me)    ((signed long)-0x8000000000000000L >> (me))
 889 #define MASK64(mb, me)  (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
 890 #define DATA32(x)       (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
 891 #else
 892 #define DATA32(x)       (x)
 893 #endif
 894 #define ROTATE(x, n)    ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
 895
 896 /*
 897  * Decode an instruction, and return information about it in *op
 898  * without changing *regs.
 899  * Integer arithmetic and logical instructions, branches, and barrier
 900  * instructions can be emulated just using the information in *op.
 901  *
 902  * Return value is 1 if the instruction can be emulated just by
 903  * updating *regs with the information in *op, -1 if we need the
 904  * GPRs but *regs doesn't contain the full register set, or 0
 905  * otherwise.
 906  */
 907 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
 908                   unsigned int instr)
 909 {
 910         unsigned int opcode, ra, rb, rd, spr, u;
 911         unsigned long int imm;
 912         unsigned long int val, val2;
 913         unsigned int mb, me, sh;
 914         long ival;
 915
 916         op->type = COMPUTE;
 917
 918         opcode = instr >> 26;
 919         switch (opcode) {
 920         case 16:        /* bc */
 921                 op->type = BRANCH;
 922                 imm = (signed short)(instr & 0xfffc);
 923                 if ((instr & 2) == 0)
 924                         imm += regs->nip;
 925                 op->val = truncate_if_32bit(regs->msr, imm);
 926                 if (instr & 1)
 927                         op->type |= SETLK;
 928                 if (branch_taken(instr, regs, op))
 929                         op->type |= BRTAKEN;
 930                 return 1;
 931 #ifdef CONFIG_PPC64
 932         case 17:        /* sc */
 933                 if ((instr & 0xfe2) == 2)
 934                         op->type = SYSCALL;
 935                 else
 936                         op->type = UNKNOWN;
 937                 return 0;
 938 #endif
 939         case 18:        /* b */
 940                 op->type = BRANCH | BRTAKEN;
 941                 imm = instr & 0x03fffffc;
 942                 if (imm & 0x02000000)
 943                         imm -= 0x04000000;
 944                 if ((instr & 2) == 0)
 945                         imm += regs->nip;
 946                 op->val = truncate_if_32bit(regs->msr, imm);
 947                 if (instr & 1)
 948                         op->type |= SETLK;
 949                 return 1;
 950         case 19:
 951                 switch ((instr >> 1) & 0x3ff) {
 952                 case 0:         /* mcrf */
 953                         op->type = COMPUTE + SETCC;
 954                         rd = 7 - ((instr >> 23) & 0x7);
 955                         ra = 7 - ((instr >> 18) & 0x7);
 956                         rd *= 4;
 957                         ra *= 4;
 958                         val = (regs->ccr >> ra) & 0xf;
 959                         op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
 960                         return 1;
 961
 962                 case 16:        /* bclr */
 963                 case 528:       /* bcctr */
 964                         op->type = BRANCH;
 965                         imm = (instr & 0x400)? regs->ctr: regs->link;
 966                         op->val = truncate_if_32bit(regs->msr, imm);
 967                         if (instr & 1)
 968                                 op->type |= SETLK;
 969                         if (branch_taken(instr, regs, op))
 970                                 op->type |= BRTAKEN;
 971                         return 1;
 972
 973                 case 18:        /* rfid, scary */
 974                         if (regs->msr & MSR_PR)
 975                                 goto priv;
 976                         op->type = RFI;
 977                         return 0;
 978
 979                 case 150:       /* isync */
 980                         op->type = BARRIER | BARRIER_ISYNC;
 981                         return 1;
 982
 983                 case 33:        /* crnor */
 984                 case 129:       /* crandc */
 985                 case 193:       /* crxor */
 986                 case 225:       /* crnand */
 987                 case 257:       /* crand */
 988                 case 289:       /* creqv */
 989                 case 417:       /* crorc */
 990                 case 449:       /* cror */
 991                         op->type = COMPUTE + SETCC;
 992                         ra = (instr >> 16) & 0x1f;
 993                         rb = (instr >> 11) & 0x1f;
 994                         rd = (instr >> 21) & 0x1f;
 995                         ra = (regs->ccr >> (31 - ra)) & 1;
 996                         rb = (regs->ccr >> (31 - rb)) & 1;
 997                         val = (instr >> (6 + ra * 2 + rb)) & 1;
 998                         op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
 999                                 (val << (31 - rd));
1000                         return 1;
1001                 }
1002                 break;
1003         case 31:
1004                 switch ((instr >> 1) & 0x3ff) {
1005                 case 598:       /* sync */
1006                         op->type = BARRIER + BARRIER_SYNC;
1007 #ifdef __powerpc64__
1008                         switch ((instr >> 21) & 3) {
1009                         case 1:         /* lwsync */
1010                                 op->type = BARRIER + BARRIER_LWSYNC;
1011                                 break;
1012                         case 2:         /* ptesync */
1013                                 op->type = BARRIER + BARRIER_PTESYNC;
1014                                 break;
1015                         }
1016 #endif
1017                         return 1;
1018
1019                 case 854:       /* eieio */
1020                         op->type = BARRIER + BARRIER_EIEIO;
1021                         return 1;
1022                 }
1023                 break;
1024         }
1025
1026         /* Following cases refer to regs->gpr[], so we need all regs */
1027         if (!FULL_REGS(regs))
1028                 return -1;
1029
1030         rd = (instr >> 21) & 0x1f;
1031         ra = (instr >> 16) & 0x1f;
1032         rb = (instr >> 11) & 0x1f;
1033
1034         switch (opcode) {
1035 #ifdef __powerpc64__
1036         case 2:         /* tdi */
1037                 if (rd & trap_compare(regs->gpr[ra], (short) instr))
1038                         goto trap;
1039                 return 1;
1040 #endif
1041         case 3:         /* twi */
1042                 if (rd & trap_compare((int)regs->gpr[ra], (short) instr))
1043                         goto trap;
1044                 return 1;
1045
1046         case 7:         /* mulli */
1047                 op->val = regs->gpr[ra] * (short) instr;
1048                 goto compute_done;
1049
1050         case 8:         /* subfic */
1051                 imm = (short) instr;
1052                 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1053                 return 1;
1054
1055         case 10:        /* cmpli */
1056                 imm = (unsigned short) instr;
1057                 val = regs->gpr[ra];
1058 #ifdef __powerpc64__
1059                 if ((rd & 1) == 0)
1060                         val = (unsigned int) val;
1061 #endif
1062                 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1063                 return 1;
1064
1065         case 11:        /* cmpi */
1066                 imm = (short) instr;
1067                 val = regs->gpr[ra];
1068 #ifdef __powerpc64__
1069                 if ((rd & 1) == 0)
1070                         val = (int) val;
1071 #endif
1072                 do_cmp_signed(regs, op, val, imm, rd >> 2);
1073                 return 1;
1074
1075         case 12:        /* addic */
1076                 imm = (short) instr;
1077                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1078                 return 1;
1079
1080         case 13:        /* addic. */
1081                 imm = (short) instr;
1082                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1083                 set_cr0(regs, op, rd);
1084                 return 1;
1085
1086         case 14:        /* addi */
1087                 imm = (short) instr;
1088                 if (ra)
1089                         imm += regs->gpr[ra];
1090                 op->val = imm;
1091                 goto compute_done;
1092
1093         case 15:        /* addis */
1094                 imm = ((short) instr) << 16;
1095                 if (ra)
1096                         imm += regs->gpr[ra];
1097                 op->val = imm;
1098                 goto compute_done;
1099
1100         case 19:
1101                 if (((instr >> 1) & 0x1f) == 2) {
1102                         /* addpcis */
1103                         imm = (short) (instr & 0xffc1); /* d0 + d2 fields */
1104                         imm |= (instr >> 15) & 0x3e;    /* d1 field */
1105                         op->val = regs->nip + (imm << 16) + 4;
1106                         goto compute_done;
1107                 }
1108                 op->type = UNKNOWN;
1109                 return 0;
1110
1111         case 20:        /* rlwimi */
1112                 mb = (instr >> 6) & 0x1f;
1113                 me = (instr >> 1) & 0x1f;
1114                 val = DATA32(regs->gpr[rd]);
1115                 imm = MASK32(mb, me);
1116                 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1117                 goto logical_done;
1118
1119         case 21:        /* rlwinm */
1120                 mb = (instr >> 6) & 0x1f;
1121                 me = (instr >> 1) & 0x1f;
1122                 val = DATA32(regs->gpr[rd]);
1123                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1124                 goto logical_done;
1125
1126         case 23:        /* rlwnm */
1127                 mb = (instr >> 6) & 0x1f;
1128                 me = (instr >> 1) & 0x1f;
1129                 rb = regs->gpr[rb] & 0x1f;
1130                 val = DATA32(regs->gpr[rd]);
1131                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1132                 goto logical_done;
1133
1134         case 24:        /* ori */
1135                 op->val = regs->gpr[rd] | (unsigned short) instr;
1136                 goto logical_done_nocc;
1137
1138         case 25:        /* oris */
1139                 imm = (unsigned short) instr;
1140                 op->val = regs->gpr[rd] | (imm << 16);
1141                 goto logical_done_nocc;
1142
1143         case 26:        /* xori */
1144                 op->val = regs->gpr[rd] ^ (unsigned short) instr;
1145                 goto logical_done_nocc;
1146
1147         case 27:        /* xoris */
1148                 imm = (unsigned short) instr;
1149                 op->val = regs->gpr[rd] ^ (imm << 16);
1150                 goto logical_done_nocc;
1151
1152         case 28:        /* andi. */
1153                 op->val = regs->gpr[rd] & (unsigned short) instr;
1154                 set_cr0(regs, op, ra);
1155                 goto logical_done_nocc;
1156
1157         case 29:        /* andis. */
1158                 imm = (unsigned short) instr;
1159                 op->val = regs->gpr[rd] & (imm << 16);
1160                 set_cr0(regs, op, ra);
1161                 goto logical_done_nocc;
1162
1163 #ifdef __powerpc64__
1164         case 30:        /* rld* */
1165                 mb = ((instr >> 6) & 0x1f) | (instr & 0x20);
1166                 val = regs->gpr[rd];
1167                 if ((instr & 0x10) == 0) {
1168                         sh = rb | ((instr & 2) << 4);
1169                         val = ROTATE(val, sh);
1170                         switch ((instr >> 2) & 3) {
1171                         case 0:         /* rldicl */
1172                                 val &= MASK64_L(mb);
1173                                 break;
1174                         case 1:         /* rldicr */
1175                                 val &= MASK64_R(mb);
1176                                 break;
1177                         case 2:         /* rldic */
1178                                 val &= MASK64(mb, 63 - sh);
1179                                 break;
1180                         case 3:         /* rldimi */
1181                                 imm = MASK64(mb, 63 - sh);
1182                                 val = (regs->gpr[ra] & ~imm) |
1183                                         (val & imm);
1184                         }
1185                         op->val = val;
1186                         goto logical_done;
1187                 } else {
1188                         sh = regs->gpr[rb] & 0x3f;
1189                         val = ROTATE(val, sh);
1190                         switch ((instr >> 1) & 7) {
1191                         case 0:         /* rldcl */
1192                                 op->val = val & MASK64_L(mb);
1193                                 goto logical_done;
1194                         case 1:         /* rldcr */
1195                                 op->val = val & MASK64_R(mb);
1196                                 goto logical_done;
1197                         }
1198                 }
1199 #endif
1200                 op->type = UNKNOWN;     /* illegal instruction */
1201                 return 0;
1202
1203         case 31:
1204                 /* isel occupies 32 minor opcodes */
1205                 if (((instr >> 1) & 0x1f) == 15) {
1206                         mb = (instr >> 6) & 0x1f; /* bc field */
1207                         val = (regs->ccr >> (31 - mb)) & 1;
1208                         val2 = (ra) ? regs->gpr[ra] : 0;
1209
1210                         op->val = (val) ? val2 : regs->gpr[rb];
1211                         goto compute_done;
1212                 }
1213
1214                 switch ((instr >> 1) & 0x3ff) {
1215                 case 4:         /* tw */
1216                         if (rd == 0x1f ||
1217                             (rd & trap_compare((int)regs->gpr[ra],
1218                                                (int)regs->gpr[rb])))
1219                                 goto trap;
1220                         return 1;
1221 #ifdef __powerpc64__
1222                 case 68:        /* td */
1223                         if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1224                                 goto trap;
1225                         return 1;
1226 #endif
1227                 case 83:        /* mfmsr */
1228                         if (regs->msr & MSR_PR)
1229                                 goto priv;
1230                         op->type = MFMSR;
1231                         op->reg = rd;
1232                         return 0;
1233                 case 146:       /* mtmsr */
1234                         if (regs->msr & MSR_PR)
1235                                 goto priv;
1236                         op->type = MTMSR;
1237                         op->reg = rd;
1238                         op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1239                         return 0;
1240 #ifdef CONFIG_PPC64
1241                 case 178:       /* mtmsrd */
1242                         if (regs->msr & MSR_PR)
1243                                 goto priv;
1244                         op->type = MTMSR;
1245                         op->reg = rd;
1246                         /* only MSR_EE and MSR_RI get changed if bit 15 set */
1247                         /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1248                         imm = (instr & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1249                         op->val = imm;
1250                         return 0;
1251 #endif
1252
1253                 case 19:        /* mfcr */
1254                         imm = 0xffffffffUL;
1255                         if ((instr >> 20) & 1) {
1256                                 imm = 0xf0000000UL;
1257                                 for (sh = 0; sh < 8; ++sh) {
1258                                         if (instr & (0x80000 >> sh))
1259                                                 break;
1260                                         imm >>= 4;
1261                                 }
1262                         }
1263                         op->val = regs->ccr & imm;
1264                         goto compute_done;
1265
1266                 case 144:       /* mtcrf */
1267                         op->type = COMPUTE + SETCC;
1268                         imm = 0xf0000000UL;
1269                         val = regs->gpr[rd];
1270                         op->val = regs->ccr;
1271                         for (sh = 0; sh < 8; ++sh) {
1272                                 if (instr & (0x80000 >> sh))
1273                                         op->val = (op->val & ~imm) |
1274                                                 (val & imm);
1275                                 imm >>= 4;
1276                         }
1277                         return 1;
1278
1279                 case 339:       /* mfspr */
1280                         spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1281                         op->type = MFSPR;
1282                         op->reg = rd;
1283                         op->spr = spr;
1284                         if (spr == SPRN_XER || spr == SPRN_LR ||
1285                             spr == SPRN_CTR)
1286                                 return 1;
1287                         return 0;
1288
1289                 case 467:       /* mtspr */
1290                         spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1291                         op->type = MTSPR;
1292                         op->val = regs->gpr[rd];
1293                         op->spr = spr;
1294                         if (spr == SPRN_XER || spr == SPRN_LR ||
1295                             spr == SPRN_CTR)
1296                                 return 1;
1297                         return 0;
1298
1299 /*
1300  * Compare instructions
1301  */
1302                 case 0: /* cmp */
1303                         val = regs->gpr[ra];
1304                         val2 = regs->gpr[rb];
1305 #ifdef __powerpc64__
1306                         if ((rd & 1) == 0) {
1307                                 /* word (32-bit) compare */
1308                                 val = (int) val;
1309                                 val2 = (int) val2;
1310                         }
1311 #endif
1312                         do_cmp_signed(regs, op, val, val2, rd >> 2);
1313                         return 1;
1314
1315                 case 32:        /* cmpl */
1316                         val = regs->gpr[ra];
1317                         val2 = regs->gpr[rb];
1318 #ifdef __powerpc64__
1319                         if ((rd & 1) == 0) {
1320                                 /* word (32-bit) compare */
1321                                 val = (unsigned int) val;
1322                                 val2 = (unsigned int) val2;
1323                         }
1324 #endif
1325                         do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1326                         return 1;
1327
1328                 case 508: /* cmpb */
1329                         do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1330                         goto logical_done_nocc;
1331
1332 /*
1333  * Arithmetic instructions
1334  */
1335                 case 8: /* subfc */
1336                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1337                                        regs->gpr[rb], 1);
1338                         goto arith_done;
1339 #ifdef __powerpc64__
1340                 case 9: /* mulhdu */
1341                         asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1342                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1343                         goto arith_done;
1344 #endif
1345                 case 10:        /* addc */
1346                         add_with_carry(regs, op, rd, regs->gpr[ra],
1347                                        regs->gpr[rb], 0);
1348                         goto arith_done;
1349
1350                 case 11:        /* mulhwu */
1351                         asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1352                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1353                         goto arith_done;
1354
1355                 case 40:        /* subf */
1356                         op->val = regs->gpr[rb] - regs->gpr[ra];
1357                         goto arith_done;
1358 #ifdef __powerpc64__
1359                 case 73:        /* mulhd */
1360                         asm("mulhd %0,%1,%2" : "=r" (op->val) :
1361                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1362                         goto arith_done;
1363 #endif
1364                 case 75:        /* mulhw */
1365                         asm("mulhw %0,%1,%2" : "=r" (op->val) :
1366                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1367                         goto arith_done;
1368
1369                 case 104:       /* neg */
1370                         op->val = -regs->gpr[ra];
1371                         goto arith_done;
1372
1373                 case 136:       /* subfe */
1374                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1375                                        regs->gpr[rb], regs->xer & XER_CA);
1376                         goto arith_done;
1377
1378                 case 138:       /* adde */
1379                         add_with_carry(regs, op, rd, regs->gpr[ra],
1380                                        regs->gpr[rb], regs->xer & XER_CA);
1381                         goto arith_done;
1382
1383                 case 200:       /* subfze */
1384                         add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1385                                        regs->xer & XER_CA);
1386                         goto arith_done;
1387
1388                 case 202:       /* addze */
1389                         add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1390                                        regs->xer & XER_CA);
1391                         goto arith_done;
1392
1393                 case 232:       /* subfme */
1394                         add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1395                                        regs->xer & XER_CA);
1396                         goto arith_done;
1397 #ifdef __powerpc64__
1398                 case 233:       /* mulld */
1399                         op->val = regs->gpr[ra] * regs->gpr[rb];
1400                         goto arith_done;
1401 #endif
1402                 case 234:       /* addme */
1403                         add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1404                                        regs->xer & XER_CA);
1405                         goto arith_done;
1406
1407                 case 235:       /* mullw */
1408                         op->val = (unsigned int) regs->gpr[ra] *
1409                                 (unsigned int) regs->gpr[rb];
1410                         goto arith_done;
1411
1412                 case 266:       /* add */
1413                         op->val = regs->gpr[ra] + regs->gpr[rb];
1414                         goto arith_done;
1415 #ifdef __powerpc64__
1416                 case 457:       /* divdu */
1417                         op->val = regs->gpr[ra] / regs->gpr[rb];
1418                         goto arith_done;
1419 #endif
1420                 case 459:       /* divwu */
1421                         op->val = (unsigned int) regs->gpr[ra] /
1422                                 (unsigned int) regs->gpr[rb];
1423                         goto arith_done;
1424 #ifdef __powerpc64__
1425                 case 489:       /* divd */
1426                         op->val = (long int) regs->gpr[ra] /
1427                                 (long int) regs->gpr[rb];
1428                         goto arith_done;
1429 #endif
1430                 case 491:       /* divw */
1431                         op->val = (int) regs->gpr[ra] /
1432                                 (int) regs->gpr[rb];
1433                         goto arith_done;
1434
1435
1436 /*
1437  * Logical instructions
1438  */
1439                 case 26:        /* cntlzw */
1440                         op->val = __builtin_clz((unsigned int) regs->gpr[rd]);
1441                         goto logical_done;
1442 #ifdef __powerpc64__
1443                 case 58:        /* cntlzd */
1444                         op->val = __builtin_clzl(regs->gpr[rd]);
1445                         goto logical_done;
1446 #endif
1447                 case 28:        /* and */
1448                         op->val = regs->gpr[rd] & regs->gpr[rb];
1449                         goto logical_done;
1450
1451                 case 60:        /* andc */
1452                         op->val = regs->gpr[rd] & ~regs->gpr[rb];
1453                         goto logical_done;
1454
1455                 case 122:       /* popcntb */
1456                         do_popcnt(regs, op, regs->gpr[rd], 8);
1457                         goto logical_done_nocc;
1458
1459                 case 124:       /* nor */
1460                         op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1461                         goto logical_done;
1462
1463                 case 154:       /* prtyw */
1464                         do_prty(regs, op, regs->gpr[rd], 32);
1465                         goto logical_done_nocc;
1466
1467                 case 186:       /* prtyd */
1468                         do_prty(regs, op, regs->gpr[rd], 64);
1469                         goto logical_done_nocc;
1470 #ifdef CONFIG_PPC64
1471                 case 252:       /* bpermd */
1472                         do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1473                         goto logical_done_nocc;
1474 #endif
1475                 case 284:       /* xor */
1476                         op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1477                         goto logical_done;
1478
1479                 case 316:       /* xor */
1480                         op->val = regs->gpr[rd] ^ regs->gpr[rb];
1481                         goto logical_done;
1482
1483                 case 378:       /* popcntw */
1484                         do_popcnt(regs, op, regs->gpr[rd], 32);
1485                         goto logical_done_nocc;
1486
1487                 case 412:       /* orc */
1488                         op->val = regs->gpr[rd] | ~regs->gpr[rb];
1489                         goto logical_done;
1490
1491                 case 444:       /* or */
1492                         op->val = regs->gpr[rd] | regs->gpr[rb];
1493                         goto logical_done;
1494
1495                 case 476:       /* nand */
1496                         op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1497                         goto logical_done;
1498 #ifdef CONFIG_PPC64
1499                 case 506:       /* popcntd */
1500                         do_popcnt(regs, op, regs->gpr[rd], 64);
1501                         goto logical_done_nocc;
1502 #endif
1503                 case 922:       /* extsh */
1504                         op->val = (signed short) regs->gpr[rd];
1505                         goto logical_done;
1506
1507                 case 954:       /* extsb */
1508                         op->val = (signed char) regs->gpr[rd];
1509                         goto logical_done;
1510 #ifdef __powerpc64__
1511                 case 986:       /* extsw */
1512                         op->val = (signed int) regs->gpr[rd];
1513                         goto logical_done;
1514 #endif
1515
1516 /*
1517  * Shift instructions
1518  */
1519                 case 24:        /* slw */
1520                         sh = regs->gpr[rb] & 0x3f;
1521                         if (sh < 32)
1522                                 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
1523                         else
1524                                 op->val = 0;
1525                         goto logical_done;
1526
1527                 case 536:       /* srw */
1528                         sh = regs->gpr[rb] & 0x3f;
1529                         if (sh < 32)
1530                                 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
1531                         else
1532                                 op->val = 0;
1533                         goto logical_done;
1534
1535                 case 792:       /* sraw */
1536                         op->type = COMPUTE + SETREG + SETXER;
1537                         sh = regs->gpr[rb] & 0x3f;
1538                         ival = (signed int) regs->gpr[rd];
1539                         op->val = ival >> (sh < 32 ? sh : 31);
1540                         op->xerval = regs->xer;
1541                         if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
1542                                 op->xerval |= XER_CA;
1543                         else
1544                                 op->xerval &= ~XER_CA;
1545                         goto logical_done;
1546
1547                 case 824:       /* srawi */
1548                         op->type = COMPUTE + SETREG + SETXER;
1549                         sh = rb;
1550                         ival = (signed int) regs->gpr[rd];
1551                         op->val = ival >> sh;
1552                         op->xerval = regs->xer;
1553                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1554                                 op->xerval |= XER_CA;
1555                         else
1556                                 op->xerval &= ~XER_CA;
1557                         goto logical_done;
1558
1559 #ifdef __powerpc64__
1560                 case 27:        /* sld */
1561                         sh = regs->gpr[rb] & 0x7f;
1562                         if (sh < 64)
1563                                 op->val = regs->gpr[rd] << sh;
1564                         else
1565                                 op->val = 0;
1566                         goto logical_done;
1567
1568                 case 539:       /* srd */
1569                         sh = regs->gpr[rb] & 0x7f;
1570                         if (sh < 64)
1571                                 op->val = regs->gpr[rd] >> sh;
1572                         else
1573                                 op->val = 0;
1574                         goto logical_done;
1575
1576                 case 794:       /* srad */
1577                         op->type = COMPUTE + SETREG + SETXER;
1578                         sh = regs->gpr[rb] & 0x7f;
1579                         ival = (signed long int) regs->gpr[rd];
1580                         op->val = ival >> (sh < 64 ? sh : 63);
1581                         op->xerval = regs->xer;
1582                         if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
1583                                 op->xerval |= XER_CA;
1584                         else
1585                                 op->xerval &= ~XER_CA;
1586                         goto logical_done;
1587
1588                 case 826:       /* sradi with sh_5 = 0 */
1589                 case 827:       /* sradi with sh_5 = 1 */
1590                         op->type = COMPUTE + SETREG + SETXER;
1591                         sh = rb | ((instr & 2) << 4);
1592                         ival = (signed long int) regs->gpr[rd];
1593                         op->val = ival >> sh;
1594                         op->xerval = regs->xer;
1595                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1596                                 op->xerval |= XER_CA;
1597                         else
1598                                 op->xerval &= ~XER_CA;
1599                         goto logical_done;
1600 #endif /* __powerpc64__ */
1601
1602 /*
1603  * Cache instructions
1604  */
1605                 case 54:        /* dcbst */
1606                         op->type = MKOP(CACHEOP, DCBST, 0);
1607                         op->ea = xform_ea(instr, regs);
1608                         return 0;
1609
1610                 case 86:        /* dcbf */
1611                         op->type = MKOP(CACHEOP, DCBF, 0);
1612                         op->ea = xform_ea(instr, regs);
1613                         return 0;
1614
1615                 case 246:       /* dcbtst */
1616                         op->type = MKOP(CACHEOP, DCBTST, 0);
1617                         op->ea = xform_ea(instr, regs);
1618                         op->reg = rd;
1619                         return 0;
1620
1621                 case 278:       /* dcbt */
1622                         op->type = MKOP(CACHEOP, DCBTST, 0);
1623                         op->ea = xform_ea(instr, regs);
1624                         op->reg = rd;
1625                         return 0;
1626
1627                 case 982:       /* icbi */
1628                         op->type = MKOP(CACHEOP, ICBI, 0);
1629                         op->ea = xform_ea(instr, regs);
1630                         return 0;
1631                 }
1632                 break;
1633         }
1634
1635 /*
1636  * Loads and stores.
1637  */
1638         op->type = UNKNOWN;
1639         op->update_reg = ra;
1640         op->reg = rd;
1641         op->val = regs->gpr[rd];
1642         u = (instr >> 20) & UPDATE;
1643         op->vsx_flags = 0;
1644
1645         switch (opcode) {
1646         case 31:
1647                 u = instr & UPDATE;
1648                 op->ea = xform_ea(instr, regs);
1649                 switch ((instr >> 1) & 0x3ff) {
1650                 case 20:        /* lwarx */
1651                         op->type = MKOP(LARX, 0, 4);
1652                         break;
1653
1654                 case 150:       /* stwcx. */
1655                         op->type = MKOP(STCX, 0, 4);
1656                         break;
1657
1658 #ifdef __powerpc64__
1659                 case 84:        /* ldarx */
1660                         op->type = MKOP(LARX, 0, 8);
1661                         break;
1662
1663                 case 214:       /* stdcx. */
1664                         op->type = MKOP(STCX, 0, 8);
1665                         break;
1666
1667                 case 52:        /* lbarx */
1668                         op->type = MKOP(LARX, 0, 1);
1669                         break;
1670
1671                 case 694:       /* stbcx. */
1672                         op->type = MKOP(STCX, 0, 1);
1673                         break;
1674
1675                 case 116:       /* lharx */
1676                         op->type = MKOP(LARX, 0, 2);
1677                         break;
1678
1679                 case 726:       /* sthcx. */
1680                         op->type = MKOP(STCX, 0, 2);
1681                         break;
1682
1683                 case 276:       /* lqarx */
1684                         if (!((rd & 1) || rd == ra || rd == rb))
1685                                 op->type = MKOP(LARX, 0, 16);
1686                         break;
1687
1688                 case 182:       /* stqcx. */
1689                         if (!(rd & 1))
1690                                 op->type = MKOP(STCX, 0, 16);
1691                         break;
1692 #endif
1693
1694                 case 23:        /* lwzx */
1695                 case 55:        /* lwzux */
1696                         op->type = MKOP(LOAD, u, 4);
1697                         break;
1698
1699                 case 87:        /* lbzx */
1700                 case 119:       /* lbzux */
1701                         op->type = MKOP(LOAD, u, 1);
1702                         break;
1703
1704 #ifdef CONFIG_ALTIVEC
1705                 case 103:       /* lvx */
1706                 case 359:       /* lvxl */
1707                         op->type = MKOP(LOAD_VMX, 0, 16);
1708                         op->element_size = 16;
1709                         break;
1710
1711                 case 231:       /* stvx */
1712                 case 487:       /* stvxl */
1713                         op->type = MKOP(STORE_VMX, 0, 16);
1714                         break;
1715 #endif /* CONFIG_ALTIVEC */
1716
1717 #ifdef __powerpc64__
1718                 case 21:        /* ldx */
1719                 case 53:        /* ldux */
1720                         op->type = MKOP(LOAD, u, 8);
1721                         break;
1722
1723                 case 149:       /* stdx */
1724                 case 181:       /* stdux */
1725                         op->type = MKOP(STORE, u, 8);
1726                         break;
1727 #endif
1728
1729                 case 151:       /* stwx */
1730                 case 183:       /* stwux */
1731                         op->type = MKOP(STORE, u, 4);
1732                         break;
1733
1734                 case 215:       /* stbx */
1735                 case 247:       /* stbux */
1736                         op->type = MKOP(STORE, u, 1);
1737                         break;
1738
1739                 case 279:       /* lhzx */
1740                 case 311:       /* lhzux */
1741                         op->type = MKOP(LOAD, u, 2);
1742                         break;
1743
1744 #ifdef __powerpc64__
1745                 case 341:       /* lwax */
1746                 case 373:       /* lwaux */
1747                         op->type = MKOP(LOAD, SIGNEXT | u, 4);
1748                         break;
1749 #endif
1750
1751                 case 343:       /* lhax */
1752                 case 375:       /* lhaux */
1753                         op->type = MKOP(LOAD, SIGNEXT | u, 2);
1754                         break;
1755
1756                 case 407:       /* sthx */
1757                 case 439:       /* sthux */
1758                         op->type = MKOP(STORE, u, 2);
1759                         break;
1760
1761 #ifdef __powerpc64__
1762                 case 532:       /* ldbrx */
1763                         op->type = MKOP(LOAD, BYTEREV, 8);
1764                         break;
1765
1766 #endif
1767                 case 533:       /* lswx */
1768                         op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
1769                         break;
1770
1771                 case 534:       /* lwbrx */
1772                         op->type = MKOP(LOAD, BYTEREV, 4);
1773                         break;
1774
1775                 case 597:       /* lswi */
1776                         if (rb == 0)
1777                                 rb = 32;        /* # bytes to load */
1778                         op->type = MKOP(LOAD_MULTI, 0, rb);
1779                         op->ea = ra ? regs->gpr[ra] : 0;
1780                         break;
1781
1782 #ifdef CONFIG_PPC_FPU
1783                 case 535:       /* lfsx */
1784                 case 567:       /* lfsux */
1785                         op->type = MKOP(LOAD_FP, u, 4);
1786                         break;
1787
1788                 case 599:       /* lfdx */
1789                 case 631:       /* lfdux */
1790                         op->type = MKOP(LOAD_FP, u, 8);
1791                         break;
1792
1793                 case 663:       /* stfsx */
1794                 case 695:       /* stfsux */
1795                         op->type = MKOP(STORE_FP, u, 4);
1796                         break;
1797
1798                 case 727:       /* stfdx */
1799                 case 759:       /* stfdux */
1800                         op->type = MKOP(STORE_FP, u, 8);
1801                         break;
1802 #endif
1803
1804 #ifdef __powerpc64__
1805                 case 660:       /* stdbrx */
1806                         op->type = MKOP(STORE, BYTEREV, 8);
1807                         op->val = byterev_8(regs->gpr[rd]);
1808                         break;
1809
1810 #endif
1811                 case 661:       /* stswx */
1812                         op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
1813                         break;
1814
1815                 case 662:       /* stwbrx */
1816                         op->type = MKOP(STORE, BYTEREV, 4);
1817                         op->val = byterev_4(regs->gpr[rd]);
1818                         break;
1819
1820                 case 725:
1821                         if (rb == 0)
1822                                 rb = 32;        /* # bytes to store */
1823                         op->type = MKOP(STORE_MULTI, 0, rb);
1824                         op->ea = ra ? regs->gpr[ra] : 0;
1825                         break;
1826
1827                 case 790:       /* lhbrx */
1828                         op->type = MKOP(LOAD, BYTEREV, 2);
1829                         break;
1830
1831                 case 918:       /* sthbrx */
1832                         op->type = MKOP(STORE, BYTEREV, 2);
1833                         op->val = byterev_2(regs->gpr[rd]);
1834                         break;
1835
1836 #ifdef CONFIG_VSX
1837                 case 12:        /* lxsiwzx */
1838                         op->reg = rd | ((instr & 1) << 5);
1839                         op->type = MKOP(LOAD_VSX, 0, 4);
1840                         op->element_size = 8;
1841                         break;
1842
1843                 case 76:        /* lxsiwax */
1844                         op->reg = rd | ((instr & 1) << 5);
1845                         op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
1846                         op->element_size = 8;
1847                         break;
1848
1849                 case 140:       /* stxsiwx */
1850                         op->reg = rd | ((instr & 1) << 5);
1851                         op->type = MKOP(STORE_VSX, 0, 4);
1852                         op->element_size = 8;
1853                         break;
1854
1855                 case 268:       /* lxvx */
1856                         op->reg = rd | ((instr & 1) << 5);
1857                         op->type = MKOP(LOAD_VSX, 0, 16);
1858                         op->element_size = 16;
1859                         op->vsx_flags = VSX_CHECK_VEC;
1860                         break;
1861
1862                 case 269:       /* lxvl */
1863                 case 301: {     /* lxvll */
1864                         int nb;
1865                         op->reg = rd | ((instr & 1) << 5);
1866                         op->ea = ra ? regs->gpr[ra] : 0;
1867                         nb = regs->gpr[rb] & 0xff;
1868                         if (nb > 16)
1869                                 nb = 16;
1870                         op->type = MKOP(LOAD_VSX, 0, nb);
1871                         op->element_size = 16;
1872                         op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
1873                                 VSX_CHECK_VEC;
1874                         break;
1875                 }
1876                 case 332:       /* lxvdsx */
1877                         op->reg = rd | ((instr & 1) << 5);
1878                         op->type = MKOP(LOAD_VSX, 0, 8);
1879                         op->element_size = 8;
1880                         op->vsx_flags = VSX_SPLAT;
1881                         break;
1882
1883                 case 364:       /* lxvwsx */
1884                         op->reg = rd | ((instr & 1) << 5);
1885                         op->type = MKOP(LOAD_VSX, 0, 4);
1886                         op->element_size = 4;
1887                         op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
1888                         break;
1889
1890                 case 396:       /* stxvx */
1891                         op->reg = rd | ((instr & 1) << 5);
1892                         op->type = MKOP(STORE_VSX, 0, 16);
1893                         op->element_size = 16;
1894                         op->vsx_flags = VSX_CHECK_VEC;
1895                         break;
1896
1897                 case 397:       /* stxvl */
1898                 case 429: {     /* stxvll */
1899                         int nb;
1900                         op->reg = rd | ((instr & 1) << 5);
1901                         op->ea = ra ? regs->gpr[ra] : 0;
1902                         nb = regs->gpr[rb] & 0xff;
1903                         if (nb > 16)
1904                                 nb = 16;
1905                         op->type = MKOP(STORE_VSX, 0, nb);
1906                         op->element_size = 16;
1907                         op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
1908                                 VSX_CHECK_VEC;
1909                         break;
1910                 }
1911                 case 524:       /* lxsspx */
1912                         op->reg = rd | ((instr & 1) << 5);
1913                         op->type = MKOP(LOAD_VSX, 0, 4);
1914                         op->element_size = 8;
1915                         op->vsx_flags = VSX_FPCONV;
1916                         break;
1917
1918                 case 588:       /* lxsdx */
1919                         op->reg = rd | ((instr & 1) << 5);
1920                         op->type = MKOP(LOAD_VSX, 0, 8);
1921                         op->element_size = 8;
1922                         break;
1923
1924                 case 652:       /* stxsspx */
1925                         op->reg = rd | ((instr & 1) << 5);
1926                         op->type = MKOP(STORE_VSX, 0, 4);
1927                         op->element_size = 8;
1928                         op->vsx_flags = VSX_FPCONV;
1929                         break;
1930
1931                 case 716:       /* stxsdx */
1932                         op->reg = rd | ((instr & 1) << 5);
1933                         op->type = MKOP(STORE_VSX, 0, 8);
1934                         op->element_size = 8;
1935                         break;
1936
1937                 case 780:       /* lxvw4x */
1938                         op->reg = rd | ((instr & 1) << 5);
1939                         op->type = MKOP(LOAD_VSX, 0, 16);
1940                         op->element_size = 4;
1941                         break;
1942
1943                 case 781:       /* lxsibzx */
1944                         op->reg = rd | ((instr & 1) << 5);
1945                         op->type = MKOP(LOAD_VSX, 0, 1);
1946                         op->element_size = 8;
1947                         op->vsx_flags = VSX_CHECK_VEC;
1948                         break;
1949
1950                 case 812:       /* lxvh8x */
1951                         op->reg = rd | ((instr & 1) << 5);
1952                         op->type = MKOP(LOAD_VSX, 0, 16);
1953                         op->element_size = 2;
1954                         op->vsx_flags = VSX_CHECK_VEC;
1955                         break;
1956
1957                 case 813:       /* lxsihzx */
1958                         op->reg = rd | ((instr & 1) << 5);
1959                         op->type = MKOP(LOAD_VSX, 0, 2);
1960                         op->element_size = 8;
1961                         op->vsx_flags = VSX_CHECK_VEC;
1962                         break;
1963
1964                 case 844:       /* lxvd2x */
1965                         op->reg = rd | ((instr & 1) << 5);
1966                         op->type = MKOP(LOAD_VSX, 0, 16);
1967                         op->element_size = 8;
1968                         break;
1969
1970                 case 876:       /* lxvb16x */
1971                         op->reg = rd | ((instr & 1) << 5);
1972                         op->type = MKOP(LOAD_VSX, 0, 16);
1973                         op->element_size = 1;
1974                         op->vsx_flags = VSX_CHECK_VEC;
1975                         break;
1976
1977                 case 908:       /* stxvw4x */
1978                         op->reg = rd | ((instr & 1) << 5);
1979                         op->type = MKOP(STORE_VSX, 0, 16);
1980                         op->element_size = 4;
1981                         break;
1982
1983                 case 909:       /* stxsibx */
1984                         op->reg = rd | ((instr & 1) << 5);
1985                         op->type = MKOP(STORE_VSX, 0, 1);
1986                         op->element_size = 8;
1987                         op->vsx_flags = VSX_CHECK_VEC;
1988                         break;
1989
1990                 case 940:       /* stxvh8x */
1991                         op->reg = rd | ((instr & 1) << 5);
1992                         op->type = MKOP(STORE_VSX, 0, 16);
1993                         op->element_size = 2;
1994                         op->vsx_flags = VSX_CHECK_VEC;
1995                         break;
1996
1997                 case 941:       /* stxsihx */
1998                         op->reg = rd | ((instr & 1) << 5);
1999                         op->type = MKOP(STORE_VSX, 0, 2);
2000                         op->element_size = 8;
2001                         op->vsx_flags = VSX_CHECK_VEC;
2002                         break;
2003
2004                 case 972:       /* stxvd2x */
2005                         op->reg = rd | ((instr & 1) << 5);
2006                         op->type = MKOP(STORE_VSX, 0, 16);
2007                         op->element_size = 8;
2008                         break;
2009
2010                 case 1004:      /* stxvb16x */
2011                         op->reg = rd | ((instr & 1) << 5);
2012                         op->type = MKOP(STORE_VSX, 0, 16);
2013                         op->element_size = 1;
2014                         op->vsx_flags = VSX_CHECK_VEC;
2015                         break;
2016
2017 #endif /* CONFIG_VSX */
2018                 }
2019                 break;
2020
2021         case 32:        /* lwz */
2022         case 33:        /* lwzu */
2023                 op->type = MKOP(LOAD, u, 4);
2024                 op->ea = dform_ea(instr, regs);
2025                 break;
2026
2027         case 34:        /* lbz */
2028         case 35:        /* lbzu */
2029                 op->type = MKOP(LOAD, u, 1);
2030                 op->ea = dform_ea(instr, regs);
2031                 break;
2032
2033         case 36:        /* stw */
2034         case 37:        /* stwu */
2035                 op->type = MKOP(STORE, u, 4);
2036                 op->ea = dform_ea(instr, regs);
2037                 break;
2038
2039         case 38:        /* stb */
2040         case 39:        /* stbu */
2041                 op->type = MKOP(STORE, u, 1);
2042                 op->ea = dform_ea(instr, regs);
2043                 break;
2044
2045         case 40:        /* lhz */
2046         case 41:        /* lhzu */
2047                 op->type = MKOP(LOAD, u, 2);
2048                 op->ea = dform_ea(instr, regs);
2049                 break;
2050
2051         case 42:        /* lha */
2052         case 43:        /* lhau */
2053                 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2054                 op->ea = dform_ea(instr, regs);
2055                 break;
2056
2057         case 44:        /* sth */
2058         case 45:        /* sthu */
2059                 op->type = MKOP(STORE, u, 2);
2060                 op->ea = dform_ea(instr, regs);
2061                 break;
2062
2063         case 46:        /* lmw */
2064                 if (ra >= rd)
2065                         break;          /* invalid form, ra in range to load */
2066                 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2067                 op->ea = dform_ea(instr, regs);
2068                 break;
2069
2070         case 47:        /* stmw */
2071                 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2072                 op->ea = dform_ea(instr, regs);
2073                 break;
2074
2075 #ifdef CONFIG_PPC_FPU
2076         case 48:        /* lfs */
2077         case 49:        /* lfsu */
2078                 op->type = MKOP(LOAD_FP, u, 4);
2079                 op->ea = dform_ea(instr, regs);
2080                 break;
2081
2082         case 50:        /* lfd */
2083         case 51:        /* lfdu */
2084                 op->type = MKOP(LOAD_FP, u, 8);
2085                 op->ea = dform_ea(instr, regs);
2086                 break;
2087
2088         case 52:        /* stfs */
2089         case 53:        /* stfsu */
2090                 op->type = MKOP(STORE_FP, u, 4);
2091                 op->ea = dform_ea(instr, regs);
2092                 break;
2093
2094         case 54:        /* stfd */
2095         case 55:        /* stfdu */
2096                 op->type = MKOP(STORE_FP, u, 8);
2097                 op->ea = dform_ea(instr, regs);
2098                 break;
2099 #endif
2100
2101 #ifdef __powerpc64__
2102         case 56:        /* lq */
2103                 if (!((rd & 1) || (rd == ra)))
2104                         op->type = MKOP(LOAD, 0, 16);
2105                 op->ea = dqform_ea(instr, regs);
2106                 break;
2107 #endif
2108
2109 #ifdef CONFIG_VSX
2110         case 57:        /* lxsd, lxssp */
2111                 op->ea = dsform_ea(instr, regs);
2112                 switch (instr & 3) {
2113                 case 2:         /* lxsd */
2114                         op->reg = rd + 32;
2115                         op->type = MKOP(LOAD_VSX, 0, 8);
2116                         op->element_size = 8;
2117                         op->vsx_flags = VSX_CHECK_VEC;
2118                         break;
2119                 case 3:         /* lxssp */
2120                         op->reg = rd + 32;
2121                         op->type = MKOP(LOAD_VSX, 0, 4);
2122                         op->element_size = 8;
2123                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2124                         break;
2125                 }
2126                 break;
2127 #endif /* CONFIG_VSX */
2128
2129 #ifdef __powerpc64__
2130         case 58:        /* ld[u], lwa */
2131                 op->ea = dsform_ea(instr, regs);
2132                 switch (instr & 3) {
2133                 case 0:         /* ld */
2134                         op->type = MKOP(LOAD, 0, 8);
2135                         break;
2136                 case 1:         /* ldu */
2137                         op->type = MKOP(LOAD, UPDATE, 8);
2138                         break;
2139                 case 2:         /* lwa */
2140                         op->type = MKOP(LOAD, SIGNEXT, 4);
2141                         break;
2142                 }
2143                 break;
2144 #endif
2145
2146 #ifdef CONFIG_VSX
2147         case 61:        /* lxv, stxsd, stxssp, stxv */
2148                 switch (instr & 7) {
2149                 case 1:         /* lxv */
2150                         op->ea = dqform_ea(instr, regs);
2151                         if (instr & 8)
2152                                 op->reg = rd + 32;
2153                         op->type = MKOP(LOAD_VSX, 0, 16);
2154                         op->element_size = 16;
2155                         op->vsx_flags = VSX_CHECK_VEC;
2156                         break;
2157
2158                 case 2:         /* stxsd with LSB of DS field = 0 */
2159                 case 6:         /* stxsd with LSB of DS field = 1 */
2160                         op->ea = dsform_ea(instr, regs);
2161                         op->reg = rd + 32;
2162                         op->type = MKOP(STORE_VSX, 0, 8);
2163                         op->element_size = 8;
2164                         op->vsx_flags = VSX_CHECK_VEC;
2165                         break;
2166
2167                 case 3:         /* stxssp with LSB of DS field = 0 */
2168                 case 7:         /* stxssp with LSB of DS field = 1 */
2169                         op->ea = dsform_ea(instr, regs);
2170                         op->reg = rd + 32;
2171                         op->type = MKOP(STORE_VSX, 0, 4);
2172                         op->element_size = 8;
2173                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2174                         break;
2175
2176                 case 5:         /* stxv */
2177                         op->ea = dqform_ea(instr, regs);
2178                         if (instr & 8)
2179                                 op->reg = rd + 32;
2180                         op->type = MKOP(STORE_VSX, 0, 16);
2181                         op->element_size = 16;
2182                         op->vsx_flags = VSX_CHECK_VEC;
2183                         break;
2184                 }
2185                 break;
2186 #endif /* CONFIG_VSX */
2187
2188 #ifdef __powerpc64__
2189         case 62:        /* std[u] */
2190                 op->ea = dsform_ea(instr, regs);
2191                 switch (instr & 3) {
2192                 case 0:         /* std */
2193                         op->type = MKOP(STORE, 0, 8);
2194                         break;
2195                 case 1:         /* stdu */
2196                         op->type = MKOP(STORE, UPDATE, 8);
2197                         break;
2198                 case 2:         /* stq */
2199                         if (!(rd & 1))
2200                                 op->type = MKOP(STORE, 0, 16);
2201                         break;
2202                 }
2203                 break;
2204 #endif /* __powerpc64__ */
2205
2206         }
2207         return 0;
2208
2209  logical_done:
2210         if (instr & 1)
2211                 set_cr0(regs, op, ra);
2212  logical_done_nocc:
2213         op->reg = ra;
2214         op->type |= SETREG;
2215         return 1;
2216
2217  arith_done:
2218         if (instr & 1)
2219                 set_cr0(regs, op, rd);
2220  compute_done:
2221         op->reg = rd;
2222         op->type |= SETREG;
2223         return 1;
2224
2225  priv:
2226         op->type = INTERRUPT | 0x700;
2227         op->val = SRR1_PROGPRIV;
2228         return 0;
2229
2230  trap:
2231         op->type = INTERRUPT | 0x700;
2232         op->val = SRR1_PROGTRAP;
2233         return 0;
2234 }
2235 EXPORT_SYMBOL_GPL(analyse_instr);
2236 NOKPROBE_SYMBOL(analyse_instr);
2237
2238 /*
2239  * For PPC32 we always use stwu with r1 to change the stack pointer.
2240  * So this emulated store may corrupt the exception frame, now we
2241  * have to provide the exception frame trampoline, which is pushed
2242  * below the kprobed function stack. So we only update gpr[1] but
2243  * don't emulate the real store operation. We will do real store
2244  * operation safely in exception return code by checking this flag.
2245  */
2246 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
2247 {
2248 #ifdef CONFIG_PPC32
2249         /*
2250          * Check if we will touch kernel stack overflow
2251          */
2252         if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
2253                 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n");
2254                 return -EINVAL;
2255         }
2256 #endif /* CONFIG_PPC32 */
2257         /*
2258          * Check if we already set since that means we'll
2259          * lose the previous value.
2260          */
2261         WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
2262         set_thread_flag(TIF_EMULATE_STACK_STORE);
2263         return 0;
2264 }
2265
2266 static nokprobe_inline void do_signext(unsigned long *valp, int size)
2267 {
2268         switch (size) {
2269         case 2:
2270                 *valp = (signed short) *valp;
2271                 break;
2272         case 4:
2273                 *valp = (signed int) *valp;
2274                 break;
2275         }
2276 }
2277
2278 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
2279 {
2280         switch (size) {
2281         case 2:
2282                 *valp = byterev_2(*valp);
2283                 break;
2284         case 4:
2285                 *valp = byterev_4(*valp);
2286                 break;
2287 #ifdef __powerpc64__
2288         case 8:
2289                 *valp = byterev_8(*valp);
2290                 break;
2291 #endif
2292         }
2293 }
2294
2295 /*
2296  * Emulate an instruction that can be executed just by updating
2297  * fields in *regs.
2298  */
2299 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
2300 {
2301         unsigned long next_pc;
2302
2303         next_pc = truncate_if_32bit(regs->msr, regs->nip + 4);
2304         switch (op->type & INSTR_TYPE_MASK) {
2305         case COMPUTE:
2306                 if (op->type & SETREG)
2307                         regs->gpr[op->reg] = op->val;
2308                 if (op->type & SETCC)
2309                         regs->ccr = op->ccval;
2310                 if (op->type & SETXER)
2311                         regs->xer = op->xerval;
2312                 break;
2313
2314         case BRANCH:
2315                 if (op->type & SETLK)
2316                         regs->link = next_pc;
2317                 if (op->type & BRTAKEN)
2318                         next_pc = op->val;
2319                 if (op->type & DECCTR)
2320                         --regs->ctr;
2321                 break;
2322
2323         case BARRIER:
2324                 switch (op->type & BARRIER_MASK) {
2325                 case BARRIER_SYNC:
2326                         mb();
2327                         break;
2328                 case BARRIER_ISYNC:
2329                         isync();
2330                         break;
2331                 case BARRIER_EIEIO:
2332                         eieio();
2333                         break;
2334                 case BARRIER_LWSYNC:
2335                         asm volatile("lwsync" : : : "memory");
2336                         break;
2337                 case BARRIER_PTESYNC:
2338                         asm volatile("ptesync" : : : "memory");
2339                         break;
2340                 }
2341                 break;
2342
2343         case MFSPR:
2344                 switch (op->spr) {
2345                 case SPRN_XER:
2346                         regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
2347                         break;
2348                 case SPRN_LR:
2349                         regs->gpr[op->reg] = regs->link;
2350                         break;
2351                 case SPRN_CTR:
2352                         regs->gpr[op->reg] = regs->ctr;
2353                         break;
2354                 default:
2355                         WARN_ON_ONCE(1);
2356                 }
2357                 break;
2358
2359         case MTSPR:
2360                 switch (op->spr) {
2361                 case SPRN_XER:
2362                         regs->xer = op->val & 0xffffffffUL;
2363                         break;
2364                 case SPRN_LR:
2365                         regs->link = op->val;
2366                         break;
2367                 case SPRN_CTR:
2368                         regs->ctr = op->val;
2369                         break;
2370                 default:
2371                         WARN_ON_ONCE(1);
2372                 }
2373                 break;
2374
2375         default:
2376                 WARN_ON_ONCE(1);
2377         }
2378         regs->nip = next_pc;
2379 }
2380
2381 /*
2382  * Emulate instructions that cause a transfer of control,
2383  * loads and stores, and a few other instructions.
2384  * Returns 1 if the step was emulated, 0 if not,
2385  * or -1 if the instruction is one that should not be stepped,
2386  * such as an rfid, or a mtmsrd that would clear MSR_RI.
2387  */
2388 int emulate_step(struct pt_regs *regs, unsigned int instr)
2389 {
2390         struct instruction_op op;
2391         int r, err, size, type;
2392         unsigned long val;
2393         unsigned int cr;
2394         int i, rd, nb;
2395         unsigned long ea;
2396
2397         r = analyse_instr(&op, regs, instr);
2398         if (r < 0)
2399                 return r;
2400         if (r > 0) {
2401                 emulate_update_regs(regs, &op);
2402                 return 1;
2403         }
2404
2405         err = 0;
2406         size = GETSIZE(op.type);
2407         type = op.type & INSTR_TYPE_MASK;
2408
2409         ea = op.ea;
2410         if (OP_IS_LOAD_STORE(type) || type == CACHEOP)
2411                 ea = truncate_if_32bit(regs->msr, op.ea);
2412
2413         switch (type) {
2414         case CACHEOP:
2415                 if (!address_ok(regs, ea, 8))
2416                         return 0;
2417                 switch (op.type & CACHEOP_MASK) {
2418                 case DCBST:
2419                         __cacheop_user_asmx(ea, err, "dcbst");
2420                         break;
2421                 case DCBF:
2422                         __cacheop_user_asmx(ea, err, "dcbf");
2423                         break;
2424                 case DCBTST:
2425                         if (op.reg == 0)
2426                                 prefetchw((void *) ea);
2427                         break;
2428                 case DCBT:
2429                         if (op.reg == 0)
2430                                 prefetch((void *) ea);
2431                         break;
2432                 case ICBI:
2433                         __cacheop_user_asmx(ea, err, "icbi");
2434                         break;
2435                 }
2436                 if (err)
2437                         return 0;
2438                 goto instr_done;
2439
2440         case LARX:
2441                 if (ea & (size - 1))
2442                         break;          /* can't handle misaligned */
2443                 if (!address_ok(regs, ea, size))
2444                         return 0;
2445                 err = 0;
2446                 switch (size) {
2447 #ifdef __powerpc64__
2448                 case 1:
2449                         __get_user_asmx(val, ea, err, "lbarx");
2450                         break;
2451                 case 2:
2452                         __get_user_asmx(val, ea, err, "lharx");
2453                         break;
2454 #endif
2455                 case 4:
2456                         __get_user_asmx(val, ea, err, "lwarx");
2457                         break;
2458 #ifdef __powerpc64__
2459                 case 8:
2460                         __get_user_asmx(val, ea, err, "ldarx");
2461                         break;
2462                 case 16:
2463                         err = do_lqarx(ea, &regs->gpr[op.reg]);
2464                         goto ldst_done;
2465 #endif
2466                 default:
2467                         return 0;
2468                 }
2469                 if (!err)
2470                         regs->gpr[op.reg] = val;
2471                 goto ldst_done;
2472
2473         case STCX:
2474                 if (ea & (size - 1))
2475                         break;          /* can't handle misaligned */
2476                 if (!address_ok(regs, ea, size))
2477                         return 0;
2478                 err = 0;
2479                 switch (size) {
2480 #ifdef __powerpc64__
2481                 case 1:
2482                         __put_user_asmx(op.val, ea, err, "stbcx.", cr);
2483                         break;
2484                 case 2:
2485                         __put_user_asmx(op.val, ea, err, "stbcx.", cr);
2486                         break;
2487 #endif
2488                 case 4:
2489                         __put_user_asmx(op.val, ea, err, "stwcx.", cr);
2490                         break;
2491 #ifdef __powerpc64__
2492                 case 8:
2493                         __put_user_asmx(op.val, ea, err, "stdcx.", cr);
2494                         break;
2495                 case 16:
2496                         err = do_stqcx(ea, regs->gpr[op.reg],
2497                                        regs->gpr[op.reg + 1], &cr);
2498                         break;
2499 #endif
2500                 default:
2501                         return 0;
2502                 }
2503                 if (!err)
2504                         regs->ccr = (regs->ccr & 0x0fffffff) |
2505                                 (cr & 0xe0000000) |
2506                                 ((regs->xer >> 3) & 0x10000000);
2507                 goto ldst_done;
2508
2509         case LOAD:
2510 #ifdef __powerpc64__
2511                 if (size == 16) {
2512                         err = emulate_lq(regs, ea, op.reg);
2513                         goto ldst_done;
2514                 }
2515 #endif
2516                 err = read_mem(&regs->gpr[op.reg], ea, size, regs);
2517                 if (!err) {
2518                         if (op.type & SIGNEXT)
2519                                 do_signext(&regs->gpr[op.reg], size);
2520                         if (op.type & BYTEREV)
2521                                 do_byterev(&regs->gpr[op.reg], size);
2522                 }
2523                 goto ldst_done;
2524
2525 #ifdef CONFIG_PPC_FPU
2526         case LOAD_FP:
2527                 if (!(regs->msr & MSR_FP))
2528                         return 0;
2529                 if (size == 4)
2530                         err = do_fp_load(op.reg, do_lfs, ea, size, regs);
2531                 else
2532                         err = do_fp_load(op.reg, do_lfd, ea, size, regs);
2533                 goto ldst_done;
2534 #endif
2535 #ifdef CONFIG_ALTIVEC
2536         case LOAD_VMX:
2537                 if (!(regs->msr & MSR_VEC))
2538                         return 0;
2539                 err = do_vec_load(op.reg, do_lvx, ea, regs);
2540                 goto ldst_done;
2541 #endif
2542 #ifdef CONFIG_VSX
2543         case LOAD_VSX: {
2544                 u8 mem[16];
2545                 union vsx_reg buf;
2546                 unsigned long msrbit = MSR_VSX;
2547
2548                 /*
2549                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
2550                  * when the target of the instruction is a vector register.
2551                  */
2552                 if (op.reg >= 32 && (op.vsx_flags & VSX_CHECK_VEC))
2553                         msrbit = MSR_VEC;
2554                 if (!(regs->msr & msrbit))
2555                         return 0;
2556                 if (!address_ok(regs, ea, size) ||
2557                     copy_mem_in(mem, ea, size))
2558                         return 0;
2559
2560                 emulate_vsx_load(&op, &buf, mem);
2561                 load_vsrn(op.reg, &buf);
2562                 goto ldst_done;
2563         }
2564 #endif
2565         case LOAD_MULTI:
2566                 if (regs->msr & MSR_LE)
2567                         return 0;
2568                 rd = op.reg;
2569                 for (i = 0; i < size; i += 4) {
2570                         nb = size - i;
2571                         if (nb > 4)
2572                                 nb = 4;
2573                         err = read_mem(&regs->gpr[rd], ea, nb, regs);
2574                         if (err)
2575                                 return 0;
2576                         if (nb < 4)     /* left-justify last bytes */
2577                                 regs->gpr[rd] <<= 32 - 8 * nb;
2578                         ea += 4;
2579                         ++rd;
2580                 }
2581                 goto instr_done;
2582
2583         case STORE:
2584 #ifdef __powerpc64__
2585                 if (size == 16) {
2586                         err = emulate_stq(regs, ea, op.reg);
2587                         goto ldst_done;
2588                 }
2589 #endif
2590                 if ((op.type & UPDATE) && size == sizeof(long) &&
2591                     op.reg == 1 && op.update_reg == 1 &&
2592                     !(regs->msr & MSR_PR) &&
2593                     ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
2594                         err = handle_stack_update(ea, regs);
2595                         goto ldst_done;
2596                 }
2597                 err = write_mem(op.val, ea, size, regs);
2598                 goto ldst_done;
2599
2600 #ifdef CONFIG_PPC_FPU
2601         case STORE_FP:
2602                 if (!(regs->msr & MSR_FP))
2603                         return 0;
2604                 if (size == 4)
2605                         err = do_fp_store(op.reg, do_stfs, ea, size, regs);
2606                 else
2607                         err = do_fp_store(op.reg, do_stfd, ea, size, regs);
2608                 goto ldst_done;
2609 #endif
2610 #ifdef CONFIG_ALTIVEC
2611         case STORE_VMX:
2612                 if (!(regs->msr & MSR_VEC))
2613                         return 0;
2614                 err = do_vec_store(op.reg, do_stvx, ea, regs);
2615                 goto ldst_done;
2616 #endif
2617 #ifdef CONFIG_VSX
2618         case STORE_VSX: {
2619                 u8 mem[16];
2620                 union vsx_reg buf;
2621                 unsigned long msrbit = MSR_VSX;
2622
2623                 /*
2624                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
2625                  * when the target of the instruction is a vector register.
2626                  */
2627                 if (op.reg >= 32 && (op.vsx_flags & VSX_CHECK_VEC))
2628                         msrbit = MSR_VEC;
2629                 if (!(regs->msr & msrbit))
2630                         return 0;
2631                 if (!address_ok(regs, ea, size))
2632                         return 0;
2633
2634                 store_vsrn(op.reg, &buf);
2635                 emulate_vsx_store(&op, &buf, mem);
2636                 if (copy_mem_out(mem, ea, size))
2637                         return 0;
2638                 goto ldst_done;
2639         }
2640 #endif
2641         case STORE_MULTI:
2642                 if (regs->msr & MSR_LE)
2643                         return 0;
2644                 rd = op.reg;
2645                 for (i = 0; i < size; i += 4) {
2646                         val = regs->gpr[rd];
2647                         nb = size - i;
2648                         if (nb > 4)
2649                                 nb = 4;
2650                         else
2651                                 val >>= 32 - 8 * nb;
2652                         err = write_mem(val, ea, nb, regs);
2653                         if (err)
2654                                 return 0;
2655                         ea += 4;
2656                         ++rd;
2657                 }
2658                 goto instr_done;
2659
2660         case MFMSR:
2661                 regs->gpr[op.reg] = regs->msr & MSR_MASK;
2662                 goto instr_done;
2663
2664         case MTMSR:
2665                 val = regs->gpr[op.reg];
2666                 if ((val & MSR_RI) == 0)
2667                         /* can't step mtmsr[d] that would clear MSR_RI */
2668                         return -1;
2669                 /* here op.val is the mask of bits to change */
2670                 regs->msr = (regs->msr & ~op.val) | (val & op.val);
2671                 goto instr_done;
2672
2673 #ifdef CONFIG_PPC64
2674         case SYSCALL:   /* sc */
2675                 /*
2676                  * N.B. this uses knowledge about how the syscall
2677                  * entry code works.  If that is changed, this will
2678                  * need to be changed also.
2679                  */
2680                 if (regs->gpr[0] == 0x1ebe &&
2681                     cpu_has_feature(CPU_FTR_REAL_LE)) {
2682                         regs->msr ^= MSR_LE;
2683                         goto instr_done;
2684                 }
2685                 regs->gpr[9] = regs->gpr[13];
2686                 regs->gpr[10] = MSR_KERNEL;
2687                 regs->gpr[11] = regs->nip + 4;
2688                 regs->gpr[12] = regs->msr & MSR_MASK;
2689                 regs->gpr[13] = (unsigned long) get_paca();
2690                 regs->nip = (unsigned long) &system_call_common;
2691                 regs->msr = MSR_KERNEL;
2692                 return 1;
2693
2694         case RFI:
2695                 return -1;
2696 #endif
2697         }
2698         return 0;
2699
2700  ldst_done:
2701         if (err)
2702                 return 0;
2703         if (op.type & UPDATE)
2704                 regs->gpr[op.update_reg] = op.ea;
2705
2706  instr_done:
2707         regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4);
2708         return 1;
2709 }
2710 NOKPROBE_SYMBOL(emulate_step);