2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/mmu-hash64.h>
33 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
35 #ifdef __LITTLE_ENDIAN__
36 #error Need to fix lppaca and SLB shadow accesses in little endian mode
39 /* Values in HSTATE_NAPPING(r13) */
40 #define NAPPING_CEDE 1
41 #define NAPPING_NOVCPU 2
44 * Call kvmppc_hv_entry in real mode.
45 * Must be called with interrupts hard-disabled.
49 * LR = return address to continue at after eventually re-enabling MMU
51 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
53 std r0, PPC_LR_STKOFF(r1)
56 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
61 mtmsrd r0,1 /* clear RI in MSR */
67 ld r4, HSTATE_KVM_VCPU(r13)
70 /* Back from guest - restore host state and return to caller */
73 /* Restore host DABR and DABRX */
74 ld r5,HSTATE_DABR(r13)
78 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
81 ld r3,PACA_SPRG_VDSO(r13)
82 mtspr SPRN_SPRG_VDSO_WRITE,r3
84 /* Reload the host's PMU registers */
85 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
86 lbz r4, LPPACA_PMCINUSE(r3)
88 beq 23f /* skip if not */
90 ld r3, HSTATE_MMCR(r13)
91 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
94 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
95 lwz r3, HSTATE_PMC(r13)
96 lwz r4, HSTATE_PMC + 4(r13)
97 lwz r5, HSTATE_PMC + 8(r13)
98 lwz r6, HSTATE_PMC + 12(r13)
99 lwz r8, HSTATE_PMC + 16(r13)
100 lwz r9, HSTATE_PMC + 20(r13)
102 lwz r10, HSTATE_PMC + 24(r13)
103 lwz r11, HSTATE_PMC + 28(r13)
104 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
114 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
115 ld r3, HSTATE_MMCR(r13)
116 ld r4, HSTATE_MMCR + 8(r13)
117 ld r5, HSTATE_MMCR + 16(r13)
118 ld r6, HSTATE_MMCR + 24(r13)
119 ld r7, HSTATE_MMCR + 32(r13)
125 ld r8, HSTATE_MMCR + 40(r13)
126 ld r9, HSTATE_MMCR + 48(r13)
129 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
135 * Reload DEC. HDEC interrupts were disabled when
136 * we reloaded the host's LPCR value.
138 ld r3, HSTATE_DECEXP(r13)
144 * For external and machine check interrupts, we need
145 * to call the Linux handler to process the interrupt.
146 * We do that by jumping to absolute address 0x500 for
147 * external interrupts, or the machine_check_fwnmi label
148 * for machine checks (since firmware might have patched
149 * the vector area at 0x200). The [h]rfid at the end of the
150 * handler will return to the book3s_hv_interrupts.S code.
151 * For other interrupts we do the rfid to get back
152 * to the book3s_hv_interrupts.S code here.
154 ld r8, 112+PPC_LR_STKOFF(r1)
156 ld r7, HSTATE_HOST_MSR(r13)
158 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
159 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
162 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
164 /* RFI into the highmem handler, or branch to interrupt handler */
168 mtmsrd r6, 1 /* Clear RI in MSR */
171 beqa 0x500 /* external interrupt (PPC970) */
172 beq cr1, 13f /* machine check */
175 /* On POWER7, we have external interrupts set to use HSRR0/1 */
176 11: mtspr SPRN_HSRR0, r8
180 13: b machine_check_fwnmi
182 kvmppc_primary_no_guest:
183 /* We handle this much like a ceded vcpu */
184 /* set our bit in napping_threads */
185 ld r5, HSTATE_KVM_VCORE(r13)
186 lbz r7, HSTATE_PTID(r13)
189 addi r6, r5, VCORE_NAPPING_THREADS
194 /* order napping_threads update vs testing entry_exit_count */
197 lwz r7, VCORE_ENTRY_EXIT(r5)
199 bge kvm_novcpu_exit /* another thread already exiting */
200 li r3, NAPPING_NOVCPU
201 stb r3, HSTATE_NAPPING(r13)
203 stb r3, HSTATE_HWTHREAD_REQ(r13)
208 ld r1, HSTATE_HOST_R1(r13)
209 ld r5, HSTATE_KVM_VCORE(r13)
211 stb r0, HSTATE_NAPPING(r13)
212 stb r0, HSTATE_HWTHREAD_REQ(r13)
214 /* check the wake reason */
215 bl kvmppc_check_wake_reason
217 /* see if any other thread is already exiting */
218 lwz r0, VCORE_ENTRY_EXIT(r5)
222 /* clear our bit in napping_threads */
223 lbz r7, HSTATE_PTID(r13)
226 addi r6, r5, VCORE_NAPPING_THREADS
232 /* See if the wake reason means we need to exit */
236 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
237 ld r4, HSTATE_KVM_VCPU(r13)
245 * We come in here when wakened from nap mode.
246 * Relocation is off and most register values are lost.
247 * r13 points to the PACA.
249 .globl kvm_start_guest
252 /* Set runlatch bit the minute you wake up from nap */
259 li r0,KVM_HWTHREAD_IN_KVM
260 stb r0,HSTATE_HWTHREAD_STATE(r13)
262 /* NV GPR values from power7_idle() will no longer be valid */
264 stb r0,PACA_NAPSTATELOST(r13)
266 /* were we napping due to cede? */
267 lbz r0,HSTATE_NAPPING(r13)
268 cmpwi r0,NAPPING_CEDE
270 cmpwi r0,NAPPING_NOVCPU
271 beq kvm_novcpu_wakeup
273 ld r1,PACAEMERGSP(r13)
274 subi r1,r1,STACK_FRAME_OVERHEAD
277 * We weren't napping due to cede, so this must be a secondary
278 * thread being woken up to run a guest, or being woken up due
279 * to a stray IPI. (Or due to some machine check or hypervisor
280 * maintenance interrupt while the core is in KVM.)
283 /* Check the wake reason in SRR1 to see why we got here */
284 bl kvmppc_check_wake_reason
288 /* get vcpu pointer, NULL if we have no vcpu to run */
289 ld r4,HSTATE_KVM_VCPU(r13)
291 /* if we have no vcpu to run, go back to sleep */
294 /* Set HSTATE_DSCR(r13) to something sensible */
295 ld r6, PACA_DSCR(r13)
296 std r6, HSTATE_DSCR(r13)
300 /* Back from the guest, go back to nap */
301 /* Clear our vcpu pointer so we don't come back in early */
303 std r0, HSTATE_KVM_VCPU(r13)
305 * Make sure we clear HSTATE_KVM_VCPU(r13) before incrementing
306 * the nap_count, because once the increment to nap_count is
307 * visible we could be given another vcpu.
311 /* increment the nap count and then go to nap mode */
312 ld r4, HSTATE_KVM_VCORE(r13)
313 addi r4, r4, VCORE_NAP_COUNT
320 li r0, KVM_HWTHREAD_IN_NAP
321 stb r0, HSTATE_HWTHREAD_STATE(r13)
323 /* Clear the runlatch bit before napping */
330 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
333 std r0, HSTATE_SCRATCH0(r13)
335 ld r0, HSTATE_SCRATCH0(r13)
341 /******************************************************************************
345 *****************************************************************************/
347 .global kvmppc_hv_entry
352 * R4 = vcpu pointer (or NULL)
356 * all other volatile GPRS = free
359 std r0, PPC_LR_STKOFF(r1)
362 /* Save R1 in the PACA */
363 std r1, HSTATE_HOST_R1(r13)
365 li r6, KVM_GUEST_MODE_HOST_HV
366 stb r6, HSTATE_IN_GUEST(r13)
376 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
378 * POWER7 host -> guest partition switch code.
379 * We don't have to lock against concurrent tlbies,
380 * but we do have to coordinate across hardware threads.
382 /* Increment entry count iff exit count is zero. */
383 ld r5,HSTATE_KVM_VCORE(r13)
384 addi r9,r5,VCORE_ENTRY_EXIT
386 cmpwi r3,0x100 /* any threads starting to exit? */
387 bge secondary_too_late /* if so we're too late to the party */
392 /* Primary thread switches to guest partition. */
393 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
394 lbz r6,HSTATE_PTID(r13)
399 li r0,LPID_RSVD /* switch to reserved LPID */
402 mtspr SPRN_SDR1,r6 /* switch to partition page table */
406 /* See if we need to flush the TLB */
407 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
408 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
409 srdi r6,r6,6 /* doubleword number */
410 sldi r6,r6,3 /* address offset */
412 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
418 23: ldarx r7,0,r6 /* if set, clear the bit */
422 /* Flush the TLB of any entries for this LPID */
423 /* use arch 2.07S as a proxy for POWER8 */
425 li r6,512 /* POWER8 has 512 sets */
427 li r6,128 /* POWER7 has 128 sets */
428 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
430 li r7,0x800 /* IS field = 0b10 */
437 /* Add timebase offset onto timebase */
438 22: ld r8,VCORE_TB_OFFSET(r5)
441 mftb r6 /* current host timebase */
443 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
444 mftb r7 /* check if lower 24 bits overflowed */
449 addis r8,r8,0x100 /* if so, increment upper 40 bits */
452 /* Load guest PCR value to select appropriate compat mode */
453 37: ld r7, VCORE_PCR(r5)
460 /* DPDES is shared between threads */
461 ld r8, VCORE_DPDES(r5)
463 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
466 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
469 /* Secondary threads wait for primary to have done partition switch */
470 20: lbz r0,VCORE_IN_GUEST(r5)
474 /* Set LPCR and RMOR. */
475 10: ld r8,VCORE_LPCR(r5)
481 /* Check if HDEC expires soon */
483 cmpwi r3,512 /* 1 microsecond */
484 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
489 * PPC970 host -> guest partition switch code.
490 * We have to lock against concurrent tlbies,
491 * using native_tlbie_lock to lock against host tlbies
492 * and kvm->arch.tlbie_lock to lock against guest tlbies.
493 * We also have to invalidate the TLB since its
494 * entries aren't tagged with the LPID.
496 30: ld r5,HSTATE_KVM_VCORE(r13)
497 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
499 /* first take native_tlbie_lock */
502 .tc native_tlbie_lock[TC],native_tlbie_lock
504 ld r3,toc_tlbie_lock@toc(2)
505 #ifdef __BIG_ENDIAN__
506 lwz r8,PACA_LOCK_TOKEN(r13)
508 lwz r8,PACAPACAINDEX(r13)
517 ld r5,HSTATE_KVM_VCORE(r13)
518 ld r7,VCORE_LPCR(r5) /* use vcore->lpcr to store HID4 */
520 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
524 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
527 stw r0,0(r3) /* drop native_tlbie_lock */
529 /* invalidate the whole TLB */
538 /* Take the guest's tlbie_lock */
539 addi r3,r9,KVM_TLBIE_LOCK
547 mtspr SPRN_SDR1,r6 /* switch to partition page table */
549 /* Set up HID4 with the guest's LPID etc. */
554 /* drop the guest's tlbie_lock */
558 /* Check if HDEC expires soon */
561 li r12,BOOK3S_INTERRUPT_HV_DECREMENTER
564 /* Enable HDEC interrupts */
567 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
577 /* Do we have a guest vcpu to run? */
579 beq kvmppc_primary_no_guest
582 /* Load up guest SLB entries */
583 lwz r5,VCPU_SLB_MAX(r4)
588 1: ld r8,VCPU_SLB_E(r6)
591 addi r6,r6,VCPU_SLB_SIZE
594 /* Increment yield count if they have a VPA */
598 lwz r5, LPPACA_YIELDCOUNT(r3)
600 stw r5, LPPACA_YIELDCOUNT(r3)
602 stb r6, VCPU_VPA_DIRTY(r4)
606 /* Save purr/spurr */
609 std r5,HSTATE_PURR(r13)
610 std r6,HSTATE_SPURR(r13)
615 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
618 /* Set partition DABR */
619 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
620 lwz r5,VCPU_DABRX(r4)
624 BEGIN_FTR_SECTION_NESTED(89)
626 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_206, CPU_FTR_ARCH_206, 89)
627 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
629 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
632 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
634 /* Turn on TM/FP/VSX/VMX so we can restore them. */
640 oris r5, r5, (MSR_VEC | MSR_VSX)@h
644 * The user may change these outside of a transaction, so they must
645 * always be context switched.
647 ld r5, VCPU_TFHAR(r4)
648 ld r6, VCPU_TFIAR(r4)
649 ld r7, VCPU_TEXASR(r4)
652 mtspr SPRN_TEXASR, r7
655 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
656 beq skip_tm /* TM not active in guest */
658 /* Make sure the failure summary is set, otherwise we'll program check
659 * when we trechkpt. It's possible that this might have been not set
660 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
663 oris r7, r7, (TEXASR_FS)@h
664 mtspr SPRN_TEXASR, r7
667 * We need to load up the checkpointed state for the guest.
668 * We need to do this early as it will blow away any GPRs, VSRs and
673 addi r3, r31, VCPU_FPRS_TM
675 addi r3, r31, VCPU_VRS_TM
678 lwz r7, VCPU_VRSAVE_TM(r4)
679 mtspr SPRN_VRSAVE, r7
681 ld r5, VCPU_LR_TM(r4)
682 lwz r6, VCPU_CR_TM(r4)
683 ld r7, VCPU_CTR_TM(r4)
684 ld r8, VCPU_AMR_TM(r4)
685 ld r9, VCPU_TAR_TM(r4)
693 * Load up PPR and DSCR values but don't put them in the actual SPRs
694 * till the last moment to avoid running with userspace PPR and DSCR for
697 ld r29, VCPU_DSCR_TM(r4)
698 ld r30, VCPU_PPR_TM(r4)
700 std r2, PACATMSCRATCH(r13) /* Save TOC */
702 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
706 /* Load GPRs r0-r28 */
709 ld reg, VCPU_GPRS_TM(reg)(r31)
716 /* Load final GPRs */
717 ld 29, VCPU_GPRS_TM(29)(r31)
718 ld 30, VCPU_GPRS_TM(30)(r31)
719 ld 31, VCPU_GPRS_TM(31)(r31)
721 /* TM checkpointed state is now setup. All GPRs are now volatile. */
724 /* Now let's get back the state we need. */
727 ld r29, HSTATE_DSCR(r13)
729 ld r4, HSTATE_KVM_VCPU(r13)
730 ld r1, HSTATE_HOST_R1(r13)
731 ld r2, PACATMSCRATCH(r13)
733 /* Set the MSR RI since we have our registers back. */
739 /* Load guest PMU registers */
740 /* R4 is live here (vcpu pointer) */
742 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
743 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
747 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
750 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
751 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
752 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
753 lwz r6, VCPU_PMC + 8(r4)
754 lwz r7, VCPU_PMC + 12(r4)
755 lwz r8, VCPU_PMC + 16(r4)
756 lwz r9, VCPU_PMC + 20(r4)
758 lwz r10, VCPU_PMC + 24(r4)
759 lwz r11, VCPU_PMC + 28(r4)
760 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
770 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
772 ld r5, VCPU_MMCR + 8(r4)
773 ld r6, VCPU_MMCR + 16(r4)
781 ld r5, VCPU_MMCR + 24(r4)
783 lwz r7, VCPU_PMC + 24(r4)
784 lwz r8, VCPU_PMC + 28(r4)
785 ld r9, VCPU_MMCR + 32(r4)
791 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
795 /* Load up FP, VMX and VSX registers */
798 ld r14, VCPU_GPR(R14)(r4)
799 ld r15, VCPU_GPR(R15)(r4)
800 ld r16, VCPU_GPR(R16)(r4)
801 ld r17, VCPU_GPR(R17)(r4)
802 ld r18, VCPU_GPR(R18)(r4)
803 ld r19, VCPU_GPR(R19)(r4)
804 ld r20, VCPU_GPR(R20)(r4)
805 ld r21, VCPU_GPR(R21)(r4)
806 ld r22, VCPU_GPR(R22)(r4)
807 ld r23, VCPU_GPR(R23)(r4)
808 ld r24, VCPU_GPR(R24)(r4)
809 ld r25, VCPU_GPR(R25)(r4)
810 ld r26, VCPU_GPR(R26)(r4)
811 ld r27, VCPU_GPR(R27)(r4)
812 ld r28, VCPU_GPR(R28)(r4)
813 ld r29, VCPU_GPR(R29)(r4)
814 ld r30, VCPU_GPR(R30)(r4)
815 ld r31, VCPU_GPR(R31)(r4)
818 /* Switch DSCR to guest value */
821 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
824 /* Skip next section on POWER7 or PPC970 */
826 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
827 /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
830 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
833 /* Load up POWER8-specific registers */
835 lwz r6, VCPU_PSPB(r4)
841 ld r6, VCPU_DAWRX(r4)
842 ld r7, VCPU_CIABR(r4)
852 ld r8, VCPU_EBBHR(r4)
854 ld r5, VCPU_EBBRR(r4)
855 ld r6, VCPU_BESCR(r4)
856 ld r7, VCPU_CSIGR(r4)
862 ld r5, VCPU_TCSCR(r4)
864 lwz r7, VCPU_GUEST_PID(r4)
873 * Set the decrementer to the guest decrementer.
875 ld r8,VCPU_DEC_EXPIRES(r4)
876 /* r8 is a host timebase value here, convert to guest TB */
877 ld r5,HSTATE_KVM_VCORE(r13)
878 ld r6,VCORE_TB_OFFSET(r5)
885 ld r5, VCPU_SPRG0(r4)
886 ld r6, VCPU_SPRG1(r4)
887 ld r7, VCPU_SPRG2(r4)
888 ld r8, VCPU_SPRG3(r4)
894 /* Load up DAR and DSISR */
896 lwz r6, VCPU_DSISR(r4)
901 /* Restore AMR and UAMOR, set AMOR to all 1s */
908 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
910 /* Restore state of CTRL run bit; assume 1 on entry */
924 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
932 deliver_guest_interrupt:
933 /* r11 = vcpu->arch.msr & ~MSR_HV */
934 rldicl r11, r11, 63 - MSR_HV_LG, 1
935 rotldi r11, r11, 1 + MSR_HV_LG
938 /* Check if we can deliver an external or decrementer interrupt now */
939 ld r0, VCPU_PENDING_EXC(r4)
940 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
942 andi. r8, r11, MSR_EE
945 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
946 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
949 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
951 li r0, BOOK3S_INTERRUPT_EXTERNAL
955 li r0, BOOK3S_INTERRUPT_DECREMENTER
958 12: mtspr SPRN_SRR0, r10
962 bl kvmppc_msr_interrupt
968 * R10: value for HSRR0
969 * R11: value for HSRR1
974 stb r0,VCPU_CEDED(r4) /* cancel cede */
978 /* Activate guest mode, so faults get handled by KVM */
979 li r9, KVM_GUEST_MODE_GUEST_HV
980 stb r9, HSTATE_IN_GUEST(r13)
987 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
990 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
997 ld r1, VCPU_GPR(R1)(r4)
998 ld r2, VCPU_GPR(R2)(r4)
999 ld r3, VCPU_GPR(R3)(r4)
1000 ld r5, VCPU_GPR(R5)(r4)
1001 ld r6, VCPU_GPR(R6)(r4)
1002 ld r7, VCPU_GPR(R7)(r4)
1003 ld r8, VCPU_GPR(R8)(r4)
1004 ld r9, VCPU_GPR(R9)(r4)
1005 ld r10, VCPU_GPR(R10)(r4)
1006 ld r11, VCPU_GPR(R11)(r4)
1007 ld r12, VCPU_GPR(R12)(r4)
1008 ld r13, VCPU_GPR(R13)(r4)
1012 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1013 ld r0, VCPU_GPR(R0)(r4)
1014 ld r4, VCPU_GPR(R4)(r4)
1019 /******************************************************************************
1023 *****************************************************************************/
1026 * We come here from the first-level interrupt handlers.
1028 .globl kvmppc_interrupt_hv
1029 kvmppc_interrupt_hv:
1031 * Register contents:
1032 * R12 = interrupt vector
1034 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
1035 * guest R13 saved in SPRN_SCRATCH0
1037 std r9, HSTATE_SCRATCH2(r13)
1039 lbz r9, HSTATE_IN_GUEST(r13)
1040 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1041 beq kvmppc_bad_host_intr
1042 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1043 cmpwi r9, KVM_GUEST_MODE_GUEST
1044 ld r9, HSTATE_SCRATCH2(r13)
1045 beq kvmppc_interrupt_pr
1047 /* We're now back in the host but in guest MMU context */
1048 li r9, KVM_GUEST_MODE_HOST_HV
1049 stb r9, HSTATE_IN_GUEST(r13)
1051 ld r9, HSTATE_KVM_VCPU(r13)
1053 /* Save registers */
1055 std r0, VCPU_GPR(R0)(r9)
1056 std r1, VCPU_GPR(R1)(r9)
1057 std r2, VCPU_GPR(R2)(r9)
1058 std r3, VCPU_GPR(R3)(r9)
1059 std r4, VCPU_GPR(R4)(r9)
1060 std r5, VCPU_GPR(R5)(r9)
1061 std r6, VCPU_GPR(R6)(r9)
1062 std r7, VCPU_GPR(R7)(r9)
1063 std r8, VCPU_GPR(R8)(r9)
1064 ld r0, HSTATE_SCRATCH2(r13)
1065 std r0, VCPU_GPR(R9)(r9)
1066 std r10, VCPU_GPR(R10)(r9)
1067 std r11, VCPU_GPR(R11)(r9)
1068 ld r3, HSTATE_SCRATCH0(r13)
1069 lwz r4, HSTATE_SCRATCH1(r13)
1070 std r3, VCPU_GPR(R12)(r9)
1073 ld r3, HSTATE_CFAR(r13)
1074 std r3, VCPU_CFAR(r9)
1075 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1077 ld r4, HSTATE_PPR(r13)
1078 std r4, VCPU_PPR(r9)
1079 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1081 /* Restore R1/R2 so we can handle faults */
1082 ld r1, HSTATE_HOST_R1(r13)
1085 mfspr r10, SPRN_SRR0
1086 mfspr r11, SPRN_SRR1
1087 std r10, VCPU_SRR0(r9)
1088 std r11, VCPU_SRR1(r9)
1089 andi. r0, r12, 2 /* need to read HSRR0/1? */
1091 mfspr r10, SPRN_HSRR0
1092 mfspr r11, SPRN_HSRR1
1094 1: std r10, VCPU_PC(r9)
1095 std r11, VCPU_MSR(r9)
1099 std r3, VCPU_GPR(R13)(r9)
1102 stw r12,VCPU_TRAP(r9)
1104 /* Save HEIR (HV emulation assist reg) in last_inst
1105 if this is an HEI (HV emulation interrupt, e40) */
1106 li r3,KVM_INST_FETCH_FAILED
1108 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1111 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1112 11: stw r3,VCPU_LAST_INST(r9)
1114 /* these are volatile across C function calls */
1117 std r3, VCPU_CTR(r9)
1118 stw r4, VCPU_XER(r9)
1121 /* If this is a page table miss then see if it's theirs or ours */
1122 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1124 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1126 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1128 /* See if this is a leftover HDEC interrupt */
1129 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1135 /* See if this is an hcall we can handle in real mode */
1136 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1137 beq hcall_try_real_mode
1139 /* Only handle external interrupts here on arch 206 and later */
1141 b ext_interrupt_to_host
1142 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
1144 /* External interrupt ? */
1145 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1146 bne+ ext_interrupt_to_host
1148 /* External interrupt, first check for host_ipi. If this is
1149 * set, we know the host wants us out so let's do it now
1153 bgt ext_interrupt_to_host
1155 /* Check if any CPU is heading out to the host, if so head out too */
1156 ld r5, HSTATE_KVM_VCORE(r13)
1157 lwz r0, VCORE_ENTRY_EXIT(r5)
1159 bge ext_interrupt_to_host
1161 /* Return to guest after delivering any pending interrupt */
1163 b deliver_guest_interrupt
1165 ext_interrupt_to_host:
1167 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1168 /* Save more register state */
1171 std r6, VCPU_DAR(r9)
1172 stw r7, VCPU_DSISR(r9)
1174 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1175 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1177 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1178 std r6, VCPU_FAULT_DAR(r9)
1179 stw r7, VCPU_FAULT_DSISR(r9)
1181 /* See if it is a machine check */
1182 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1183 beq machine_check_realmode
1186 /* Save guest CTRL register, set runlatch to 1 */
1187 6: mfspr r6,SPRN_CTRLF
1188 stw r6,VCPU_CTRL(r9)
1194 /* Read the guest SLB and save it away */
1195 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1201 andis. r0,r8,SLB_ESID_V@h
1203 add r8,r8,r6 /* put index in */
1205 std r8,VCPU_SLB_E(r7)
1206 std r3,VCPU_SLB_V(r7)
1207 addi r7,r7,VCPU_SLB_SIZE
1211 stw r5,VCPU_SLB_MAX(r9)
1214 * Save the guest PURR/SPURR
1220 ld r8,VCPU_SPURR(r9)
1221 std r5,VCPU_PURR(r9)
1222 std r6,VCPU_SPURR(r9)
1227 * Restore host PURR/SPURR and add guest times
1228 * so that the time in the guest gets accounted.
1230 ld r3,HSTATE_PURR(r13)
1231 ld r4,HSTATE_SPURR(r13)
1236 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
1243 /* r5 is a guest timebase value here, convert to host TB */
1244 ld r3,HSTATE_KVM_VCORE(r13)
1245 ld r4,VCORE_TB_OFFSET(r3)
1247 std r5,VCPU_DEC_EXPIRES(r9)
1251 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1252 /* Save POWER8-specific registers */
1256 std r5, VCPU_IAMR(r9)
1257 stw r6, VCPU_PSPB(r9)
1258 std r7, VCPU_FSCR(r9)
1263 std r6, VCPU_VTB(r9)
1264 std r7, VCPU_TAR(r9)
1265 mfspr r8, SPRN_EBBHR
1266 std r8, VCPU_EBBHR(r9)
1267 mfspr r5, SPRN_EBBRR
1268 mfspr r6, SPRN_BESCR
1269 mfspr r7, SPRN_CSIGR
1271 std r5, VCPU_EBBRR(r9)
1272 std r6, VCPU_BESCR(r9)
1273 std r7, VCPU_CSIGR(r9)
1274 std r8, VCPU_TACR(r9)
1275 mfspr r5, SPRN_TCSCR
1279 std r5, VCPU_TCSCR(r9)
1280 std r6, VCPU_ACOP(r9)
1281 stw r7, VCPU_GUEST_PID(r9)
1282 std r8, VCPU_WORT(r9)
1285 /* Save and reset AMR and UAMOR before turning on the MMU */
1290 std r6,VCPU_UAMOR(r9)
1293 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1295 /* Switch DSCR back to host value */
1298 ld r7, HSTATE_DSCR(r13)
1299 std r8, VCPU_DSCR(r9)
1301 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1303 /* Save non-volatile GPRs */
1304 std r14, VCPU_GPR(R14)(r9)
1305 std r15, VCPU_GPR(R15)(r9)
1306 std r16, VCPU_GPR(R16)(r9)
1307 std r17, VCPU_GPR(R17)(r9)
1308 std r18, VCPU_GPR(R18)(r9)
1309 std r19, VCPU_GPR(R19)(r9)
1310 std r20, VCPU_GPR(R20)(r9)
1311 std r21, VCPU_GPR(R21)(r9)
1312 std r22, VCPU_GPR(R22)(r9)
1313 std r23, VCPU_GPR(R23)(r9)
1314 std r24, VCPU_GPR(R24)(r9)
1315 std r25, VCPU_GPR(R25)(r9)
1316 std r26, VCPU_GPR(R26)(r9)
1317 std r27, VCPU_GPR(R27)(r9)
1318 std r28, VCPU_GPR(R28)(r9)
1319 std r29, VCPU_GPR(R29)(r9)
1320 std r30, VCPU_GPR(R30)(r9)
1321 std r31, VCPU_GPR(R31)(r9)
1324 mfspr r3, SPRN_SPRG0
1325 mfspr r4, SPRN_SPRG1
1326 mfspr r5, SPRN_SPRG2
1327 mfspr r6, SPRN_SPRG3
1328 std r3, VCPU_SPRG0(r9)
1329 std r4, VCPU_SPRG1(r9)
1330 std r5, VCPU_SPRG2(r9)
1331 std r6, VCPU_SPRG3(r9)
1337 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1340 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
1344 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
1348 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
1349 beq 1f /* TM not active in guest. */
1351 li r3, TM_CAUSE_KVM_RESCHED
1353 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
1357 /* All GPRs are volatile at this point. */
1360 /* Temporarily store r13 and r9 so we have some regs to play with */
1363 std r9, PACATMSCRATCH(r13)
1364 ld r9, HSTATE_KVM_VCPU(r13)
1366 /* Get a few more GPRs free. */
1367 std r29, VCPU_GPRS_TM(29)(r9)
1368 std r30, VCPU_GPRS_TM(30)(r9)
1369 std r31, VCPU_GPRS_TM(31)(r9)
1371 /* Save away PPR and DSCR soon so don't run with user values. */
1374 mfspr r30, SPRN_DSCR
1375 ld r29, HSTATE_DSCR(r13)
1376 mtspr SPRN_DSCR, r29
1378 /* Save all but r9, r13 & r29-r31 */
1381 .if (reg != 9) && (reg != 13)
1382 std reg, VCPU_GPRS_TM(reg)(r9)
1386 /* ... now save r13 */
1388 std r4, VCPU_GPRS_TM(13)(r9)
1389 /* ... and save r9 */
1390 ld r4, PACATMSCRATCH(r13)
1391 std r4, VCPU_GPRS_TM(9)(r9)
1393 /* Reload stack pointer and TOC. */
1394 ld r1, HSTATE_HOST_R1(r13)
1397 /* Set MSR RI now we have r1 and r13 back. */
1401 /* Save away checkpinted SPRs. */
1402 std r31, VCPU_PPR_TM(r9)
1403 std r30, VCPU_DSCR_TM(r9)
1409 std r5, VCPU_LR_TM(r9)
1410 stw r6, VCPU_CR_TM(r9)
1411 std r7, VCPU_CTR_TM(r9)
1412 std r8, VCPU_AMR_TM(r9)
1413 std r10, VCPU_TAR_TM(r9)
1415 /* Restore r12 as trap number. */
1416 lwz r12, VCPU_TRAP(r9)
1419 addi r3, r9, VCPU_FPRS_TM
1421 addi r3, r9, VCPU_VRS_TM
1423 mfspr r6, SPRN_VRSAVE
1424 stw r6, VCPU_VRSAVE_TM(r9)
1427 * We need to save these SPRs after the treclaim so that the software
1428 * error code is recorded correctly in the TEXASR. Also the user may
1429 * change these outside of a transaction, so they must always be
1432 mfspr r5, SPRN_TFHAR
1433 mfspr r6, SPRN_TFIAR
1434 mfspr r7, SPRN_TEXASR
1435 std r5, VCPU_TFHAR(r9)
1436 std r6, VCPU_TFIAR(r9)
1437 std r7, VCPU_TEXASR(r9)
1441 /* Increment yield count if they have a VPA */
1442 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1445 lwz r3, LPPACA_YIELDCOUNT(r8)
1447 stw r3, LPPACA_YIELDCOUNT(r8)
1449 stb r3, VCPU_VPA_DIRTY(r9)
1451 /* Save PMU registers if requested */
1452 /* r8 and cr0.eq are live here */
1455 * POWER8 seems to have a hardware bug where setting
1456 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
1457 * when some counters are already negative doesn't seem
1458 * to cause a performance monitor alert (and hence interrupt).
1459 * The effect of this is that when saving the PMU state,
1460 * if there is no PMU alert pending when we read MMCR0
1461 * before freezing the counters, but one becomes pending
1462 * before we read the counters, we lose it.
1463 * To work around this, we need a way to freeze the counters
1464 * before reading MMCR0. Normally, freezing the counters
1465 * is done by writing MMCR0 (to set MMCR0[FC]) which
1466 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
1467 * we can also freeze the counters using MMCR2, by writing
1468 * 1s to all the counter freeze condition bits (there are
1469 * 9 bits each for 6 counters).
1471 li r3, -1 /* set all freeze bits */
1473 mfspr r10, SPRN_MMCR2
1474 mtspr SPRN_MMCR2, r3
1476 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1478 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1479 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1480 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1481 mfspr r6, SPRN_MMCRA
1483 /* On P7, clear MMCRA in order to disable SDAR updates */
1485 mtspr SPRN_MMCRA, r7
1486 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
1488 beq 21f /* if no VPA, save PMU stuff anyway */
1489 lbz r7, LPPACA_PMCINUSE(r8)
1490 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1492 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1494 21: mfspr r5, SPRN_MMCR1
1497 std r4, VCPU_MMCR(r9)
1498 std r5, VCPU_MMCR + 8(r9)
1499 std r6, VCPU_MMCR + 16(r9)
1501 std r10, VCPU_MMCR + 24(r9)
1502 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1503 std r7, VCPU_SIAR(r9)
1504 std r8, VCPU_SDAR(r9)
1512 mfspr r10, SPRN_PMC7
1513 mfspr r11, SPRN_PMC8
1514 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1515 stw r3, VCPU_PMC(r9)
1516 stw r4, VCPU_PMC + 4(r9)
1517 stw r5, VCPU_PMC + 8(r9)
1518 stw r6, VCPU_PMC + 12(r9)
1519 stw r7, VCPU_PMC + 16(r9)
1520 stw r8, VCPU_PMC + 20(r9)
1522 stw r10, VCPU_PMC + 24(r9)
1523 stw r11, VCPU_PMC + 28(r9)
1524 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1527 mfspr r6, SPRN_SPMC1
1528 mfspr r7, SPRN_SPMC2
1529 mfspr r8, SPRN_MMCRS
1530 std r5, VCPU_SIER(r9)
1531 stw r6, VCPU_PMC + 24(r9)
1532 stw r7, VCPU_PMC + 28(r9)
1533 std r8, VCPU_MMCR + 32(r9)
1535 mtspr SPRN_MMCRS, r4
1536 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1544 hdec_soon: /* r12 = trap, r13 = paca */
1547 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
1549 * POWER7 guest -> host partition switch code.
1550 * We don't have to lock against tlbies but we do
1551 * have to coordinate the hardware threads.
1553 /* Increment the threads-exiting-guest count in the 0xff00
1554 bits of vcore->entry_exit_count */
1555 ld r5,HSTATE_KVM_VCORE(r13)
1556 addi r6,r5,VCORE_ENTRY_EXIT
1561 isync /* order stwcx. vs. reading napping_threads */
1564 * At this point we have an interrupt that we have to pass
1565 * up to the kernel or qemu; we can't handle it in real mode.
1566 * Thus we have to do a partition switch, so we have to
1567 * collect the other threads, if we are the first thread
1568 * to take an interrupt. To do this, we set the HDEC to 0,
1569 * which causes an HDEC interrupt in all threads within 2ns
1570 * because the HDEC register is shared between all 4 threads.
1571 * However, we don't need to bother if this is an HDEC
1572 * interrupt, since the other threads will already be on their
1573 * way here in that case.
1575 cmpwi r3,0x100 /* Are we the first here? */
1577 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1583 * Send an IPI to any napping threads, since an HDEC interrupt
1584 * doesn't wake CPUs up from nap.
1586 lwz r3,VCORE_NAPPING_THREADS(r5)
1587 lbz r4,HSTATE_PTID(r13)
1590 andc. r3,r3,r0 /* no sense IPI'ing ourselves */
1592 /* Order entry/exit update vs. IPIs */
1594 mulli r4,r4,PACA_SIZE /* get paca for thread 0 */
1598 ld r8,HSTATE_XICS_PHYS(r6) /* get thread's XICS reg addr */
1601 stbcix r0,r7,r8 /* trigger the IPI */
1603 addi r6,r6,PACA_SIZE
1607 /* Secondary threads wait for primary to do partition switch */
1608 43: ld r5,HSTATE_KVM_VCORE(r13)
1609 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1610 lbz r3,HSTATE_PTID(r13)
1614 13: lbz r3,VCORE_IN_GUEST(r5)
1620 /* Primary thread waits for all the secondaries to exit guest */
1621 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1628 /* Primary thread switches back to host partition */
1629 ld r6,KVM_HOST_SDR1(r4)
1630 lwz r7,KVM_HOST_LPID(r4)
1631 li r8,LPID_RSVD /* switch to reserved LPID */
1634 mtspr SPRN_SDR1,r6 /* switch to partition page table */
1639 /* DPDES is shared between threads */
1640 mfspr r7, SPRN_DPDES
1641 std r7, VCORE_DPDES(r5)
1642 /* clear DPDES so we don't get guest doorbells in the host */
1644 mtspr SPRN_DPDES, r8
1645 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1647 /* Subtract timebase offset from timebase */
1648 ld r8,VCORE_TB_OFFSET(r5)
1651 mftb r6 /* current guest timebase */
1653 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1654 mftb r7 /* check if lower 24 bits overflowed */
1659 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1663 17: ld r0, VCORE_PCR(r5)
1669 /* Signal secondary CPUs to continue */
1670 stb r0,VCORE_IN_GUEST(r5)
1671 lis r8,0x7fff /* MAX_INT@h */
1674 16: ld r8,KVM_HOST_LPCR(r4)
1680 * PPC970 guest -> host partition switch code.
1681 * We have to lock against concurrent tlbies, and
1682 * we have to flush the whole TLB.
1684 32: ld r5,HSTATE_KVM_VCORE(r13)
1685 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1687 /* Take the guest's tlbie_lock */
1688 #ifdef __BIG_ENDIAN__
1689 lwz r8,PACA_LOCK_TOKEN(r13)
1691 lwz r8,PACAPACAINDEX(r13)
1693 addi r3,r4,KVM_TLBIE_LOCK
1701 ld r7,KVM_HOST_LPCR(r4) /* use kvm->arch.host_lpcr for HID4 */
1703 rotldi r0,r0,HID4_LPID5_SH /* all lpid bits in HID4 = 1 */
1707 mtspr SPRN_HID4,r0 /* switch to reserved LPID */
1710 stw r0,0(r3) /* drop guest tlbie_lock */
1712 /* invalidate the whole TLB */
1721 /* take native_tlbie_lock */
1722 ld r3,toc_tlbie_lock@toc(2)
1730 ld r6,KVM_HOST_SDR1(r4)
1731 mtspr SPRN_SDR1,r6 /* switch to host page table */
1733 /* Set up host HID4 value */
1738 stw r0,0(r3) /* drop native_tlbie_lock */
1740 lis r8,0x7fff /* MAX_INT@h */
1743 /* Disable HDEC interrupts */
1746 rldimi r0,r3, HID0_HDICE_SH, 64-HID0_HDICE_SH-1
1756 /* load host SLB entries */
1757 33: ld r8,PACA_SLBSHADOWPTR(r13)
1759 .rept SLB_NUM_BOLTED
1760 ld r5,SLBSHADOW_SAVEAREA(r8)
1761 ld r6,SLBSHADOW_SAVEAREA+8(r8)
1762 andis. r7,r5,SLB_ESID_V@h
1768 /* Unset guest mode */
1769 li r0, KVM_GUEST_MODE_NONE
1770 stb r0, HSTATE_IN_GUEST(r13)
1772 ld r0, 112+PPC_LR_STKOFF(r1)
1778 * Check whether an HDSI is an HPTE not found fault or something else.
1779 * If it is an HPTE not found fault that is due to the guest accessing
1780 * a page that they have mapped but which we have paged out, then
1781 * we continue on with the guest exit path. In all other cases,
1782 * reflect the HDSI to the guest as a DSI.
1786 mfspr r6, SPRN_HDSISR
1787 /* HPTE not found fault or protection fault? */
1788 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1789 beq 1f /* if not, send it to the guest */
1790 andi. r0, r11, MSR_DR /* data relocation enabled? */
1793 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1794 bne 1f /* if no SLB entry found */
1795 4: std r4, VCPU_FAULT_DAR(r9)
1796 stw r6, VCPU_FAULT_DSISR(r9)
1798 /* Search the hash table. */
1799 mr r3, r9 /* vcpu pointer */
1800 li r7, 1 /* data fault */
1801 bl kvmppc_hpte_hv_fault
1802 ld r9, HSTATE_KVM_VCPU(r13)
1804 ld r11, VCPU_MSR(r9)
1805 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1806 cmpdi r3, 0 /* retry the instruction */
1808 cmpdi r3, -1 /* handle in kernel mode */
1810 cmpdi r3, -2 /* MMIO emulation; need instr word */
1813 /* Synthesize a DSI for the guest */
1814 ld r4, VCPU_FAULT_DAR(r9)
1816 1: mtspr SPRN_DAR, r4
1817 mtspr SPRN_DSISR, r6
1818 mtspr SPRN_SRR0, r10
1819 mtspr SPRN_SRR1, r11
1820 li r10, BOOK3S_INTERRUPT_DATA_STORAGE
1821 bl kvmppc_msr_interrupt
1822 fast_interrupt_c_return:
1823 6: ld r7, VCPU_CTR(r9)
1824 lwz r8, VCPU_XER(r9)
1830 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1831 ld r5, KVM_VRMA_SLB_V(r5)
1834 /* If this is for emulated MMIO, load the instruction word */
1835 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1837 /* Set guest mode to 'jump over instruction' so if lwz faults
1838 * we'll just continue at the next IP. */
1839 li r0, KVM_GUEST_MODE_SKIP
1840 stb r0, HSTATE_IN_GUEST(r13)
1842 /* Do the access with MSR:DR enabled */
1844 ori r4, r3, MSR_DR /* Enable paging for data */
1849 /* Store the result */
1850 stw r8, VCPU_LAST_INST(r9)
1852 /* Unset guest mode. */
1853 li r0, KVM_GUEST_MODE_HOST_HV
1854 stb r0, HSTATE_IN_GUEST(r13)
1858 * Similarly for an HISI, reflect it to the guest as an ISI unless
1859 * it is an HPTE not found fault for a page that we have paged out.
1862 andis. r0, r11, SRR1_ISI_NOPT@h
1864 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1867 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1868 bne 1f /* if no SLB entry found */
1870 /* Search the hash table. */
1871 mr r3, r9 /* vcpu pointer */
1874 li r7, 0 /* instruction fault */
1875 bl kvmppc_hpte_hv_fault
1876 ld r9, HSTATE_KVM_VCPU(r13)
1878 ld r11, VCPU_MSR(r9)
1879 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1880 cmpdi r3, 0 /* retry the instruction */
1881 beq fast_interrupt_c_return
1882 cmpdi r3, -1 /* handle in kernel mode */
1885 /* Synthesize an ISI for the guest */
1887 1: mtspr SPRN_SRR0, r10
1888 mtspr SPRN_SRR1, r11
1889 li r10, BOOK3S_INTERRUPT_INST_STORAGE
1890 bl kvmppc_msr_interrupt
1891 b fast_interrupt_c_return
1893 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1894 ld r5, KVM_VRMA_SLB_V(r6)
1898 * Try to handle an hcall in real mode.
1899 * Returns to the guest if we handle it, or continues on up to
1900 * the kernel if we can't (i.e. if we don't have a handler for
1901 * it, or if the handler returns H_TOO_HARD).
1903 .globl hcall_try_real_mode
1904 hcall_try_real_mode:
1905 ld r3,VCPU_GPR(R3)(r9)
1907 /* sc 1 from userspace - reflect to guest syscall */
1908 bne sc_1_fast_return
1910 cmpldi r3,hcall_real_table_end - hcall_real_table
1912 LOAD_REG_ADDR(r4, hcall_real_table)
1918 mr r3,r9 /* get vcpu pointer */
1919 ld r4,VCPU_GPR(R4)(r9)
1922 beq hcall_real_fallback
1923 ld r4,HSTATE_KVM_VCPU(r13)
1924 std r3,VCPU_GPR(R3)(r4)
1932 li r10, BOOK3S_INTERRUPT_SYSCALL
1933 bl kvmppc_msr_interrupt
1937 /* We've attempted a real mode hcall, but it's punted it back
1938 * to userspace. We need to restore some clobbered volatiles
1939 * before resuming the pass-it-to-qemu path */
1940 hcall_real_fallback:
1941 li r12,BOOK3S_INTERRUPT_SYSCALL
1942 ld r9, HSTATE_KVM_VCPU(r13)
1946 .globl hcall_real_table
1948 .long 0 /* 0 - unused */
1949 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
1950 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
1951 .long DOTSYM(kvmppc_h_read) - hcall_real_table
1952 .long 0 /* 0x10 - H_CLEAR_MOD */
1953 .long 0 /* 0x14 - H_CLEAR_REF */
1954 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
1955 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
1956 .long DOTSYM(kvmppc_h_put_tce) - hcall_real_table
1957 .long 0 /* 0x24 - H_SET_SPRG0 */
1958 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
1973 #ifdef CONFIG_KVM_XICS
1974 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
1975 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
1976 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
1977 .long 0 /* 0x70 - H_IPOLL */
1978 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
1980 .long 0 /* 0x64 - H_EOI */
1981 .long 0 /* 0x68 - H_CPPR */
1982 .long 0 /* 0x6c - H_IPI */
1983 .long 0 /* 0x70 - H_IPOLL */
1984 .long 0 /* 0x74 - H_XIRR */
2012 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
2029 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
2033 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
2034 hcall_real_table_end:
2040 _GLOBAL(kvmppc_h_set_xdabr)
2041 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2043 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2046 6: li r3, H_PARAMETER
2049 _GLOBAL(kvmppc_h_set_dabr)
2050 li r5, DABRX_USER | DABRX_KERNEL
2054 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2055 std r4,VCPU_DABR(r3)
2056 stw r5, VCPU_DABRX(r3)
2057 mtspr SPRN_DABRX, r5
2058 /* Work around P7 bug where DABR can get corrupted on mtspr */
2059 1: mtspr SPRN_DABR,r4
2067 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2068 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2069 rlwimi r5, r4, 1, DAWRX_WT
2071 std r4, VCPU_DAWR(r3)
2072 std r5, VCPU_DAWRX(r3)
2074 mtspr SPRN_DAWRX, r5
2078 _GLOBAL(kvmppc_h_cede)
2080 std r11,VCPU_MSR(r3)
2082 stb r0,VCPU_CEDED(r3)
2083 sync /* order setting ceded vs. testing prodded */
2084 lbz r5,VCPU_PRODDED(r3)
2086 bne kvm_cede_prodded
2087 li r0,0 /* set trap to 0 to say hcall is handled */
2088 stw r0,VCPU_TRAP(r3)
2090 std r0,VCPU_GPR(R3)(r3)
2092 b kvm_cede_exit /* just send it up to host on 970 */
2093 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
2096 * Set our bit in the bitmask of napping threads unless all the
2097 * other threads are already napping, in which case we send this
2100 ld r5,HSTATE_KVM_VCORE(r13)
2101 lbz r6,HSTATE_PTID(r13)
2102 lwz r8,VCORE_ENTRY_EXIT(r5)
2106 addi r6,r5,VCORE_NAPPING_THREADS
2114 /* order napping_threads update vs testing entry_exit_count */
2117 stb r0,HSTATE_NAPPING(r13)
2118 lwz r7,VCORE_ENTRY_EXIT(r5)
2120 bge 33f /* another thread already exiting */
2123 * Although not specifically required by the architecture, POWER7
2124 * preserves the following registers in nap mode, even if an SMT mode
2125 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2126 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2128 /* Save non-volatile GPRs */
2129 std r14, VCPU_GPR(R14)(r3)
2130 std r15, VCPU_GPR(R15)(r3)
2131 std r16, VCPU_GPR(R16)(r3)
2132 std r17, VCPU_GPR(R17)(r3)
2133 std r18, VCPU_GPR(R18)(r3)
2134 std r19, VCPU_GPR(R19)(r3)
2135 std r20, VCPU_GPR(R20)(r3)
2136 std r21, VCPU_GPR(R21)(r3)
2137 std r22, VCPU_GPR(R22)(r3)
2138 std r23, VCPU_GPR(R23)(r3)
2139 std r24, VCPU_GPR(R24)(r3)
2140 std r25, VCPU_GPR(R25)(r3)
2141 std r26, VCPU_GPR(R26)(r3)
2142 std r27, VCPU_GPR(R27)(r3)
2143 std r28, VCPU_GPR(R28)(r3)
2144 std r29, VCPU_GPR(R29)(r3)
2145 std r30, VCPU_GPR(R30)(r3)
2146 std r31, VCPU_GPR(R31)(r3)
2152 * Take a nap until a decrementer or external or doobell interrupt
2153 * occurs, with PECE1, PECE0 and PECEDP set in LPCR. Also clear the
2154 * runlatch bit before napping.
2156 mfspr r2, SPRN_CTRLF
2158 mtspr SPRN_CTRLT, r2
2161 stb r0,HSTATE_HWTHREAD_REQ(r13)
2163 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2165 oris r5,r5,LPCR_PECEDP@h
2166 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2170 std r0, HSTATE_SCRATCH0(r13)
2172 ld r0, HSTATE_SCRATCH0(r13)
2184 /* get vcpu pointer */
2185 ld r4, HSTATE_KVM_VCPU(r13)
2187 /* Woken by external or decrementer interrupt */
2188 ld r1, HSTATE_HOST_R1(r13)
2190 /* load up FP state */
2194 ld r14, VCPU_GPR(R14)(r4)
2195 ld r15, VCPU_GPR(R15)(r4)
2196 ld r16, VCPU_GPR(R16)(r4)
2197 ld r17, VCPU_GPR(R17)(r4)
2198 ld r18, VCPU_GPR(R18)(r4)
2199 ld r19, VCPU_GPR(R19)(r4)
2200 ld r20, VCPU_GPR(R20)(r4)
2201 ld r21, VCPU_GPR(R21)(r4)
2202 ld r22, VCPU_GPR(R22)(r4)
2203 ld r23, VCPU_GPR(R23)(r4)
2204 ld r24, VCPU_GPR(R24)(r4)
2205 ld r25, VCPU_GPR(R25)(r4)
2206 ld r26, VCPU_GPR(R26)(r4)
2207 ld r27, VCPU_GPR(R27)(r4)
2208 ld r28, VCPU_GPR(R28)(r4)
2209 ld r29, VCPU_GPR(R29)(r4)
2210 ld r30, VCPU_GPR(R30)(r4)
2211 ld r31, VCPU_GPR(R31)(r4)
2213 /* Check the wake reason in SRR1 to see why we got here */
2214 bl kvmppc_check_wake_reason
2216 /* clear our bit in vcore->napping_threads */
2217 34: ld r5,HSTATE_KVM_VCORE(r13)
2218 lbz r7,HSTATE_PTID(r13)
2221 addi r6,r5,VCORE_NAPPING_THREADS
2227 stb r0,HSTATE_NAPPING(r13)
2229 /* See if the wake reason means we need to exit */
2230 stw r12, VCPU_TRAP(r4)
2235 /* see if any other thread is already exiting */
2236 lwz r0,VCORE_ENTRY_EXIT(r5)
2240 b kvmppc_cede_reentry /* if not go back to guest */
2242 /* cede when already previously prodded case */
2245 stb r0,VCPU_PRODDED(r3)
2246 sync /* order testing prodded vs. clearing ceded */
2247 stb r0,VCPU_CEDED(r3)
2251 /* we've ceded but we want to give control to the host */
2253 b hcall_real_fallback
2255 /* Try to handle a machine check in real mode */
2256 machine_check_realmode:
2257 mr r3, r9 /* get vcpu pointer */
2258 bl kvmppc_realmode_machine_check
2260 cmpdi r3, 0 /* Did we handle MCE ? */
2261 ld r9, HSTATE_KVM_VCPU(r13)
2262 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2264 * Deliver unhandled/fatal (e.g. UE) MCE errors to guest through
2265 * machine check interrupt (set HSRR0 to 0x200). And for handled
2266 * errors (no-fatal), just go back to guest execution with current
2267 * HSRR0 instead of exiting guest. This new approach will inject
2268 * machine check to guest for fatal error causing guest to crash.
2270 * The old code used to return to host for unhandled errors which
2271 * was causing guest to hang with soft lockups inside guest and
2272 * makes it difficult to recover guest instance.
2275 ld r11, VCPU_MSR(r9)
2276 bne 2f /* Continue guest execution. */
2277 /* If not, deliver a machine check. SRR0/1 are already set */
2278 li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2279 ld r11, VCPU_MSR(r9)
2280 bl kvmppc_msr_interrupt
2281 2: b fast_interrupt_c_return
2284 * Check the reason we woke from nap, and take appropriate action.
2286 * 0 if nothing needs to be done
2287 * 1 if something happened that needs to be handled by the host
2288 * -1 if there was a guest wakeup (IPI)
2290 * Also sets r12 to the interrupt vector for any interrupt that needs
2291 * to be handled now by the host (0x500 for external interrupt), or zero.
2293 kvmppc_check_wake_reason:
2296 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2298 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2299 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2300 cmpwi r6, 8 /* was it an external interrupt? */
2301 li r12, BOOK3S_INTERRUPT_EXTERNAL
2302 beq kvmppc_read_intr /* if so, see what it was */
2305 cmpwi r6, 6 /* was it the decrementer? */
2308 cmpwi r6, 5 /* privileged doorbell? */
2310 cmpwi r6, 3 /* hypervisor doorbell? */
2312 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2313 li r3, 1 /* anything else, return 1 */
2316 /* hypervisor doorbell */
2317 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2322 * Determine what sort of external interrupt is pending (if any).
2324 * 0 if no interrupt is pending
2325 * 1 if an interrupt is pending that needs to be handled by the host
2326 * -1 if there was a guest wakeup IPI (which has now been cleared)
2329 /* see if a host IPI is pending */
2331 lbz r0, HSTATE_HOST_IPI(r13)
2335 /* Now read the interrupt from the ICP */
2336 ld r6, HSTATE_XICS_PHYS(r13)
2341 rlwinm. r3, r0, 0, 0xffffff
2343 beq 1f /* if nothing pending in the ICP */
2345 /* We found something in the ICP...
2347 * If it's not an IPI, stash it in the PACA and return to
2348 * the host, we don't (yet) handle directing real external
2349 * interrupts directly to the guest
2351 cmpwi r3, XICS_IPI /* if there is, is it an IPI? */
2354 /* It's an IPI, clear the MFRR and EOI it */
2357 stbcix r3, r6, r8 /* clear the IPI */
2358 stwcix r0, r6, r7 /* EOI it */
2361 /* We need to re-check host IPI now in case it got set in the
2362 * meantime. If it's clear, we bounce the interrupt to the
2365 lbz r0, HSTATE_HOST_IPI(r13)
2369 /* OK, it's an IPI for us */
2373 42: /* It's not an IPI and it's for the host, stash it in the PACA
2374 * before exit, it will be picked up by the host ICP driver
2376 stw r0, HSTATE_SAVED_XIRR(r13)
2380 43: /* We raced with the host, we need to resend that IPI, bummer */
2382 stbcix r0, r6, r8 /* set the IPI */
2388 * Save away FP, VMX and VSX registers.
2390 * N.B. r30 and r31 are volatile across this function,
2391 * thus it is not callable from C.
2398 #ifdef CONFIG_ALTIVEC
2400 oris r8,r8,MSR_VEC@h
2401 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2405 oris r8,r8,MSR_VSX@h
2406 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2410 addi r3,r3,VCPU_FPRS
2412 #ifdef CONFIG_ALTIVEC
2414 addi r3,r31,VCPU_VRS
2416 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2418 mfspr r6,SPRN_VRSAVE
2419 stw r6,VCPU_VRSAVE(r31)
2424 * Load up FP, VMX and VSX registers
2426 * N.B. r30 and r31 are volatile across this function,
2427 * thus it is not callable from C.
2434 #ifdef CONFIG_ALTIVEC
2436 oris r8,r8,MSR_VEC@h
2437 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2441 oris r8,r8,MSR_VSX@h
2442 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2446 addi r3,r4,VCPU_FPRS
2448 #ifdef CONFIG_ALTIVEC
2450 addi r3,r31,VCPU_VRS
2452 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2454 lwz r7,VCPU_VRSAVE(r31)
2455 mtspr SPRN_VRSAVE,r7
2461 * We come here if we get any exception or interrupt while we are
2462 * executing host real mode code while in guest MMU context.
2463 * For now just spin, but we should do something better.
2465 kvmppc_bad_host_intr:
2469 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
2470 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
2471 * r11 has the guest MSR value (in/out)
2472 * r9 has a vcpu pointer (in)
2473 * r0 is used as a scratch register
2475 kvmppc_msr_interrupt:
2476 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
2477 cmpwi r0, 2 /* Check if we are in transactional state.. */
2478 ld r11, VCPU_INTR_MSR(r9)
2480 /* ... if transactional, change to suspended */
2482 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
2486 * This works around a hardware bug on POWER8E processors, where
2487 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
2488 * performance monitor interrupt. Instead, when we need to have
2489 * an interrupt pending, we have to arrange for a counter to overflow.
2493 mtspr SPRN_MMCR2, r3
2494 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
2495 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
2496 mtspr SPRN_MMCR0, r3