2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/kvm_asm.h>
25 #include <asm/ptrace.h>
26 #include <asm/hvcall.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/exception-64s.h>
29 #include <asm/kvm_book3s_asm.h>
30 #include <asm/book3s/64/mmu-hash.h>
31 #include <asm/export.h>
34 #include <asm/xive-regs.h>
35 #include <asm/thread_info.h>
36 #include <asm/asm-compat.h>
37 #include <asm/feature-fixups.h>
38 #include <asm/cpuidle.h>
40 /* Sign-extend HDEC if not on POWER9 */
41 #define EXTEND_HDEC(reg) \
44 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
46 /* Values in HSTATE_NAPPING(r13) */
47 #define NAPPING_CEDE 1
48 #define NAPPING_NOVCPU 2
49 #define NAPPING_UNSPLIT 3
51 /* Stack frame offsets for kvmppc_hv_entry */
53 #define STACK_SLOT_TRAP (SFS-4)
54 #define STACK_SLOT_SHORT_PATH (SFS-8)
55 #define STACK_SLOT_TID (SFS-16)
56 #define STACK_SLOT_PSSCR (SFS-24)
57 #define STACK_SLOT_PID (SFS-32)
58 #define STACK_SLOT_IAMR (SFS-40)
59 #define STACK_SLOT_CIABR (SFS-48)
60 #define STACK_SLOT_DAWR (SFS-56)
61 #define STACK_SLOT_DAWRX (SFS-64)
62 #define STACK_SLOT_HFSCR (SFS-72)
63 #define STACK_SLOT_AMR (SFS-80)
64 #define STACK_SLOT_UAMOR (SFS-88)
65 /* the following is used by the P9 short path */
66 #define STACK_SLOT_NVGPRS (SFS-152) /* 18 gprs */
69 * Call kvmppc_hv_entry in real mode.
70 * Must be called with interrupts hard-disabled.
74 * LR = return address to continue at after eventually re-enabling MMU
76 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
78 std r0, PPC_LR_STKOFF(r1)
81 std r10, HSTATE_HOST_MSR(r13)
82 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
87 mtmsrd r0,1 /* clear RI in MSR */
94 /* On P9, do LPCR setting, if necessary */
95 ld r3, HSTATE_SPLIT_MODE(r13)
98 lwz r4, KVM_SPLIT_DO_SET(r3)
104 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
106 ld r4, HSTATE_KVM_VCPU(r13)
109 /* Back from guest - restore host state and return to caller */
112 /* Restore host DABR and DABRX */
113 ld r5,HSTATE_DABR(r13)
117 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
120 ld r3,PACA_SPRG_VDSO(r13)
121 mtspr SPRN_SPRG_VDSO_WRITE,r3
123 /* Reload the host's PMU registers */
124 bl kvmhv_load_host_pmu
127 * Reload DEC. HDEC interrupts were disabled when
128 * we reloaded the host's LPCR value.
130 ld r3, HSTATE_DECEXP(r13)
135 /* hwthread_req may have got set by cede or no vcpu, so clear it */
137 stb r0, HSTATE_HWTHREAD_REQ(r13)
140 * For external interrupts we need to call the Linux
141 * handler to process the interrupt. We do that by jumping
142 * to absolute address 0x500 for external interrupts.
143 * The [h]rfid at the end of the handler will return to
144 * the book3s_hv_interrupts.S code. For other interrupts
145 * we do the rfid to get back to the book3s_hv_interrupts.S
148 ld r8, 112+PPC_LR_STKOFF(r1)
150 ld r7, HSTATE_HOST_MSR(r13)
152 /* Return the trap number on this thread as the return value */
156 * If we came back from the guest via a relocation-on interrupt,
157 * we will be in virtual mode at this point, which makes it a
158 * little easier to get back to the caller.
161 andi. r0, r0, MSR_IR /* in real mode? */
164 /* RFI into the highmem handler */
168 mtmsrd r6, 1 /* Clear RI in MSR */
173 /* Virtual-mode return */
178 kvmppc_primary_no_guest:
179 /* We handle this much like a ceded vcpu */
180 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
181 /* HDEC may be larger than DEC for arch >= v3.00, but since the */
182 /* HDEC value came from DEC in the first place, it will fit */
186 * Make sure the primary has finished the MMU switch.
187 * We should never get here on a secondary thread, but
188 * check it for robustness' sake.
190 ld r5, HSTATE_KVM_VCORE(r13)
191 65: lbz r0, VCORE_IN_GUEST(r5)
198 /* set our bit in napping_threads */
199 ld r5, HSTATE_KVM_VCORE(r13)
200 lbz r7, HSTATE_PTID(r13)
203 addi r6, r5, VCORE_NAPPING_THREADS
208 /* order napping_threads update vs testing entry_exit_map */
211 lwz r7, VCORE_ENTRY_EXIT(r5)
213 bge kvm_novcpu_exit /* another thread already exiting */
214 li r3, NAPPING_NOVCPU
215 stb r3, HSTATE_NAPPING(r13)
217 li r3, 0 /* Don't wake on privileged (OS) doorbell */
222 * Entered from kvm_start_guest if kvm_hstate.napping is set
228 ld r1, HSTATE_HOST_R1(r13)
229 ld r5, HSTATE_KVM_VCORE(r13)
231 stb r0, HSTATE_NAPPING(r13)
233 /* check the wake reason */
234 bl kvmppc_check_wake_reason
237 * Restore volatile registers since we could have called
238 * a C routine in kvmppc_check_wake_reason.
241 ld r5, HSTATE_KVM_VCORE(r13)
243 /* see if any other thread is already exiting */
244 lwz r0, VCORE_ENTRY_EXIT(r5)
248 /* clear our bit in napping_threads */
249 lbz r7, HSTATE_PTID(r13)
252 addi r6, r5, VCORE_NAPPING_THREADS
258 /* See if the wake reason means we need to exit */
262 /* See if our timeslice has expired (HDEC is negative) */
265 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
269 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
270 ld r4, HSTATE_KVM_VCPU(r13)
272 beq kvmppc_primary_no_guest
274 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
275 addi r3, r4, VCPU_TB_RMENTRY
276 bl kvmhv_start_timing
281 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
282 ld r4, HSTATE_KVM_VCPU(r13)
285 addi r3, r4, VCPU_TB_RMEXIT
286 bl kvmhv_accumulate_time
289 stw r12, STACK_SLOT_TRAP(r1)
290 bl kvmhv_commence_exit
292 b kvmhv_switch_to_host
295 * We come in here when wakened from Linux offline idle code.
297 * r3 contains the SRR1 wakeup value, SRR1 is trashed.
299 _GLOBAL(idle_kvm_start_guest)
300 ld r4,PACAEMERGSP(r13)
306 subi r1,r4,STACK_FRAME_OVERHEAD
310 * Could avoid this and pass it through in r3. For now,
311 * code expects it to be in SRR1.
316 stb r0,PACA_FTRACE_ENABLED(r13)
318 li r0,KVM_HWTHREAD_IN_KVM
319 stb r0,HSTATE_HWTHREAD_STATE(r13)
321 /* kvm cede / napping does not come through here */
322 lbz r0,HSTATE_NAPPING(r13)
329 stb r0, HSTATE_NAPPING(r13)
334 * We weren't napping due to cede, so this must be a secondary
335 * thread being woken up to run a guest, or being woken up due
336 * to a stray IPI. (Or due to some machine check or hypervisor
337 * maintenance interrupt while the core is in KVM.)
340 /* Check the wake reason in SRR1 to see why we got here */
341 bl kvmppc_check_wake_reason
343 * kvmppc_check_wake_reason could invoke a C routine, but we
344 * have no volatile registers to restore when we return.
350 /* get vcore pointer, NULL if we have nothing to run */
351 ld r5,HSTATE_KVM_VCORE(r13)
353 /* if we have no vcore to run, go back to sleep */
356 kvm_secondary_got_guest:
358 /* Set HSTATE_DSCR(r13) to something sensible */
359 ld r6, PACA_DSCR_DEFAULT(r13)
360 std r6, HSTATE_DSCR(r13)
362 /* On thread 0 of a subcore, set HDEC to max */
363 lbz r4, HSTATE_PTID(r13)
366 LOAD_REG_ADDR(r6, decrementer_max)
369 /* and set per-LPAR registers, if doing dynamic micro-threading */
370 ld r6, HSTATE_SPLIT_MODE(r13)
374 ld r0, KVM_SPLIT_RPR(r6)
376 ld r0, KVM_SPLIT_PMMAR(r6)
378 ld r0, KVM_SPLIT_LDBAR(r6)
382 /* On P9 we use the split_info for coordinating LPCR changes */
383 lwz r4, KVM_SPLIT_DO_SET(r6)
390 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
392 /* Order load of vcpu after load of vcore */
394 ld r4, HSTATE_KVM_VCPU(r13)
397 /* Back from the guest, go back to nap */
398 /* Clear our vcpu and vcore pointers so we don't come back in early */
400 std r0, HSTATE_KVM_VCPU(r13)
402 * Once we clear HSTATE_KVM_VCORE(r13), the code in
403 * kvmppc_run_core() is going to assume that all our vcpu
404 * state is visible in memory. This lwsync makes sure
408 std r0, HSTATE_KVM_VCORE(r13)
411 * All secondaries exiting guest will fall through this path.
412 * Before proceeding, just check for HMI interrupt and
413 * invoke opal hmi handler. By now we are sure that the
414 * primary thread on this core/subcore has already made partition
415 * switch/TB resync and we are good to call opal hmi handler.
417 cmpwi r12, BOOK3S_INTERRUPT_HMI
420 li r3,0 /* NULL argument */
421 bl hmi_exception_realmode
423 * At this point we have finished executing in the guest.
424 * We need to wait for hwthread_req to become zero, since
425 * we may not turn on the MMU while hwthread_req is non-zero.
426 * While waiting we also need to check if we get given a vcpu to run.
429 lbz r3, HSTATE_HWTHREAD_REQ(r13)
433 li r0, KVM_HWTHREAD_IN_KERNEL
434 stb r0, HSTATE_HWTHREAD_STATE(r13)
435 /* need to recheck hwthread_req after a barrier, to avoid race */
437 lbz r3, HSTATE_HWTHREAD_REQ(r13)
442 * Jump to idle_return_gpr_loss, which returns to the
443 * idle_kvm_start_guest caller.
447 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
449 /* set up r3 for return */
452 addi r1, r1, STACK_FRAME_OVERHEAD
461 ld r5, HSTATE_KVM_VCORE(r13)
464 ld r3, HSTATE_SPLIT_MODE(r13)
467 lwz r0, KVM_SPLIT_DO_SET(r3)
470 lwz r0, KVM_SPLIT_DO_RESTORE(r3)
473 lbz r0, KVM_SPLIT_DO_NAP(r3)
479 b kvm_secondary_got_guest
481 54: li r0, KVM_HWTHREAD_IN_KVM
482 stb r0, HSTATE_HWTHREAD_STATE(r13)
486 /* Set LPCR, LPIDR etc. on P9 */
494 bl kvmhv_p9_restore_lpcr
499 * Here the primary thread is trying to return the core to
500 * whole-core mode, so we need to nap.
504 * When secondaries are napping in kvm_unsplit_nap() with
505 * hwthread_req = 1, HMI goes ignored even though subcores are
506 * already exited the guest. Hence HMI keeps waking up secondaries
507 * from nap in a loop and secondaries always go back to nap since
508 * no vcore is assigned to them. This makes impossible for primary
509 * thread to get hold of secondary threads resulting into a soft
510 * lockup in KVM path.
512 * Let us check if HMI is pending and handle it before we go to nap.
514 cmpwi r12, BOOK3S_INTERRUPT_HMI
516 li r3, 0 /* NULL argument */
517 bl hmi_exception_realmode
520 * Ensure that secondary doesn't nap when it has
521 * its vcore pointer set.
523 sync /* matches smp_mb() before setting split_info.do_nap */
524 ld r0, HSTATE_KVM_VCORE(r13)
527 /* clear any pending message */
529 lis r6, (PPC_DBELL_SERVER << (63-36))@h
531 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
532 /* Set kvm_split_mode.napped[tid] = 1 */
533 ld r3, HSTATE_SPLIT_MODE(r13)
535 lbz r4, HSTATE_TID(r13)
536 addi r4, r4, KVM_SPLIT_NAPPED
538 /* Check the do_nap flag again after setting napped[] */
540 lbz r0, KVM_SPLIT_DO_NAP(r3)
543 li r3, NAPPING_UNSPLIT
544 stb r3, HSTATE_NAPPING(r13)
545 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
547 rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
554 /******************************************************************************
558 *****************************************************************************/
560 .global kvmppc_hv_entry
565 * R4 = vcpu pointer (or NULL)
570 * all other volatile GPRS = free
571 * Does not preserve non-volatile GPRs or CR fields
574 std r0, PPC_LR_STKOFF(r1)
577 /* Save R1 in the PACA */
578 std r1, HSTATE_HOST_R1(r13)
580 li r6, KVM_GUEST_MODE_HOST_HV
581 stb r6, HSTATE_IN_GUEST(r13)
583 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
584 /* Store initial timestamp */
587 addi r3, r4, VCPU_TB_RMENTRY
588 bl kvmhv_start_timing
592 /* Use cr7 as an indication of radix mode */
593 ld r5, HSTATE_KVM_VCORE(r13)
594 ld r9, VCORE_KVM(r5) /* pointer to struct kvm */
595 lbz r0, KVM_RADIX(r9)
599 * POWER7/POWER8 host -> guest partition switch code.
600 * We don't have to lock against concurrent tlbies,
601 * but we do have to coordinate across hardware threads.
603 /* Set bit in entry map iff exit map is zero. */
605 lbz r6, HSTATE_PTID(r13)
607 addi r8, r5, VCORE_ENTRY_EXIT
609 cmpwi r3, 0x100 /* any threads starting to exit? */
610 bge secondary_too_late /* if so we're too late to the party */
615 /* Primary thread switches to guest partition. */
619 /* Radix has already switched LPID and flushed core TLB */
625 li r0,LPID_RSVD /* switch to reserved LPID */
628 mtspr SPRN_SDR1,r6 /* switch to partition page table */
629 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
633 /* See if we need to flush the TLB. Hash has to be done in RM */
634 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
637 * On POWER9, individual threads can come in here, but the
638 * TLB is shared between the 4 threads in a core, hence
639 * invalidating on one thread invalidates for all.
640 * Thus we make all 4 threads use the same bit here.
643 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
644 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
645 srdi r6,r6,6 /* doubleword number */
646 sldi r6,r6,3 /* address offset */
648 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
654 /* Flush the TLB of any entries for this LPID */
655 lwz r0,KVM_TLB_SETS(r9)
657 li r7,0x800 /* IS field = 0b10 */
659 li r0,0 /* RS for P9 version of tlbiel */
660 28: tlbiel r7 /* On P9, rs=0, RIC=0, PRS=0, R=0 */
664 23: ldarx r7,0,r6 /* clear the bit after TLB flushed */
669 /* Add timebase offset onto timebase */
670 22: ld r8,VCORE_TB_OFFSET(r5)
673 std r8, VCORE_TB_OFFSET_APPL(r5)
674 mftb r6 /* current host timebase */
676 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
677 mftb r7 /* check if lower 24 bits overflowed */
682 addis r8,r8,0x100 /* if so, increment upper 40 bits */
685 /* Load guest PCR value to select appropriate compat mode */
686 37: ld r7, VCORE_PCR(r5)
693 /* DPDES and VTB are shared between threads */
694 ld r8, VCORE_DPDES(r5)
698 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
700 /* Mark the subcore state as inside guest */
701 bl kvmppc_subcore_enter_guest
703 ld r5, HSTATE_KVM_VCORE(r13)
704 ld r4, HSTATE_KVM_VCPU(r13)
706 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
708 /* Do we have a guest vcpu to run? */
710 beq kvmppc_primary_no_guest
712 /* Increment yield count if they have a VPA */
716 li r6, LPPACA_YIELDCOUNT
721 stb r6, VCPU_VPA_DIRTY(r4)
724 /* Save purr/spurr */
727 std r5,HSTATE_PURR(r13)
728 std r6,HSTATE_SPURR(r13)
734 /* Save host values of some registers */
739 std r5, STACK_SLOT_TID(r1)
740 std r6, STACK_SLOT_PSSCR(r1)
741 std r7, STACK_SLOT_PID(r1)
743 std r5, STACK_SLOT_HFSCR(r1)
744 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
750 std r5, STACK_SLOT_CIABR(r1)
751 std r6, STACK_SLOT_DAWR(r1)
752 std r7, STACK_SLOT_DAWRX(r1)
753 std r8, STACK_SLOT_IAMR(r1)
754 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
757 std r5, STACK_SLOT_AMR(r1)
759 std r6, STACK_SLOT_UAMOR(r1)
762 /* Set partition DABR */
763 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
764 lwz r5,VCPU_DABRX(r4)
769 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
771 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
773 * Branch around the call if both CPU_FTR_TM and
774 * CPU_FTR_P9_TM_HV_ASSIST are off.
778 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
780 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
784 li r5, 0 /* don't preserve non-vol regs */
785 bl kvmppc_restore_tm_hv
787 ld r4, HSTATE_KVM_VCPU(r13)
791 /* Load guest PMU registers; r4 = vcpu pointer here */
793 bl kvmhv_load_guest_pmu
795 /* Load up FP, VMX and VSX registers */
796 ld r4, HSTATE_KVM_VCPU(r13)
799 ld r14, VCPU_GPR(R14)(r4)
800 ld r15, VCPU_GPR(R15)(r4)
801 ld r16, VCPU_GPR(R16)(r4)
802 ld r17, VCPU_GPR(R17)(r4)
803 ld r18, VCPU_GPR(R18)(r4)
804 ld r19, VCPU_GPR(R19)(r4)
805 ld r20, VCPU_GPR(R20)(r4)
806 ld r21, VCPU_GPR(R21)(r4)
807 ld r22, VCPU_GPR(R22)(r4)
808 ld r23, VCPU_GPR(R23)(r4)
809 ld r24, VCPU_GPR(R24)(r4)
810 ld r25, VCPU_GPR(R25)(r4)
811 ld r26, VCPU_GPR(R26)(r4)
812 ld r27, VCPU_GPR(R27)(r4)
813 ld r28, VCPU_GPR(R28)(r4)
814 ld r29, VCPU_GPR(R29)(r4)
815 ld r30, VCPU_GPR(R30)(r4)
816 ld r31, VCPU_GPR(R31)(r4)
818 /* Switch DSCR to guest value */
823 /* Skip next section on POWER7 */
825 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
826 /* Load up POWER8-specific registers */
828 lwz r6, VCPU_PSPB(r4)
834 * Handle broken DAWR case by not writing it. This means we
835 * can still store the DAWR register for migration.
837 LOAD_REG_ADDR(r5, dawr_force_enable)
842 ld r6, VCPU_DAWRX(r4)
846 ld r7, VCPU_CIABR(r4)
851 ld r8, VCPU_EBBHR(r4)
854 ld r5, VCPU_EBBRR(r4)
855 ld r6, VCPU_BESCR(r4)
856 lwz r7, VCPU_GUEST_PID(r4)
863 /* POWER8-only registers */
864 ld r5, VCPU_TCSCR(r4)
866 ld r7, VCPU_CSIGR(r4)
874 /* POWER9-only registers */
876 ld r6, VCPU_PSSCR(r4)
877 lbz r8, HSTATE_FAKE_SUSPEND(r13)
878 oris r6, r6, PSSCR_EC@h /* This makes stop trap to HV */
879 rldimi r6, r8, PSSCR_FAKE_SUSPEND_LG, 63 - PSSCR_FAKE_SUSPEND_LG
880 ld r7, VCPU_HFSCR(r4)
884 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
887 ld r5, VCPU_SPRG0(r4)
888 ld r6, VCPU_SPRG1(r4)
889 ld r7, VCPU_SPRG2(r4)
890 ld r8, VCPU_SPRG3(r4)
896 /* Load up DAR and DSISR */
898 lwz r6, VCPU_DSISR(r4)
902 /* Restore AMR and UAMOR, set AMOR to all 1s */
910 /* Restore state of CTRL run bit; assume 1 on entry */
918 /* Secondary threads wait for primary to have done partition switch */
919 ld r5, HSTATE_KVM_VCORE(r13)
920 lbz r6, HSTATE_PTID(r13)
923 lbz r0, VCORE_IN_GUEST(r5)
927 20: lwz r3, VCORE_ENTRY_EXIT(r5)
930 lbz r0, VCORE_IN_GUEST(r5)
941 * Set the decrementer to the guest decrementer.
943 ld r8,VCPU_DEC_EXPIRES(r4)
944 /* r8 is a host timebase value here, convert to guest TB */
945 ld r5,HSTATE_KVM_VCORE(r13)
946 ld r6,VCORE_TB_OFFSET_APPL(r5)
952 /* Check if HDEC expires soon */
955 cmpdi r3, 512 /* 1 microsecond */
958 /* For hash guest, clear out and reload the SLB */
960 lbz r0, KVM_RADIX(r6)
968 /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
969 lwz r5,VCPU_SLB_MAX(r4)
974 1: ld r8,VCPU_SLB_E(r6)
977 addi r6,r6,VCPU_SLB_SIZE
981 #ifdef CONFIG_KVM_XICS
982 /* We are entering the guest on that thread, push VCPU to XIVE */
983 ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
986 ld r11, VCPU_XIVE_SAVED_STATE(r4)
990 lwz r11, VCPU_XIVE_CAM_WORD(r4)
991 li r9, TM_QW1_OS + TM_WORD2
994 stb r9, VCPU_XIVE_PUSHED(r4)
998 * We clear the irq_pending flag. There is a small chance of a
999 * race vs. the escalation interrupt happening on another
1000 * processor setting it again, but the only consequence is to
1001 * cause a spurrious wakeup on the next H_CEDE which is not an
1005 stb r0, VCPU_IRQ_PENDING(r4)
1008 * In single escalation mode, if the escalation interrupt is
1011 lbz r0, VCPU_XIVE_ESC_ON(r4)
1014 ld r10, VCPU_XIVE_ESC_RADDR(r4)
1015 li r9, XIVE_ESB_SET_PQ_01
1019 /* We have a possible subtle race here: The escalation interrupt might
1020 * have fired and be on its way to the host queue while we mask it,
1021 * and if we unmask it early enough (re-cede right away), there is
1022 * a theorical possibility that it fires again, thus landing in the
1023 * target queue more than once which is a big no-no.
1025 * Fortunately, solving this is rather easy. If the above load setting
1026 * PQ to 01 returns a previous value where P is set, then we know the
1027 * escalation interrupt is somewhere on its way to the host. In that
1028 * case we simply don't clear the xive_esc_on flag below. It will be
1029 * eventually cleared by the handler for the escalation interrupt.
1031 * Then, when doing a cede, we check that flag again before re-enabling
1032 * the escalation interrupt, and if set, we abort the cede.
1034 andi. r0, r0, XIVE_ESB_VAL_P
1037 /* Now P is 0, we can clear the flag */
1039 stb r0, VCPU_XIVE_ESC_ON(r4)
1042 #endif /* CONFIG_KVM_XICS */
1045 stw r0, STACK_SLOT_SHORT_PATH(r1)
1047 deliver_guest_interrupt: /* r4 = vcpu, r13 = paca */
1048 /* Check if we can deliver an external or decrementer interrupt now */
1049 ld r0, VCPU_PENDING_EXC(r4)
1051 /* On POWER9, also check for emulated doorbell interrupt */
1052 lbz r3, VCPU_DBELL_REQ(r4)
1054 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1058 bl kvmppc_guest_entry_inject_int
1059 ld r4, HSTATE_KVM_VCPU(r13)
1061 ld r6, VCPU_SRR0(r4)
1062 ld r7, VCPU_SRR1(r4)
1068 ld r11, VCPU_MSR(r4)
1069 /* r11 = vcpu->arch.msr & ~MSR_HV */
1070 rldicl r11, r11, 63 - MSR_HV_LG, 1
1071 rotldi r11, r11, 1 + MSR_HV_LG
1072 ori r11, r11, MSR_ME
1082 * R10: value for HSRR0
1083 * R11: value for HSRR1
1088 stb r0,VCPU_CEDED(r4) /* cancel cede */
1089 mtspr SPRN_HSRR0,r10
1090 mtspr SPRN_HSRR1,r11
1092 /* Activate guest mode, so faults get handled by KVM */
1093 li r9, KVM_GUEST_MODE_GUEST_HV
1094 stb r9, HSTATE_IN_GUEST(r13)
1096 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1097 /* Accumulate timing */
1098 addi r3, r4, VCPU_TB_GUEST
1099 bl kvmhv_accumulate_time
1105 ld r5, VCPU_CFAR(r4)
1107 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1110 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1117 ld r1, VCPU_GPR(R1)(r4)
1118 ld r2, VCPU_GPR(R2)(r4)
1119 ld r3, VCPU_GPR(R3)(r4)
1120 ld r5, VCPU_GPR(R5)(r4)
1121 ld r6, VCPU_GPR(R6)(r4)
1122 ld r7, VCPU_GPR(R7)(r4)
1123 ld r8, VCPU_GPR(R8)(r4)
1124 ld r9, VCPU_GPR(R9)(r4)
1125 ld r10, VCPU_GPR(R10)(r4)
1126 ld r11, VCPU_GPR(R11)(r4)
1127 ld r12, VCPU_GPR(R12)(r4)
1128 ld r13, VCPU_GPR(R13)(r4)
1132 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1134 /* Move canary into DSISR to check for later */
1137 mtspr SPRN_HDSISR, r0
1138 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1140 ld r0, VCPU_GPR(R0)(r4)
1141 ld r4, VCPU_GPR(R4)(r4)
1146 * Enter the guest on a P9 or later system where we have exactly
1147 * one vcpu per vcore and we don't need to go to real mode
1148 * (which implies that host and guest are both using radix MMU mode).
1150 * Most SPRs and all the VSRs have been loaded already.
1152 _GLOBAL(__kvmhv_vcpu_entry_p9)
1153 EXPORT_SYMBOL_GPL(__kvmhv_vcpu_entry_p9)
1155 std r0, PPC_LR_STKOFF(r1)
1159 stw r0, STACK_SLOT_SHORT_PATH(r1)
1161 std r3, HSTATE_KVM_VCPU(r13)
1165 std r1, HSTATE_HOST_R1(r13)
1169 std reg, STACK_SLOT_NVGPRS + ((reg - 14) * 8)(r1)
1175 ld reg, __VCPU_GPR(reg)(r3)
1180 std r10, HSTATE_HOST_MSR(r13)
1183 b fast_guest_entry_c
1184 guest_exit_short_path:
1186 li r0, KVM_GUEST_MODE_NONE
1187 stb r0, HSTATE_IN_GUEST(r13)
1191 std reg, __VCPU_GPR(reg)(r9)
1197 ld reg, STACK_SLOT_NVGPRS + ((reg - 14) * 8)(r1)
1204 mr r3, r12 /* trap number */
1207 ld r0, PPC_LR_STKOFF(r1)
1210 /* If we are in real mode, do a rfid to get back to the caller */
1212 andi. r5, r4, MSR_IR
1214 rldicl r5, r4, 64 - MSR_TS_S_LG, 62 /* extract TS field */
1216 ld r10, HSTATE_HOST_MSR(r13)
1217 rldimi r10, r5, MSR_TS_S_LG, 63 - MSR_TS_T_LG
1218 mtspr SPRN_SRR1, r10
1224 stw r12, STACK_SLOT_TRAP(r1)
1227 stw r12, VCPU_TRAP(r4)
1228 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1229 addi r3, r4, VCPU_TB_RMEXIT
1230 bl kvmhv_accumulate_time
1232 11: b kvmhv_switch_to_host
1239 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
1240 12: stw r12, VCPU_TRAP(r4)
1242 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1243 addi r3, r4, VCPU_TB_RMEXIT
1244 bl kvmhv_accumulate_time
1248 /******************************************************************************
1252 *****************************************************************************/
1255 * We come here from the first-level interrupt handlers.
1257 .globl kvmppc_interrupt_hv
1258 kvmppc_interrupt_hv:
1260 * Register contents:
1261 * R12 = (guest CR << 32) | interrupt vector
1263 * guest R12 saved in shadow VCPU SCRATCH0
1264 * guest CTR saved in shadow VCPU SCRATCH1 if RELOCATABLE
1265 * guest R13 saved in SPRN_SCRATCH0
1267 std r9, HSTATE_SCRATCH2(r13)
1268 lbz r9, HSTATE_IN_GUEST(r13)
1269 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1270 beq kvmppc_bad_host_intr
1271 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1272 cmpwi r9, KVM_GUEST_MODE_GUEST
1273 ld r9, HSTATE_SCRATCH2(r13)
1274 beq kvmppc_interrupt_pr
1276 /* We're now back in the host but in guest MMU context */
1277 li r9, KVM_GUEST_MODE_HOST_HV
1278 stb r9, HSTATE_IN_GUEST(r13)
1280 ld r9, HSTATE_KVM_VCPU(r13)
1282 /* Save registers */
1284 std r0, VCPU_GPR(R0)(r9)
1285 std r1, VCPU_GPR(R1)(r9)
1286 std r2, VCPU_GPR(R2)(r9)
1287 std r3, VCPU_GPR(R3)(r9)
1288 std r4, VCPU_GPR(R4)(r9)
1289 std r5, VCPU_GPR(R5)(r9)
1290 std r6, VCPU_GPR(R6)(r9)
1291 std r7, VCPU_GPR(R7)(r9)
1292 std r8, VCPU_GPR(R8)(r9)
1293 ld r0, HSTATE_SCRATCH2(r13)
1294 std r0, VCPU_GPR(R9)(r9)
1295 std r10, VCPU_GPR(R10)(r9)
1296 std r11, VCPU_GPR(R11)(r9)
1297 ld r3, HSTATE_SCRATCH0(r13)
1298 std r3, VCPU_GPR(R12)(r9)
1299 /* CR is in the high half of r12 */
1303 ld r3, HSTATE_CFAR(r13)
1304 std r3, VCPU_CFAR(r9)
1305 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1307 ld r4, HSTATE_PPR(r13)
1308 std r4, VCPU_PPR(r9)
1309 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1311 /* Restore R1/R2 so we can handle faults */
1312 ld r1, HSTATE_HOST_R1(r13)
1315 mfspr r10, SPRN_SRR0
1316 mfspr r11, SPRN_SRR1
1317 std r10, VCPU_SRR0(r9)
1318 std r11, VCPU_SRR1(r9)
1319 /* trap is in the low half of r12, clear CR from the high half */
1321 andi. r0, r12, 2 /* need to read HSRR0/1? */
1323 mfspr r10, SPRN_HSRR0
1324 mfspr r11, SPRN_HSRR1
1326 1: std r10, VCPU_PC(r9)
1327 std r11, VCPU_MSR(r9)
1331 std r3, VCPU_GPR(R13)(r9)
1334 stw r12,VCPU_TRAP(r9)
1337 * Now that we have saved away SRR0/1 and HSRR0/1,
1338 * interrupts are recoverable in principle, so set MSR_RI.
1339 * This becomes important for relocation-on interrupts from
1340 * the guest, which we can get in radix mode on POWER9.
1345 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1346 addi r3, r9, VCPU_TB_RMINTR
1348 bl kvmhv_accumulate_time
1349 ld r5, VCPU_GPR(R5)(r9)
1350 ld r6, VCPU_GPR(R6)(r9)
1351 ld r7, VCPU_GPR(R7)(r9)
1352 ld r8, VCPU_GPR(R8)(r9)
1355 /* Save HEIR (HV emulation assist reg) in emul_inst
1356 if this is an HEI (HV emulation interrupt, e40) */
1357 li r3,KVM_INST_FETCH_FAILED
1358 stw r3,VCPU_LAST_INST(r9)
1359 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1362 11: stw r3,VCPU_HEIR(r9)
1364 /* these are volatile across C function calls */
1365 #ifdef CONFIG_RELOCATABLE
1366 ld r3, HSTATE_SCRATCH1(r13)
1372 std r3, VCPU_CTR(r9)
1373 std r4, VCPU_XER(r9)
1375 /* Save more register state */
1378 std r3, VCPU_DAR(r9)
1379 stw r4, VCPU_DSISR(r9)
1381 /* If this is a page table miss then see if it's theirs or ours */
1382 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1384 std r3, VCPU_FAULT_DAR(r9)
1385 stw r4, VCPU_FAULT_DSISR(r9)
1386 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1389 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1390 /* For softpatch interrupt, go off and do TM instruction emulation */
1391 cmpwi r12, BOOK3S_INTERRUPT_HV_SOFTPATCH
1395 /* See if this is a leftover HDEC interrupt */
1396 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1402 bge fast_guest_return
1404 /* See if this is an hcall we can handle in real mode */
1405 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1406 beq hcall_try_real_mode
1408 /* Hypervisor doorbell - exit only if host IPI flag set */
1409 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1414 /* always exit if we're running a nested guest */
1415 ld r0, VCPU_NESTED(r9)
1418 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1419 lbz r0, HSTATE_HOST_IPI(r13)
1421 beq maybe_reenter_guest
1424 /* If it's a hypervisor facility unavailable interrupt, save HFSCR */
1425 cmpwi r12, BOOK3S_INTERRUPT_H_FAC_UNAVAIL
1427 mfspr r3, SPRN_HFSCR
1428 std r3, VCPU_HFSCR(r9)
1431 /* External interrupt ? */
1432 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1433 beq kvmppc_guest_external
1434 /* See if it is a machine check */
1435 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1436 beq machine_check_realmode
1437 /* Or a hypervisor maintenance interrupt */
1438 cmpwi r12, BOOK3S_INTERRUPT_HMI
1441 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1443 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1444 addi r3, r9, VCPU_TB_RMEXIT
1446 bl kvmhv_accumulate_time
1448 #ifdef CONFIG_KVM_XICS
1449 /* We are exiting, pull the VP from the XIVE */
1450 lbz r0, VCPU_XIVE_PUSHED(r9)
1453 li r7, TM_SPC_PULL_OS_CTX
1456 andi. r0, r0, MSR_DR /* in real mode? */
1458 ld r10, HSTATE_XIVE_TIMA_VIRT(r13)
1461 /* First load to pull the context, we ignore the value */
1464 /* Second load to recover the context state (Words 0 and 1) */
1467 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
1470 /* First load to pull the context, we ignore the value */
1473 /* Second load to recover the context state (Words 0 and 1) */
1475 3: std r11, VCPU_XIVE_SAVED_STATE(r9)
1476 /* Fixup some of the state for the next load */
1479 stb r10, VCPU_XIVE_PUSHED(r9)
1480 stb r10, (VCPU_XIVE_SAVED_STATE+3)(r9)
1481 stb r0, (VCPU_XIVE_SAVED_STATE+4)(r9)
1484 #endif /* CONFIG_KVM_XICS */
1486 /* If we came in through the P9 short path, go back out to C now */
1487 lwz r0, STACK_SLOT_SHORT_PATH(r1)
1489 bne guest_exit_short_path
1491 /* For hash guest, read the guest SLB and save it away */
1493 lbz r0, KVM_RADIX(r5)
1496 bne 3f /* for radix, save 0 entries */
1497 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1502 andis. r0,r8,SLB_ESID_V@h
1504 add r8,r8,r6 /* put index in */
1506 std r8,VCPU_SLB_E(r7)
1507 std r3,VCPU_SLB_V(r7)
1508 addi r7,r7,VCPU_SLB_SIZE
1512 /* Finally clear out the SLB */
1517 3: stw r5,VCPU_SLB_MAX(r9)
1519 /* load host SLB entries */
1520 BEGIN_MMU_FTR_SECTION
1522 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
1523 ld r8,PACA_SLBSHADOWPTR(r13)
1525 .rept SLB_NUM_BOLTED
1526 li r3, SLBSHADOW_SAVEAREA
1530 andis. r7,r5,SLB_ESID_V@h
1538 stw r12, STACK_SLOT_TRAP(r1)
1541 /* Do this before kvmhv_commence_exit so we know TB is guest TB */
1542 ld r3, HSTATE_KVM_VCORE(r13)
1545 /* On P9, if the guest has large decr enabled, don't sign extend */
1547 ld r4, VCORE_LPCR(r3)
1548 andis. r4, r4, LPCR_LD@h
1550 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1553 /* r5 is a guest timebase value here, convert to host TB */
1554 ld r4,VCORE_TB_OFFSET_APPL(r3)
1556 std r5,VCPU_DEC_EXPIRES(r9)
1558 /* Increment exit count, poke other threads to exit */
1560 bl kvmhv_commence_exit
1562 ld r9, HSTATE_KVM_VCPU(r13)
1564 /* Stop others sending VCPU interrupts to this physical CPU */
1566 stw r0, VCPU_CPU(r9)
1567 stw r0, VCPU_THREAD_CPU(r9)
1569 /* Save guest CTRL register, set runlatch to 1 */
1571 stw r6,VCPU_CTRL(r9)
1578 * Save the guest PURR/SPURR
1583 ld r8,VCPU_SPURR(r9)
1584 std r5,VCPU_PURR(r9)
1585 std r6,VCPU_SPURR(r9)
1590 * Restore host PURR/SPURR and add guest times
1591 * so that the time in the guest gets accounted.
1593 ld r3,HSTATE_PURR(r13)
1594 ld r4,HSTATE_SPURR(r13)
1602 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1603 /* Save POWER8-specific registers */
1607 std r5, VCPU_IAMR(r9)
1608 stw r6, VCPU_PSPB(r9)
1609 std r7, VCPU_FSCR(r9)
1613 std r7, VCPU_TAR(r9)
1614 mfspr r8, SPRN_EBBHR
1615 std r8, VCPU_EBBHR(r9)
1616 mfspr r5, SPRN_EBBRR
1617 mfspr r6, SPRN_BESCR
1620 std r5, VCPU_EBBRR(r9)
1621 std r6, VCPU_BESCR(r9)
1622 stw r7, VCPU_GUEST_PID(r9)
1623 std r8, VCPU_WORT(r9)
1625 mfspr r5, SPRN_TCSCR
1627 mfspr r7, SPRN_CSIGR
1629 std r5, VCPU_TCSCR(r9)
1630 std r6, VCPU_ACOP(r9)
1631 std r7, VCPU_CSIGR(r9)
1632 std r8, VCPU_TACR(r9)
1635 mfspr r6, SPRN_PSSCR
1636 std r5, VCPU_TID(r9)
1637 rldicl r6, r6, 4, 50 /* r6 &= PSSCR_GUEST_VIS */
1639 std r6, VCPU_PSSCR(r9)
1640 /* Restore host HFSCR value */
1641 ld r7, STACK_SLOT_HFSCR(r1)
1642 mtspr SPRN_HFSCR, r7
1643 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
1645 * Restore various registers to 0, where non-zero values
1646 * set by the guest could disrupt the host.
1652 mtspr SPRN_TCSCR, r0
1653 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1656 mtspr SPRN_MMCRS, r0
1657 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1659 /* Save and restore AMR, IAMR and UAMOR before turning on the MMU */
1660 ld r8, STACK_SLOT_IAMR(r1)
1663 8: /* Power7 jumps back in here */
1667 std r6,VCPU_UAMOR(r9)
1668 ld r5,STACK_SLOT_AMR(r1)
1669 ld r6,STACK_SLOT_UAMOR(r1)
1671 mtspr SPRN_UAMOR, r6
1673 /* Switch DSCR back to host value */
1675 ld r7, HSTATE_DSCR(r13)
1676 std r8, VCPU_DSCR(r9)
1679 /* Save non-volatile GPRs */
1680 std r14, VCPU_GPR(R14)(r9)
1681 std r15, VCPU_GPR(R15)(r9)
1682 std r16, VCPU_GPR(R16)(r9)
1683 std r17, VCPU_GPR(R17)(r9)
1684 std r18, VCPU_GPR(R18)(r9)
1685 std r19, VCPU_GPR(R19)(r9)
1686 std r20, VCPU_GPR(R20)(r9)
1687 std r21, VCPU_GPR(R21)(r9)
1688 std r22, VCPU_GPR(R22)(r9)
1689 std r23, VCPU_GPR(R23)(r9)
1690 std r24, VCPU_GPR(R24)(r9)
1691 std r25, VCPU_GPR(R25)(r9)
1692 std r26, VCPU_GPR(R26)(r9)
1693 std r27, VCPU_GPR(R27)(r9)
1694 std r28, VCPU_GPR(R28)(r9)
1695 std r29, VCPU_GPR(R29)(r9)
1696 std r30, VCPU_GPR(R30)(r9)
1697 std r31, VCPU_GPR(R31)(r9)
1700 mfspr r3, SPRN_SPRG0
1701 mfspr r4, SPRN_SPRG1
1702 mfspr r5, SPRN_SPRG2
1703 mfspr r6, SPRN_SPRG3
1704 std r3, VCPU_SPRG0(r9)
1705 std r4, VCPU_SPRG1(r9)
1706 std r5, VCPU_SPRG2(r9)
1707 std r6, VCPU_SPRG3(r9)
1713 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1715 * Branch around the call if both CPU_FTR_TM and
1716 * CPU_FTR_P9_TM_HV_ASSIST are off.
1720 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
1722 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
1726 li r5, 0 /* don't preserve non-vol regs */
1727 bl kvmppc_save_tm_hv
1729 ld r9, HSTATE_KVM_VCPU(r13)
1733 /* Increment yield count if they have a VPA */
1734 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1737 li r4, LPPACA_YIELDCOUNT
1742 stb r3, VCPU_VPA_DIRTY(r9)
1744 /* Save PMU registers if requested */
1745 /* r8 and cr0.eq are live here */
1748 beq 21f /* if no VPA, save PMU stuff anyway */
1749 lbz r4, LPPACA_PMCINUSE(r8)
1750 21: bl kvmhv_save_guest_pmu
1751 ld r9, HSTATE_KVM_VCPU(r13)
1753 /* Restore host values of some registers */
1755 ld r5, STACK_SLOT_CIABR(r1)
1756 ld r6, STACK_SLOT_DAWR(r1)
1757 ld r7, STACK_SLOT_DAWRX(r1)
1758 mtspr SPRN_CIABR, r5
1760 * If the DAWR doesn't work, it's ok to write these here as
1761 * this value should always be zero
1764 mtspr SPRN_DAWRX, r7
1765 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1767 ld r5, STACK_SLOT_TID(r1)
1768 ld r6, STACK_SLOT_PSSCR(r1)
1769 ld r7, STACK_SLOT_PID(r1)
1771 mtspr SPRN_PSSCR, r6
1773 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1775 #ifdef CONFIG_PPC_RADIX_MMU
1777 * Are we running hash or radix ?
1780 lbz r0, KVM_RADIX(r5)
1785 * Radix: do eieio; tlbsync; ptesync sequence in case we
1786 * interrupted the guest between a tlbie and a ptesync.
1792 /* Radix: Handle the case where the guest used an illegal PID */
1793 LOAD_REG_ADDR(r4, mmu_base_pid)
1794 lwz r3, VCPU_GUEST_PID(r9)
1800 * Illegal PID, the HW might have prefetched and cached in the TLB
1801 * some translations for the LPID 0 / guest PID combination which
1802 * Linux doesn't know about, so we need to flush that PID out of
1803 * the TLB. First we need to set LPIDR to 0 so tlbiel applies to
1804 * the right context.
1810 /* Then do a congruence class local flush */
1812 lwz r0,KVM_TLB_SETS(r6)
1814 li r7,0x400 /* IS field = 0b01 */
1816 sldi r0,r3,32 /* RS has PID */
1817 1: PPC_TLBIEL(7,0,2,1,1) /* RIC=2, PRS=1, R=1 */
1823 #endif /* CONFIG_PPC_RADIX_MMU */
1826 * POWER7/POWER8 guest -> host partition switch code.
1827 * We don't have to lock against tlbies but we do
1828 * have to coordinate the hardware threads.
1829 * Here STACK_SLOT_TRAP(r1) contains the trap number.
1831 kvmhv_switch_to_host:
1832 /* Secondary threads wait for primary to do partition switch */
1833 ld r5,HSTATE_KVM_VCORE(r13)
1834 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1835 lbz r3,HSTATE_PTID(r13)
1839 13: lbz r3,VCORE_IN_GUEST(r5)
1845 /* Primary thread waits for all the secondaries to exit guest */
1846 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1847 rlwinm r0,r3,32-8,0xff
1853 /* Did we actually switch to the guest at all? */
1854 lbz r6, VCORE_IN_GUEST(r5)
1858 /* Primary thread switches back to host partition */
1859 lwz r7,KVM_HOST_LPID(r4)
1861 ld r6,KVM_HOST_SDR1(r4)
1862 li r8,LPID_RSVD /* switch to reserved LPID */
1865 mtspr SPRN_SDR1,r6 /* switch to host page table */
1866 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1871 /* DPDES and VTB are shared between threads */
1872 mfspr r7, SPRN_DPDES
1874 std r7, VCORE_DPDES(r5)
1875 std r8, VCORE_VTB(r5)
1876 /* clear DPDES so we don't get guest doorbells in the host */
1878 mtspr SPRN_DPDES, r8
1879 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1881 /* Subtract timebase offset from timebase */
1882 ld r8, VCORE_TB_OFFSET_APPL(r5)
1886 std r0, VCORE_TB_OFFSET_APPL(r5)
1887 mftb r6 /* current guest timebase */
1889 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1890 mftb r7 /* check if lower 24 bits overflowed */
1895 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1900 * If this is an HMI, we called kvmppc_realmode_hmi_handler
1901 * above, which may or may not have already called
1902 * kvmppc_subcore_exit_guest. Fortunately, all that
1903 * kvmppc_subcore_exit_guest does is clear a flag, so calling
1904 * it again here is benign even if kvmppc_realmode_hmi_handler
1905 * has already called it.
1907 bl kvmppc_subcore_exit_guest
1909 30: ld r5,HSTATE_KVM_VCORE(r13)
1910 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1913 ld r0, VCORE_PCR(r5)
1919 /* Signal secondary CPUs to continue */
1920 stb r0,VCORE_IN_GUEST(r5)
1921 19: lis r8,0x7fff /* MAX_INT@h */
1926 /* On POWER9 with HPT-on-radix we need to wait for all other threads */
1927 ld r3, HSTATE_SPLIT_MODE(r13)
1930 lwz r8, KVM_SPLIT_DO_RESTORE(r3)
1933 bl kvmhv_p9_restore_lpcr
1937 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1938 ld r8,KVM_HOST_LPCR(r4)
1942 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1943 /* Finish timing, if we have a vcpu */
1944 ld r4, HSTATE_KVM_VCPU(r13)
1948 bl kvmhv_accumulate_time
1951 /* Unset guest mode */
1952 li r0, KVM_GUEST_MODE_NONE
1953 stb r0, HSTATE_IN_GUEST(r13)
1955 lwz r12, STACK_SLOT_TRAP(r1) /* return trap # in r12 */
1956 ld r0, SFS+PPC_LR_STKOFF(r1)
1961 kvmppc_guest_external:
1962 /* External interrupt, first check for host_ipi. If this is
1963 * set, we know the host wants us out so let's do it now
1968 * Restore the active volatile registers after returning from
1971 ld r9, HSTATE_KVM_VCPU(r13)
1972 li r12, BOOK3S_INTERRUPT_EXTERNAL
1975 * kvmppc_read_intr return codes:
1977 * Exit to host (r3 > 0)
1978 * 1 An interrupt is pending that needs to be handled by the host
1979 * Exit guest and return to host by branching to guest_exit_cont
1981 * 2 Passthrough that needs completion in the host
1982 * Exit guest and return to host by branching to guest_exit_cont
1983 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
1984 * to indicate to the host to complete handling the interrupt
1986 * Before returning to guest, we check if any CPU is heading out
1987 * to the host and if so, we head out also. If no CPUs are heading
1988 * check return values <= 0.
1990 * Return to guest (r3 <= 0)
1991 * 0 No external interrupt is pending
1992 * -1 A guest wakeup IPI (which has now been cleared)
1993 * In either case, we return to guest to deliver any pending
1996 * -2 A PCI passthrough external interrupt was handled
1997 * (interrupt was delivered directly to guest)
1998 * Return to guest to deliver any pending guest interrupts.
2004 /* Return code = 2 */
2005 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2006 stw r12, VCPU_TRAP(r9)
2009 1: /* Return code <= 1 */
2013 /* Return code <= 0 */
2014 maybe_reenter_guest:
2015 ld r5, HSTATE_KVM_VCORE(r13)
2016 lwz r0, VCORE_ENTRY_EXIT(r5)
2019 blt deliver_guest_interrupt
2022 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2024 * Softpatch interrupt for transactional memory emulation cases
2025 * on POWER9 DD2.2. This is early in the guest exit path - we
2026 * haven't saved registers or done a treclaim yet.
2029 /* Save instruction image in HEIR */
2031 stw r3, VCPU_HEIR(r9)
2034 * The cases we want to handle here are those where the guest
2035 * is in real suspend mode and is trying to transition to
2036 * transactional mode.
2038 lbz r0, HSTATE_FAKE_SUSPEND(r13)
2039 cmpwi r0, 0 /* keep exiting guest if in fake suspend */
2041 rldicl r3, r11, 64 - MSR_TS_S_LG, 62
2042 cmpwi r3, 1 /* or if not in suspend state */
2045 /* Call C code to do the emulation */
2047 bl kvmhv_p9_tm_emulation_early
2049 ld r9, HSTATE_KVM_VCPU(r13)
2050 li r12, BOOK3S_INTERRUPT_HV_SOFTPATCH
2052 beq guest_exit_cont /* continue exiting if not handled */
2054 ld r11, VCPU_MSR(r9)
2055 b fast_interrupt_c_return /* go back to guest if handled */
2056 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2059 * Check whether an HDSI is an HPTE not found fault or something else.
2060 * If it is an HPTE not found fault that is due to the guest accessing
2061 * a page that they have mapped but which we have paged out, then
2062 * we continue on with the guest exit path. In all other cases,
2063 * reflect the HDSI to the guest as a DSI.
2067 lbz r0, KVM_RADIX(r3)
2069 mfspr r6, SPRN_HDSISR
2071 /* Look for DSISR canary. If we find it, retry instruction */
2074 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2076 bne .Lradix_hdsi /* on radix, just save DAR/DSISR/ASDR */
2077 /* HPTE not found fault or protection fault? */
2078 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
2079 beq 1f /* if not, send it to the guest */
2080 andi. r0, r11, MSR_DR /* data relocation enabled? */
2083 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2085 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2087 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2088 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
2089 bne 7f /* if no SLB entry found */
2090 4: std r4, VCPU_FAULT_DAR(r9)
2091 stw r6, VCPU_FAULT_DSISR(r9)
2093 /* Search the hash table. */
2094 mr r3, r9 /* vcpu pointer */
2095 li r7, 1 /* data fault */
2096 bl kvmppc_hpte_hv_fault
2097 ld r9, HSTATE_KVM_VCPU(r13)
2099 ld r11, VCPU_MSR(r9)
2100 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
2101 cmpdi r3, 0 /* retry the instruction */
2103 cmpdi r3, -1 /* handle in kernel mode */
2105 cmpdi r3, -2 /* MMIO emulation; need instr word */
2108 /* Synthesize a DSI (or DSegI) for the guest */
2109 ld r4, VCPU_FAULT_DAR(r9)
2111 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
2112 mtspr SPRN_DSISR, r6
2113 7: mtspr SPRN_DAR, r4
2114 mtspr SPRN_SRR0, r10
2115 mtspr SPRN_SRR1, r11
2117 bl kvmppc_msr_interrupt
2118 fast_interrupt_c_return:
2119 6: ld r7, VCPU_CTR(r9)
2126 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
2127 ld r5, KVM_VRMA_SLB_V(r5)
2130 /* If this is for emulated MMIO, load the instruction word */
2131 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
2133 /* Set guest mode to 'jump over instruction' so if lwz faults
2134 * we'll just continue at the next IP. */
2135 li r0, KVM_GUEST_MODE_SKIP
2136 stb r0, HSTATE_IN_GUEST(r13)
2138 /* Do the access with MSR:DR enabled */
2140 ori r4, r3, MSR_DR /* Enable paging for data */
2145 /* Store the result */
2146 stw r8, VCPU_LAST_INST(r9)
2148 /* Unset guest mode. */
2149 li r0, KVM_GUEST_MODE_HOST_HV
2150 stb r0, HSTATE_IN_GUEST(r13)
2154 std r4, VCPU_FAULT_DAR(r9)
2155 stw r6, VCPU_FAULT_DSISR(r9)
2158 std r5, VCPU_FAULT_GPA(r9)
2162 * Similarly for an HISI, reflect it to the guest as an ISI unless
2163 * it is an HPTE not found fault for a page that we have paged out.
2167 lbz r0, KVM_RADIX(r3)
2169 bne .Lradix_hisi /* for radix, just save ASDR */
2170 andis. r0, r11, SRR1_ISI_NOPT@h
2172 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
2175 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2177 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2179 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2180 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
2181 bne 7f /* if no SLB entry found */
2183 /* Search the hash table. */
2184 mr r3, r9 /* vcpu pointer */
2187 li r7, 0 /* instruction fault */
2188 bl kvmppc_hpte_hv_fault
2189 ld r9, HSTATE_KVM_VCPU(r13)
2191 ld r11, VCPU_MSR(r9)
2192 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
2193 cmpdi r3, 0 /* retry the instruction */
2194 beq fast_interrupt_c_return
2195 cmpdi r3, -1 /* handle in kernel mode */
2198 /* Synthesize an ISI (or ISegI) for the guest */
2200 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
2201 7: mtspr SPRN_SRR0, r10
2202 mtspr SPRN_SRR1, r11
2204 bl kvmppc_msr_interrupt
2205 b fast_interrupt_c_return
2207 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
2208 ld r5, KVM_VRMA_SLB_V(r6)
2212 * Try to handle an hcall in real mode.
2213 * Returns to the guest if we handle it, or continues on up to
2214 * the kernel if we can't (i.e. if we don't have a handler for
2215 * it, or if the handler returns H_TOO_HARD).
2217 * r5 - r8 contain hcall args,
2218 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
2220 hcall_try_real_mode:
2221 ld r3,VCPU_GPR(R3)(r9)
2223 /* sc 1 from userspace - reflect to guest syscall */
2224 bne sc_1_fast_return
2225 /* sc 1 from nested guest - give it to L1 to handle */
2226 ld r0, VCPU_NESTED(r9)
2230 cmpldi r3,hcall_real_table_end - hcall_real_table
2232 /* See if this hcall is enabled for in-kernel handling */
2234 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
2235 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
2237 ld r0, KVM_ENABLED_HCALLS(r4)
2238 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
2242 /* Get pointer to handler, if any, and call it */
2243 LOAD_REG_ADDR(r4, hcall_real_table)
2249 mr r3,r9 /* get vcpu pointer */
2250 ld r4,VCPU_GPR(R4)(r9)
2253 beq hcall_real_fallback
2254 ld r4,HSTATE_KVM_VCPU(r13)
2255 std r3,VCPU_GPR(R3)(r4)
2263 li r10, BOOK3S_INTERRUPT_SYSCALL
2264 bl kvmppc_msr_interrupt
2268 /* We've attempted a real mode hcall, but it's punted it back
2269 * to userspace. We need to restore some clobbered volatiles
2270 * before resuming the pass-it-to-qemu path */
2271 hcall_real_fallback:
2272 li r12,BOOK3S_INTERRUPT_SYSCALL
2273 ld r9, HSTATE_KVM_VCPU(r13)
2277 .globl hcall_real_table
2279 .long 0 /* 0 - unused */
2280 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
2281 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
2282 .long DOTSYM(kvmppc_h_read) - hcall_real_table
2283 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
2284 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
2285 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
2286 #ifdef CONFIG_SPAPR_TCE_IOMMU
2287 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
2288 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
2293 .long 0 /* 0x24 - H_SET_SPRG0 */
2294 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
2309 #ifdef CONFIG_KVM_XICS
2310 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
2311 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
2312 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
2313 .long DOTSYM(kvmppc_rm_h_ipoll) - hcall_real_table
2314 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
2316 .long 0 /* 0x64 - H_EOI */
2317 .long 0 /* 0x68 - H_CPPR */
2318 .long 0 /* 0x6c - H_IPI */
2319 .long 0 /* 0x70 - H_IPOLL */
2320 .long 0 /* 0x74 - H_XIRR */
2348 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
2349 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
2365 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
2369 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
2370 #ifdef CONFIG_SPAPR_TCE_IOMMU
2371 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
2372 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
2488 #ifdef CONFIG_KVM_XICS
2489 .long DOTSYM(kvmppc_rm_h_xirr_x) - hcall_real_table
2491 .long 0 /* 0x2fc - H_XIRR_X*/
2493 .long DOTSYM(kvmppc_h_random) - hcall_real_table
2494 .globl hcall_real_table_end
2495 hcall_real_table_end:
2497 _GLOBAL(kvmppc_h_set_xdabr)
2498 EXPORT_SYMBOL_GPL(kvmppc_h_set_xdabr)
2499 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2501 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2504 6: li r3, H_PARAMETER
2507 _GLOBAL(kvmppc_h_set_dabr)
2508 EXPORT_SYMBOL_GPL(kvmppc_h_set_dabr)
2509 li r5, DABRX_USER | DABRX_KERNEL
2513 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2514 std r4,VCPU_DABR(r3)
2515 stw r5, VCPU_DABRX(r3)
2516 mtspr SPRN_DABRX, r5
2517 /* Work around P7 bug where DABR can get corrupted on mtspr */
2518 1: mtspr SPRN_DABR,r4
2527 LOAD_REG_ADDR(r11, dawr_force_enable)
2532 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2533 rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2534 rlwimi r5, r4, 2, DAWRX_WT
2536 std r4, VCPU_DAWR(r3)
2537 std r5, VCPU_DAWRX(r3)
2539 mtspr SPRN_DAWRX, r5
2543 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2545 std r11,VCPU_MSR(r3)
2547 stb r0,VCPU_CEDED(r3)
2548 sync /* order setting ceded vs. testing prodded */
2549 lbz r5,VCPU_PRODDED(r3)
2551 bne kvm_cede_prodded
2552 li r12,0 /* set trap to 0 to say hcall is handled */
2553 stw r12,VCPU_TRAP(r3)
2555 std r0,VCPU_GPR(R3)(r3)
2558 * Set our bit in the bitmask of napping threads unless all the
2559 * other threads are already napping, in which case we send this
2562 ld r5,HSTATE_KVM_VCORE(r13)
2563 lbz r6,HSTATE_PTID(r13)
2564 lwz r8,VCORE_ENTRY_EXIT(r5)
2568 addi r6,r5,VCORE_NAPPING_THREADS
2575 /* order napping_threads update vs testing entry_exit_map */
2578 stb r0,HSTATE_NAPPING(r13)
2579 lwz r7,VCORE_ENTRY_EXIT(r5)
2581 bge 33f /* another thread already exiting */
2584 * Although not specifically required by the architecture, POWER7
2585 * preserves the following registers in nap mode, even if an SMT mode
2586 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2587 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2589 /* Save non-volatile GPRs */
2590 std r14, VCPU_GPR(R14)(r3)
2591 std r15, VCPU_GPR(R15)(r3)
2592 std r16, VCPU_GPR(R16)(r3)
2593 std r17, VCPU_GPR(R17)(r3)
2594 std r18, VCPU_GPR(R18)(r3)
2595 std r19, VCPU_GPR(R19)(r3)
2596 std r20, VCPU_GPR(R20)(r3)
2597 std r21, VCPU_GPR(R21)(r3)
2598 std r22, VCPU_GPR(R22)(r3)
2599 std r23, VCPU_GPR(R23)(r3)
2600 std r24, VCPU_GPR(R24)(r3)
2601 std r25, VCPU_GPR(R25)(r3)
2602 std r26, VCPU_GPR(R26)(r3)
2603 std r27, VCPU_GPR(R27)(r3)
2604 std r28, VCPU_GPR(R28)(r3)
2605 std r29, VCPU_GPR(R29)(r3)
2606 std r30, VCPU_GPR(R30)(r3)
2607 std r31, VCPU_GPR(R31)(r3)
2612 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2614 * Branch around the call if both CPU_FTR_TM and
2615 * CPU_FTR_P9_TM_HV_ASSIST are off.
2619 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
2621 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
2623 ld r3, HSTATE_KVM_VCPU(r13)
2625 li r5, 0 /* don't preserve non-vol regs */
2626 bl kvmppc_save_tm_hv
2632 * Set DEC to the smaller of DEC and HDEC, so that we wake
2633 * no later than the end of our timeslice (HDEC interrupts
2634 * don't wake us from nap).
2640 /* On P9 check whether the guest has large decrementer mode enabled */
2641 ld r6, HSTATE_KVM_VCORE(r13)
2642 ld r6, VCORE_LPCR(r6)
2643 andis. r6, r6, LPCR_LD@h
2645 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2652 /* save expiry time of guest decrementer */
2654 ld r4, HSTATE_KVM_VCPU(r13)
2655 ld r5, HSTATE_KVM_VCORE(r13)
2656 ld r6, VCORE_TB_OFFSET_APPL(r5)
2657 subf r3, r6, r3 /* convert to host TB value */
2658 std r3, VCPU_DEC_EXPIRES(r4)
2660 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2661 ld r4, HSTATE_KVM_VCPU(r13)
2662 addi r3, r4, VCPU_TB_CEDE
2663 bl kvmhv_accumulate_time
2666 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2668 /* Go back to host stack */
2669 ld r1, HSTATE_HOST_R1(r13)
2672 * Take a nap until a decrementer or external or doobell interrupt
2673 * occurs, with PECE1 and PECE0 set in LPCR.
2674 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2675 * Also clear the runlatch bit before napping.
2678 mfspr r0, SPRN_CTRLF
2680 mtspr SPRN_CTRLT, r0
2683 stb r0,HSTATE_HWTHREAD_REQ(r13)
2685 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2687 ori r5, r5, LPCR_PECEDH
2688 rlwimi r5, r3, 0, LPCR_PECEDP
2689 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2691 kvm_nap_sequence: /* desired LPCR value in r5 */
2694 * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset)
2695 * enable state loss = 1 (allow SMT mode switch)
2696 * requested level = 0 (just stop dispatching)
2698 lis r3, (PSSCR_EC | PSSCR_ESL)@h
2699 /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */
2700 li r4, LPCR_PECE_HVEE@higher
2704 li r3, PNV_THREAD_NAP
2705 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
2710 bl isa300_idle_stop_mayloss
2712 bl isa206_idle_insn_mayloss
2713 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
2715 mfspr r0, SPRN_CTRLF
2717 mtspr SPRN_CTRLT, r0
2722 stb r0, PACA_FTRACE_ENABLED(r13)
2724 li r0, KVM_HWTHREAD_IN_KVM
2725 stb r0, HSTATE_HWTHREAD_STATE(r13)
2727 lbz r0, HSTATE_NAPPING(r13)
2728 cmpwi r0, NAPPING_CEDE
2730 cmpwi r0, NAPPING_NOVCPU
2731 beq kvm_novcpu_wakeup
2732 cmpwi r0, NAPPING_UNSPLIT
2733 beq kvm_unsplit_wakeup
2734 twi 31,0,0 /* Nap state must not be zero */
2742 /* Woken by external or decrementer interrupt */
2744 /* get vcpu pointer */
2745 ld r4, HSTATE_KVM_VCPU(r13)
2747 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2748 addi r3, r4, VCPU_TB_RMINTR
2749 bl kvmhv_accumulate_time
2752 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2754 * Branch around the call if both CPU_FTR_TM and
2755 * CPU_FTR_P9_TM_HV_ASSIST are off.
2759 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
2761 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
2765 li r5, 0 /* don't preserve non-vol regs */
2766 bl kvmppc_restore_tm_hv
2768 ld r4, HSTATE_KVM_VCPU(r13)
2772 /* load up FP state */
2775 /* Restore guest decrementer */
2776 ld r3, VCPU_DEC_EXPIRES(r4)
2777 ld r5, HSTATE_KVM_VCORE(r13)
2778 ld r6, VCORE_TB_OFFSET_APPL(r5)
2779 add r3, r3, r6 /* convert host TB to guest TB value */
2785 ld r14, VCPU_GPR(R14)(r4)
2786 ld r15, VCPU_GPR(R15)(r4)
2787 ld r16, VCPU_GPR(R16)(r4)
2788 ld r17, VCPU_GPR(R17)(r4)
2789 ld r18, VCPU_GPR(R18)(r4)
2790 ld r19, VCPU_GPR(R19)(r4)
2791 ld r20, VCPU_GPR(R20)(r4)
2792 ld r21, VCPU_GPR(R21)(r4)
2793 ld r22, VCPU_GPR(R22)(r4)
2794 ld r23, VCPU_GPR(R23)(r4)
2795 ld r24, VCPU_GPR(R24)(r4)
2796 ld r25, VCPU_GPR(R25)(r4)
2797 ld r26, VCPU_GPR(R26)(r4)
2798 ld r27, VCPU_GPR(R27)(r4)
2799 ld r28, VCPU_GPR(R28)(r4)
2800 ld r29, VCPU_GPR(R29)(r4)
2801 ld r30, VCPU_GPR(R30)(r4)
2802 ld r31, VCPU_GPR(R31)(r4)
2804 /* Check the wake reason in SRR1 to see why we got here */
2805 bl kvmppc_check_wake_reason
2808 * Restore volatile registers since we could have called a
2809 * C routine in kvmppc_check_wake_reason
2811 * r3 tells us whether we need to return to host or not
2812 * WARNING: it gets checked further down:
2813 * should not modify r3 until this check is done.
2815 ld r4, HSTATE_KVM_VCPU(r13)
2817 /* clear our bit in vcore->napping_threads */
2818 34: ld r5,HSTATE_KVM_VCORE(r13)
2819 lbz r7,HSTATE_PTID(r13)
2822 addi r6,r5,VCORE_NAPPING_THREADS
2828 stb r0,HSTATE_NAPPING(r13)
2830 /* See if the wake reason saved in r3 means we need to exit */
2831 stw r12, VCPU_TRAP(r4)
2835 b maybe_reenter_guest
2837 /* cede when already previously prodded case */
2840 stb r0,VCPU_PRODDED(r3)
2841 sync /* order testing prodded vs. clearing ceded */
2842 stb r0,VCPU_CEDED(r3)
2846 /* we've ceded but we want to give control to the host */
2848 ld r9, HSTATE_KVM_VCPU(r13)
2849 #ifdef CONFIG_KVM_XICS
2850 /* Abort if we still have a pending escalation */
2851 lbz r5, VCPU_XIVE_ESC_ON(r9)
2855 stb r0, VCPU_CEDED(r9)
2856 1: /* Enable XIVE escalation */
2857 li r5, XIVE_ESB_SET_PQ_00
2859 andi. r0, r0, MSR_DR /* in real mode? */
2861 ld r10, VCPU_XIVE_ESC_VADDR(r9)
2866 1: ld r10, VCPU_XIVE_ESC_RADDR(r9)
2872 stb r0, VCPU_XIVE_ESC_ON(r9)
2873 #endif /* CONFIG_KVM_XICS */
2874 3: b guest_exit_cont
2876 /* Try to do machine check recovery in real mode */
2877 machine_check_realmode:
2878 mr r3, r9 /* get vcpu pointer */
2879 bl kvmppc_realmode_machine_check
2881 /* all machine checks go to virtual mode for further handling */
2882 ld r9, HSTATE_KVM_VCPU(r13)
2883 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2887 * Call C code to handle a HMI in real mode.
2888 * Only the primary thread does the call, secondary threads are handled
2889 * by calling hmi_exception_realmode() after kvmppc_hv_entry returns.
2890 * r9 points to the vcpu on entry
2893 lbz r0, HSTATE_PTID(r13)
2896 bl kvmppc_realmode_hmi_handler
2897 ld r9, HSTATE_KVM_VCPU(r13)
2898 li r12, BOOK3S_INTERRUPT_HMI
2902 * Check the reason we woke from nap, and take appropriate action.
2904 * 0 if nothing needs to be done
2905 * 1 if something happened that needs to be handled by the host
2906 * -1 if there was a guest wakeup (IPI or msgsnd)
2907 * -2 if we handled a PCI passthrough interrupt (returned by
2908 * kvmppc_read_intr only)
2910 * Also sets r12 to the interrupt vector for any interrupt that needs
2911 * to be handled now by the host (0x500 for external interrupt), or zero.
2912 * Modifies all volatile registers (since it may call a C function).
2913 * This routine calls kvmppc_read_intr, a C function, if an external
2914 * interrupt is pending.
2916 kvmppc_check_wake_reason:
2919 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2921 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2922 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2923 cmpwi r6, 8 /* was it an external interrupt? */
2924 beq 7f /* if so, see what it was */
2927 cmpwi r6, 6 /* was it the decrementer? */
2930 cmpwi r6, 5 /* privileged doorbell? */
2932 cmpwi r6, 3 /* hypervisor doorbell? */
2934 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2935 cmpwi r6, 0xa /* Hypervisor maintenance ? */
2937 li r3, 1 /* anything else, return 1 */
2940 /* hypervisor doorbell */
2941 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2944 * Clear the doorbell as we will invoke the handler
2945 * explicitly in the guest exit path.
2947 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2949 /* see if it's a host IPI */
2954 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2955 lbz r0, HSTATE_HOST_IPI(r13)
2958 /* if not, return -1 */
2962 /* Woken up due to Hypervisor maintenance interrupt */
2963 4: li r12, BOOK3S_INTERRUPT_HMI
2967 /* external interrupt - create a stack frame so we can call C */
2969 std r0, PPC_LR_STKOFF(r1)
2970 stdu r1, -PPC_MIN_STKFRM(r1)
2973 li r12, BOOK3S_INTERRUPT_EXTERNAL
2978 * Return code of 2 means PCI passthrough interrupt, but
2979 * we need to return back to host to complete handling the
2980 * interrupt. Trap reason is expected in r12 by guest
2983 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2985 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
2986 addi r1, r1, PPC_MIN_STKFRM
2991 * Save away FP, VMX and VSX registers.
2993 * N.B. r30 and r31 are volatile across this function,
2994 * thus it is not callable from C.
3001 #ifdef CONFIG_ALTIVEC
3003 oris r8,r8,MSR_VEC@h
3004 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3008 oris r8,r8,MSR_VSX@h
3009 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
3012 addi r3,r3,VCPU_FPRS
3014 #ifdef CONFIG_ALTIVEC
3016 addi r3,r31,VCPU_VRS
3018 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3020 mfspr r6,SPRN_VRSAVE
3021 stw r6,VCPU_VRSAVE(r31)
3026 * Load up FP, VMX and VSX registers
3028 * N.B. r30 and r31 are volatile across this function,
3029 * thus it is not callable from C.
3036 #ifdef CONFIG_ALTIVEC
3038 oris r8,r8,MSR_VEC@h
3039 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3043 oris r8,r8,MSR_VSX@h
3044 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
3047 addi r3,r4,VCPU_FPRS
3049 #ifdef CONFIG_ALTIVEC
3051 addi r3,r31,VCPU_VRS
3053 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3055 lwz r7,VCPU_VRSAVE(r31)
3056 mtspr SPRN_VRSAVE,r7
3061 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
3063 * Save transactional state and TM-related registers.
3064 * Called with r3 pointing to the vcpu struct and r4 containing
3065 * the guest MSR value.
3066 * r5 is non-zero iff non-volatile register state needs to be maintained.
3067 * If r5 == 0, this can modify all checkpointed registers, but
3068 * restores r1 and r2 before exit.
3070 _GLOBAL_TOC(kvmppc_save_tm_hv)
3071 EXPORT_SYMBOL_GPL(kvmppc_save_tm_hv)
3072 /* See if we need to handle fake suspend mode */
3075 END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
3077 lbz r0, HSTATE_FAKE_SUSPEND(r13) /* Were we fake suspended? */
3079 beq __kvmppc_save_tm
3081 /* The following code handles the fake_suspend = 1 case */
3083 std r0, PPC_LR_STKOFF(r1)
3084 stdu r1, -PPC_MIN_STKFRM(r1)
3089 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
3092 rldicl. r8, r8, 64 - MSR_TS_S_LG, 62 /* Did we actually hrfid? */
3095 bl pnv_power9_force_smt4_catch
3096 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
3099 /* We have to treclaim here because that's the only way to do S->N */
3100 li r3, TM_CAUSE_KVM_RESCHED
3104 * We were in fake suspend, so we are not going to save the
3105 * register state as the guest checkpointed state (since
3106 * we already have it), therefore we can now use any volatile GPR.
3107 * In fact treclaim in fake suspend state doesn't modify
3112 bl pnv_power9_force_smt4_release
3113 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
3117 mfspr r3, SPRN_PSSCR
3118 /* PSSCR_FAKE_SUSPEND is a write-only bit, but clear it anyway */
3119 li r0, PSSCR_FAKE_SUSPEND
3121 mtspr SPRN_PSSCR, r3
3123 /* Don't save TEXASR, use value from last exit in real suspend state */
3124 ld r9, HSTATE_KVM_VCPU(r13)
3125 mfspr r5, SPRN_TFHAR
3126 mfspr r6, SPRN_TFIAR
3127 std r5, VCPU_TFHAR(r9)
3128 std r6, VCPU_TFIAR(r9)
3130 addi r1, r1, PPC_MIN_STKFRM
3131 ld r0, PPC_LR_STKOFF(r1)
3136 * Restore transactional state and TM-related registers.
3137 * Called with r3 pointing to the vcpu struct
3138 * and r4 containing the guest MSR value.
3139 * r5 is non-zero iff non-volatile register state needs to be maintained.
3140 * This potentially modifies all checkpointed registers.
3141 * It restores r1 and r2 from the PACA.
3143 _GLOBAL_TOC(kvmppc_restore_tm_hv)
3144 EXPORT_SYMBOL_GPL(kvmppc_restore_tm_hv)
3146 * If we are doing TM emulation for the guest on a POWER9 DD2,
3147 * then we don't actually do a trechkpt -- we either set up
3148 * fake-suspend mode, or emulate a TM rollback.
3151 b __kvmppc_restore_tm
3152 END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
3154 std r0, PPC_LR_STKOFF(r1)
3157 stb r0, HSTATE_FAKE_SUSPEND(r13)
3159 /* Turn on TM so we can restore TM SPRs */
3162 rldimi r5, r0, MSR_TM_LG, 63-MSR_TM_LG
3166 * The user may change these outside of a transaction, so they must
3167 * always be context switched.
3169 ld r5, VCPU_TFHAR(r3)
3170 ld r6, VCPU_TFIAR(r3)
3171 ld r7, VCPU_TEXASR(r3)
3172 mtspr SPRN_TFHAR, r5
3173 mtspr SPRN_TFIAR, r6
3174 mtspr SPRN_TEXASR, r7
3176 rldicl. r5, r4, 64 - MSR_TS_S_LG, 62
3177 beqlr /* TM not active in guest */
3179 /* Make sure the failure summary is set */
3180 oris r7, r7, (TEXASR_FS)@h
3181 mtspr SPRN_TEXASR, r7
3183 cmpwi r5, 1 /* check for suspended state */
3185 stb r5, HSTATE_FAKE_SUSPEND(r13)
3186 b 9f /* and return */
3187 10: stdu r1, -PPC_MIN_STKFRM(r1)
3188 /* guest is in transactional state, so simulate rollback */
3189 bl kvmhv_emulate_tm_rollback
3191 addi r1, r1, PPC_MIN_STKFRM
3192 9: ld r0, PPC_LR_STKOFF(r1)
3195 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
3198 * We come here if we get any exception or interrupt while we are
3199 * executing host real mode code while in guest MMU context.
3200 * r12 is (CR << 32) | vector
3201 * r13 points to our PACA
3202 * r12 is saved in HSTATE_SCRATCH0(r13)
3203 * ctr is saved in HSTATE_SCRATCH1(r13) if RELOCATABLE
3204 * r9 is saved in HSTATE_SCRATCH2(r13)
3205 * r13 is saved in HSPRG1
3206 * cfar is saved in HSTATE_CFAR(r13)
3207 * ppr is saved in HSTATE_PPR(r13)
3209 kvmppc_bad_host_intr:
3211 * Switch to the emergency stack, but start half-way down in
3212 * case we were already on it.
3216 ld r1, PACAEMERGSP(r13)
3217 subi r1, r1, THREAD_SIZE/2 + INT_FRAME_SIZE
3230 mfspr r3, SPRN_HSRR0
3231 mfspr r4, SPRN_HSRR1
3233 mfspr r6, SPRN_HDSISR
3235 1: mfspr r3, SPRN_SRR0
3238 mfspr r6, SPRN_DSISR
3243 ld r9, HSTATE_SCRATCH2(r13)
3244 ld r12, HSTATE_SCRATCH0(r13)
3249 ld r5, HSTATE_CFAR(r13)
3250 std r5, ORIG_GPR3(r1)
3252 #ifdef CONFIG_RELOCATABLE
3253 ld r4, HSTATE_SCRATCH1(r13)
3258 lbz r6, PACAIRQSOFTMASK(r13)
3264 LOAD_REG_IMMEDIATE(3, 0x7265677368657265)
3265 std r3, STACK_FRAME_OVERHEAD-16(r1)
3268 * On POWER9 do a minimal restore of the MMU and call C code,
3269 * which will print a message and panic.
3270 * XXX On POWER7 and POWER8, we just spin here since we don't
3271 * know what the other threads are doing (and we don't want to
3272 * coordinate with them) - but at least we now have register state
3273 * in memory that we might be able to look at from another CPU.
3277 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
3278 ld r9, HSTATE_KVM_VCPU(r13)
3279 ld r10, VCPU_KVM(r9)
3284 mtspr SPRN_CIABR, r0
3285 mtspr SPRN_DAWRX, r0
3287 BEGIN_MMU_FTR_SECTION
3289 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
3294 ld r8, PACA_SLBSHADOWPTR(r13)
3295 .rept SLB_NUM_BOLTED
3296 li r3, SLBSHADOW_SAVEAREA
3300 andis. r7, r5, SLB_ESID_V@h
3306 4: lwz r7, KVM_HOST_LPID(r10)
3309 ld r8, KVM_HOST_LPCR(r10)
3312 li r0, KVM_GUEST_MODE_NONE
3313 stb r0, HSTATE_IN_GUEST(r13)
3316 * Turn on the MMU and jump to C code
3320 addi r3, r3, 9f - 5b
3322 rldimi r3, r4, 62, 0 /* ensure 0xc000000000000000 bits are set */
3323 ld r4, PACAKMSR(r13)
3327 9: addi r3, r1, STACK_FRAME_OVERHEAD
3328 bl kvmppc_bad_interrupt
3332 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
3333 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
3334 * r11 has the guest MSR value (in/out)
3335 * r9 has a vcpu pointer (in)
3336 * r0 is used as a scratch register
3338 kvmppc_msr_interrupt:
3339 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
3340 cmpwi r0, 2 /* Check if we are in transactional state.. */
3341 ld r11, VCPU_INTR_MSR(r9)
3343 /* ... if transactional, change to suspended */
3345 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
3349 * Load up guest PMU state. R3 points to the vcpu struct.
3351 _GLOBAL(kvmhv_load_guest_pmu)
3352 EXPORT_SYMBOL_GPL(kvmhv_load_guest_pmu)
3356 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
3357 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
3360 ld r3, VCPU_MMCR(r4)
3361 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
3362 cmpwi r5, MMCR0_PMAO
3363 beql kvmppc_fix_pmao
3364 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
3365 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
3366 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
3367 lwz r6, VCPU_PMC + 8(r4)
3368 lwz r7, VCPU_PMC + 12(r4)
3369 lwz r8, VCPU_PMC + 16(r4)
3370 lwz r9, VCPU_PMC + 20(r4)
3377 ld r3, VCPU_MMCR(r4)
3378 ld r5, VCPU_MMCR + 8(r4)
3379 ld r6, VCPU_MMCR + 16(r4)
3380 ld r7, VCPU_SIAR(r4)
3381 ld r8, VCPU_SDAR(r4)
3382 mtspr SPRN_MMCR1, r5
3383 mtspr SPRN_MMCRA, r6
3387 ld r5, VCPU_MMCR + 24(r4)
3388 ld r6, VCPU_SIER(r4)
3389 mtspr SPRN_MMCR2, r5
3391 BEGIN_FTR_SECTION_NESTED(96)
3392 lwz r7, VCPU_PMC + 24(r4)
3393 lwz r8, VCPU_PMC + 28(r4)
3394 ld r9, VCPU_MMCR + 32(r4)
3395 mtspr SPRN_SPMC1, r7
3396 mtspr SPRN_SPMC2, r8
3397 mtspr SPRN_MMCRS, r9
3398 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
3399 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3400 mtspr SPRN_MMCR0, r3
3406 * Reload host PMU state saved in the PACA by kvmhv_save_host_pmu.
3408 _GLOBAL(kvmhv_load_host_pmu)
3409 EXPORT_SYMBOL_GPL(kvmhv_load_host_pmu)
3411 lbz r4, PACA_PMCINUSE(r13) /* is the host using the PMU? */
3413 beq 23f /* skip if not */
3415 ld r3, HSTATE_MMCR0(r13)
3416 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
3417 cmpwi r4, MMCR0_PMAO
3418 beql kvmppc_fix_pmao
3419 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
3420 lwz r3, HSTATE_PMC1(r13)
3421 lwz r4, HSTATE_PMC2(r13)
3422 lwz r5, HSTATE_PMC3(r13)
3423 lwz r6, HSTATE_PMC4(r13)
3424 lwz r8, HSTATE_PMC5(r13)
3425 lwz r9, HSTATE_PMC6(r13)
3432 ld r3, HSTATE_MMCR0(r13)
3433 ld r4, HSTATE_MMCR1(r13)
3434 ld r5, HSTATE_MMCRA(r13)
3435 ld r6, HSTATE_SIAR(r13)
3436 ld r7, HSTATE_SDAR(r13)
3437 mtspr SPRN_MMCR1, r4
3438 mtspr SPRN_MMCRA, r5
3442 ld r8, HSTATE_MMCR2(r13)
3443 ld r9, HSTATE_SIER(r13)
3444 mtspr SPRN_MMCR2, r8
3446 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3447 mtspr SPRN_MMCR0, r3
3453 * Save guest PMU state into the vcpu struct.
3454 * r3 = vcpu, r4 = full save flag (PMU in use flag set in VPA)
3456 _GLOBAL(kvmhv_save_guest_pmu)
3457 EXPORT_SYMBOL_GPL(kvmhv_save_guest_pmu)
3462 * POWER8 seems to have a hardware bug where setting
3463 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
3464 * when some counters are already negative doesn't seem
3465 * to cause a performance monitor alert (and hence interrupt).
3466 * The effect of this is that when saving the PMU state,
3467 * if there is no PMU alert pending when we read MMCR0
3468 * before freezing the counters, but one becomes pending
3469 * before we read the counters, we lose it.
3470 * To work around this, we need a way to freeze the counters
3471 * before reading MMCR0. Normally, freezing the counters
3472 * is done by writing MMCR0 (to set MMCR0[FC]) which
3473 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
3474 * we can also freeze the counters using MMCR2, by writing
3475 * 1s to all the counter freeze condition bits (there are
3476 * 9 bits each for 6 counters).
3478 li r3, -1 /* set all freeze bits */
3480 mfspr r10, SPRN_MMCR2
3481 mtspr SPRN_MMCR2, r3
3483 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3485 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
3486 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
3487 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
3488 mfspr r6, SPRN_MMCRA
3489 /* Clear MMCRA in order to disable SDAR updates */
3491 mtspr SPRN_MMCRA, r7
3493 cmpwi r8, 0 /* did they ask for PMU stuff to be saved? */
3495 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
3497 21: mfspr r5, SPRN_MMCR1
3500 std r4, VCPU_MMCR(r9)
3501 std r5, VCPU_MMCR + 8(r9)
3502 std r6, VCPU_MMCR + 16(r9)
3504 std r10, VCPU_MMCR + 24(r9)
3505 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3506 std r7, VCPU_SIAR(r9)
3507 std r8, VCPU_SDAR(r9)
3514 stw r3, VCPU_PMC(r9)
3515 stw r4, VCPU_PMC + 4(r9)
3516 stw r5, VCPU_PMC + 8(r9)
3517 stw r6, VCPU_PMC + 12(r9)
3518 stw r7, VCPU_PMC + 16(r9)
3519 stw r8, VCPU_PMC + 20(r9)
3522 std r5, VCPU_SIER(r9)
3523 BEGIN_FTR_SECTION_NESTED(96)
3524 mfspr r6, SPRN_SPMC1
3525 mfspr r7, SPRN_SPMC2
3526 mfspr r8, SPRN_MMCRS
3527 stw r6, VCPU_PMC + 24(r9)
3528 stw r7, VCPU_PMC + 28(r9)
3529 std r8, VCPU_MMCR + 32(r9)
3531 mtspr SPRN_MMCRS, r4
3532 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
3533 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3537 * This works around a hardware bug on POWER8E processors, where
3538 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
3539 * performance monitor interrupt. Instead, when we need to have
3540 * an interrupt pending, we have to arrange for a counter to overflow.
3544 mtspr SPRN_MMCR2, r3
3545 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
3546 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
3547 mtspr SPRN_MMCR0, r3
3554 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
3556 * Start timing an activity
3557 * r3 = pointer to time accumulation struct, r4 = vcpu
3560 ld r5, HSTATE_KVM_VCORE(r13)
3561 ld r6, VCORE_TB_OFFSET_APPL(r5)
3563 subf r5, r6, r5 /* subtract current timebase offset */
3564 std r3, VCPU_CUR_ACTIVITY(r4)
3565 std r5, VCPU_ACTIVITY_START(r4)
3569 * Accumulate time to one activity and start another.
3570 * r3 = pointer to new time accumulation struct, r4 = vcpu
3572 kvmhv_accumulate_time:
3573 ld r5, HSTATE_KVM_VCORE(r13)
3574 ld r8, VCORE_TB_OFFSET_APPL(r5)
3575 ld r5, VCPU_CUR_ACTIVITY(r4)
3576 ld r6, VCPU_ACTIVITY_START(r4)
3577 std r3, VCPU_CUR_ACTIVITY(r4)
3579 subf r7, r8, r7 /* subtract current timebase offset */
3580 std r7, VCPU_ACTIVITY_START(r4)
3584 ld r8, TAS_SEQCOUNT(r5)
3587 std r8, TAS_SEQCOUNT(r5)
3589 ld r7, TAS_TOTAL(r5)
3591 std r7, TAS_TOTAL(r5)
3597 3: std r3, TAS_MIN(r5)
3603 std r8, TAS_SEQCOUNT(r5)