1 #include <asm/processor.h>
2 #include <asm/ppc_asm.h>
4 #include <asm/asm-offsets.h>
5 #include <asm/cputable.h>
6 #include <asm/thread_info.h>
8 #include <asm/ptrace.h>
11 * Load state from memory into VMX registers including VSCR.
12 * Assumes the caller has enabled VMX in the MSR.
14 _GLOBAL(load_vr_state)
22 * Store VMX state into memory, including VSCR.
23 * Assumes the caller has enabled VMX in the MSR.
25 _GLOBAL(store_vr_state)
33 * Disable VMX for the task which had it previously,
34 * and save its vector registers in its thread_struct.
35 * Enables the VMX for use in the kernel on return.
36 * On SMP we know the VMX is free, since we give it up every
37 * switch (ie, no lazy save of the vector registers).
39 * Note that on 32-bit this can only use registers that will be
40 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
42 _GLOBAL(load_up_altivec)
43 mfmsr r5 /* grab the current MSR */
45 MTMSRD(r5) /* enable use of AltiVec now */
49 * While userspace in general ignores VRSAVE, glibc uses it as a boolean
50 * to optimise userspace context save/restore. Whenever we take an
51 * altivec unavailable exception we must set VRSAVE to something non
52 * zero. Set it to all 1s. See also the programming note in the ISA.
60 /* enable use of VMX after return */
62 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
65 ld r4,PACACURRENT(r13)
66 addi r5,r4,THREAD /* Get THREAD */
67 oris r12,r12,MSR_VEC@h
70 /* Don't care if r4 overflows, this is desired behaviour */
71 lbz r4,THREAD_LOAD_VEC(r5)
73 stb r4,THREAD_LOAD_VEC(r5)
74 addi r6,r5,THREAD_VRSTATE
77 stw r4,THREAD_USED_VR(r5)
81 /* restore registers and return */
86 * Save the vector registers to its thread_struct
89 addi r3,r3,THREAD /* want THREAD of task */
90 PPC_LL r7,THREAD_VRSAVEAREA(r3)
94 addi r7,r3,THREAD_VRSTATE
95 2: SAVE_32VRS(0,r4,r7)
104 #error This asm code isn't ready for 32-bit kernels
108 * load_up_vsx(unused, unused, tsk)
109 * Disable VSX for the task which had it previously,
110 * and save its vector registers in its thread_struct.
111 * Reuse the fp and vsx saves, but first check to see if they have
112 * been saved already.
115 /* Load FP and VSX registers if they haven't been done yet */
117 beql+ load_up_fpu /* skip if already loaded */
118 andis. r5,r12,MSR_VEC@h
119 beql+ load_up_altivec /* skip if already loaded */
121 ld r4,PACACURRENT(r13)
122 addi r4,r4,THREAD /* Get THREAD */
124 stw r6,THREAD_USED_VSR(r4) /* ... also set thread used vsr */
125 /* enable use of VSX after return */
126 oris r12,r12,MSR_VSX@h
128 b fast_exception_return
130 #endif /* CONFIG_VSX */
134 * The routines below are in assembler so we can closely control the
135 * usage of floating-point registers. These routines must be called
136 * with preempt disabled.
143 .long 0x3f800000 /* 1.0 in single-precision FP */
145 .long 0x3f000000 /* 0.5 in single-precision FP */
147 #define LDCONST(fr, name) \
156 .tc FD_3ff00000_0[TC],0x3ff0000000000000 /* 1.0 */
158 .tc FD_3fe00000_0[TC],0x3fe0000000000000 /* 0.5 */
160 #define LDCONST(fr, name) \
166 * Internal routine to enable floating point and set FPSCR to 0.
167 * Don't call it from C; it doesn't use the normal calling convention.
199 * Vector add, floating point.
216 * Vector subtract, floating point.
233 * Vector multiply and add, floating point.
245 fmadds fr0,fr0,fr2,fr1
253 * Vector negative multiply and subtract, floating point.
265 fnmsubs fr0,fr0,fr2,fr1
273 * Vector reciprocal estimate. We just compute 1.0/x.
274 * r3 -> destination, r4 -> source.
291 * Vector reciprocal square-root estimate, floating point.
292 * We use the frsqrte instruction for the initial estimate followed
293 * by 2 iterations of Newton-Raphson to get sufficient accuracy.
294 * r3 -> destination, r4 -> source.
309 frsqrte fr1,fr0 /* r = frsqrte(s) */
310 fmuls fr3,fr1,fr0 /* r * s */
311 fmuls fr2,fr1,fr5 /* r * 0.5 */
312 fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */
313 fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */
314 fmuls fr3,fr1,fr0 /* r * s */
315 fmuls fr2,fr1,fr5 /* r * 0.5 */
316 fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */
317 fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */