1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Copyright 2007-2010 Freescale Semiconductor, Inc.
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 * and Paul Mackerras (paulus@samba.org)
11 * This file handles the architecture-dependent parts of hardware exceptions
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/sched/debug.h>
17 #include <linux/kernel.h>
19 #include <linux/pkeys.h>
20 #include <linux/stddef.h>
21 #include <linux/unistd.h>
22 #include <linux/ptrace.h>
23 #include <linux/user.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/extable.h>
27 #include <linux/module.h> /* print_modules */
28 #include <linux/prctl.h>
29 #include <linux/delay.h>
30 #include <linux/kprobes.h>
31 #include <linux/kexec.h>
32 #include <linux/backlight.h>
33 #include <linux/bug.h>
34 #include <linux/kdebug.h>
35 #include <linux/ratelimit.h>
36 #include <linux/context_tracking.h>
37 #include <linux/smp.h>
38 #include <linux/console.h>
39 #include <linux/kmsg_dump.h>
41 #include <asm/emulated_ops.h>
42 #include <linux/uaccess.h>
43 #include <asm/debugfs.h>
45 #include <asm/machdep.h>
49 #ifdef CONFIG_PMAC_BACKLIGHT
50 #include <asm/backlight.h>
53 #include <asm/firmware.h>
54 #include <asm/processor.h>
57 #include <asm/kexec.h>
58 #include <asm/ppc-opcode.h>
60 #include <asm/fadump.h>
61 #include <asm/switch_to.h>
63 #include <asm/debug.h>
64 #include <asm/asm-prototypes.h>
66 #include <sysdev/fsl_pci.h>
67 #include <asm/kprobes.h>
68 #include <asm/stacktrace.h>
71 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
72 int (*__debugger)(struct pt_regs *regs) __read_mostly;
73 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
74 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
75 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
76 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
77 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
78 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
80 EXPORT_SYMBOL(__debugger);
81 EXPORT_SYMBOL(__debugger_ipi);
82 EXPORT_SYMBOL(__debugger_bpt);
83 EXPORT_SYMBOL(__debugger_sstep);
84 EXPORT_SYMBOL(__debugger_iabr_match);
85 EXPORT_SYMBOL(__debugger_break_match);
86 EXPORT_SYMBOL(__debugger_fault_handler);
89 /* Transactional Memory trap debug */
91 #define TM_DEBUG(x...) printk(KERN_INFO x)
93 #define TM_DEBUG(x...) do { } while(0)
96 static const char *signame(int signr)
99 case SIGBUS: return "bus error";
100 case SIGFPE: return "floating point exception";
101 case SIGILL: return "illegal instruction";
102 case SIGSEGV: return "segfault";
103 case SIGTRAP: return "unhandled trap";
106 return "unknown signal";
110 * Trap & Exception support
113 #ifdef CONFIG_PMAC_BACKLIGHT
114 static void pmac_backlight_unblank(void)
116 mutex_lock(&pmac_backlight_mutex);
117 if (pmac_backlight) {
118 struct backlight_properties *props;
120 props = &pmac_backlight->props;
121 props->brightness = props->max_brightness;
122 props->power = FB_BLANK_UNBLANK;
123 backlight_update_status(pmac_backlight);
125 mutex_unlock(&pmac_backlight_mutex);
128 static inline void pmac_backlight_unblank(void) { }
132 * If oops/die is expected to crash the machine, return true here.
134 * This should not be expected to be 100% accurate, there may be
135 * notifiers registered or other unexpected conditions that may bring
136 * down the kernel. Or if the current process in the kernel is holding
137 * locks or has other critical state, the kernel may become effectively
140 bool die_will_crash(void)
142 if (should_fadump_crash())
144 if (kexec_should_crash(current))
146 if (in_interrupt() || panic_on_oops ||
147 !current->pid || is_global_init(current))
153 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
154 static int die_owner = -1;
155 static unsigned int die_nest_count;
156 static int die_counter;
158 extern void panic_flush_kmsg_start(void)
161 * These are mostly taken from kernel/panic.c, but tries to do
162 * relatively minimal work. Don't use delay functions (TB may
163 * be broken), don't crash dump (need to set a firmware log),
164 * don't run notifiers. We do want to get some information to
171 extern void panic_flush_kmsg_end(void)
173 printk_safe_flush_on_panic();
174 kmsg_dump(KMSG_DUMP_PANIC);
177 console_flush_on_panic(CONSOLE_FLUSH_PENDING);
180 static unsigned long oops_begin(struct pt_regs *regs)
187 /* racy, but better than risking deadlock. */
188 raw_local_irq_save(flags);
189 cpu = smp_processor_id();
190 if (!arch_spin_trylock(&die_lock)) {
191 if (cpu == die_owner)
192 /* nested oops. should stop eventually */;
194 arch_spin_lock(&die_lock);
200 if (machine_is(powermac))
201 pmac_backlight_unblank();
204 NOKPROBE_SYMBOL(oops_begin);
206 static void oops_end(unsigned long flags, struct pt_regs *regs,
210 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
214 if (!die_nest_count) {
215 /* Nest count reaches zero, release the lock. */
217 arch_spin_unlock(&die_lock);
219 raw_local_irq_restore(flags);
222 * system_reset_excption handles debugger, crash dump, panic, for 0x100
224 if (TRAP(regs) == 0x100)
227 crash_fadump(regs, "die oops");
229 if (kexec_should_crash(current))
236 * While our oops output is serialised by a spinlock, output
237 * from panic() called below can race and corrupt it. If we
238 * know we are going to panic, delay for 1 second so we have a
239 * chance to get clean backtraces from all CPUs that are oopsing.
241 if (in_interrupt() || panic_on_oops || !current->pid ||
242 is_global_init(current)) {
243 mdelay(MSEC_PER_SEC);
247 panic("Fatal exception");
250 NOKPROBE_SYMBOL(oops_end);
252 static char *get_mmu_str(void)
254 if (early_radix_enabled())
256 if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE))
261 static int __die(const char *str, struct pt_regs *regs, long err)
263 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
265 printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n",
266 IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE",
267 PAGE_SIZE / 1024, get_mmu_str(),
268 IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "",
269 IS_ENABLED(CONFIG_SMP) ? " SMP" : "",
270 IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "",
271 debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "",
272 IS_ENABLED(CONFIG_NUMA) ? " NUMA" : "",
273 ppc_md.name ? ppc_md.name : "");
275 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
283 NOKPROBE_SYMBOL(__die);
285 void die(const char *str, struct pt_regs *regs, long err)
290 * system_reset_excption handles debugger, crash dump, panic, for 0x100
292 if (TRAP(regs) != 0x100) {
297 flags = oops_begin(regs);
298 if (__die(str, regs, err))
300 oops_end(flags, regs, err);
302 NOKPROBE_SYMBOL(die);
304 void user_single_step_report(struct pt_regs *regs)
306 force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)regs->nip);
309 static void show_signal_msg(int signr, struct pt_regs *regs, int code,
312 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
313 DEFAULT_RATELIMIT_BURST);
315 if (!show_unhandled_signals)
318 if (!unhandled_signal(current, signr))
321 if (!__ratelimit(&rs))
324 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x",
325 current->comm, current->pid, signame(signr), signr,
326 addr, regs->nip, regs->link, code);
328 print_vma_addr(KERN_CONT " in ", regs->nip);
332 show_user_instructions(regs);
335 static bool exception_common(int signr, struct pt_regs *regs, int code,
338 if (!user_mode(regs)) {
339 die("Exception in kernel mode", regs, signr);
343 show_signal_msg(signr, regs, code, addr);
345 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
348 current->thread.trap_nr = code;
353 void _exception_pkey(struct pt_regs *regs, unsigned long addr, int key)
355 if (!exception_common(SIGSEGV, regs, SEGV_PKUERR, addr))
358 force_sig_pkuerr((void __user *) addr, key);
361 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
363 if (!exception_common(signr, regs, code, addr))
366 force_sig_fault(signr, code, (void __user *)addr);
370 * The interrupt architecture has a quirk in that the HV interrupts excluding
371 * the NMIs (0x100 and 0x200) do not clear MSR[RI] at entry. The first thing
372 * that an interrupt handler must do is save off a GPR into a scratch register,
373 * and all interrupts on POWERNV (HV=1) use the HSPRG1 register as scratch.
374 * Therefore an NMI can clobber an HV interrupt's live HSPRG1 without noticing
375 * that it is non-reentrant, which leads to random data corruption.
377 * The solution is for NMI interrupts in HV mode to check if they originated
378 * from these critical HV interrupt regions. If so, then mark them not
381 * An alternative would be for HV NMIs to use SPRG for scratch to avoid the
382 * HSPRG1 clobber, however this would cause guest SPRG to be clobbered. Linux
383 * guests should always have MSR[RI]=0 when its scratch SPRG is in use, so
384 * that would work. However any other guest OS that may have the SPRG live
385 * and MSR[RI]=1 could encounter silent corruption.
387 * Builds that do not support KVM could take this second option to increase
388 * the recoverability of NMIs.
390 void hv_nmi_check_nonrecoverable(struct pt_regs *regs)
392 #ifdef CONFIG_PPC_POWERNV
393 unsigned long kbase = (unsigned long)_stext;
394 unsigned long nip = regs->nip;
396 if (!(regs->msr & MSR_RI))
398 if (!(regs->msr & MSR_HV))
400 if (regs->msr & MSR_PR)
404 * Now test if the interrupt has hit a range that may be using
405 * HSPRG1 without having RI=0 (i.e., an HSRR interrupt). The
406 * problem ranges all run un-relocated. Test real and virt modes
407 * at the same time by droping the high bit of the nip (virt mode
408 * entry points still have the +0x4000 offset).
410 nip &= ~0xc000000000000000ULL;
411 if ((nip >= 0x500 && nip < 0x600) || (nip >= 0x4500 && nip < 0x4600))
413 if ((nip >= 0x980 && nip < 0xa00) || (nip >= 0x4980 && nip < 0x4a00))
415 if ((nip >= 0xe00 && nip < 0xec0) || (nip >= 0x4e00 && nip < 0x4ec0))
417 if ((nip >= 0xf80 && nip < 0xfa0) || (nip >= 0x4f80 && nip < 0x4fa0))
420 /* Trampoline code runs un-relocated so subtract kbase. */
421 if (nip >= (unsigned long)(start_real_trampolines - kbase) &&
422 nip < (unsigned long)(end_real_trampolines - kbase))
424 if (nip >= (unsigned long)(start_virt_trampolines - kbase) &&
425 nip < (unsigned long)(end_virt_trampolines - kbase))
430 regs->msr &= ~MSR_RI;
434 void system_reset_exception(struct pt_regs *regs)
436 unsigned long hsrr0, hsrr1;
437 bool saved_hsrrs = false;
438 u8 ftrace_enabled = this_cpu_get_ftrace_enabled();
440 this_cpu_set_ftrace_enabled(0);
445 * System reset can interrupt code where HSRRs are live and MSR[RI]=1.
446 * The system reset interrupt itself may clobber HSRRs (e.g., to call
447 * OPAL), so save them here and restore them before returning.
449 * Machine checks don't need to save HSRRs, as the real mode handler
450 * is careful to avoid them, and the regular handler is not delivered
453 if (cpu_has_feature(CPU_FTR_HVMODE)) {
454 hsrr0 = mfspr(SPRN_HSRR0);
455 hsrr1 = mfspr(SPRN_HSRR1);
459 hv_nmi_check_nonrecoverable(regs);
461 __this_cpu_inc(irq_stat.sreset_irqs);
463 /* See if any machine dependent calls */
464 if (ppc_md.system_reset_exception) {
465 if (ppc_md.system_reset_exception(regs))
472 kmsg_dump(KMSG_DUMP_OOPS);
474 * A system reset is a request to dump, so we always send
475 * it through the crashdump code (if fadump or kdump are
478 crash_fadump(regs, "System Reset");
483 * We aren't the primary crash CPU. We need to send it
484 * to a holding pattern to avoid it ending up in the panic
487 crash_kexec_secondary(regs);
490 * No debugger or crash dump registered, print logs then
493 die("System Reset", regs, SIGABRT);
495 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */
496 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
497 nmi_panic(regs, "System Reset");
500 #ifdef CONFIG_PPC_BOOK3S_64
501 BUG_ON(get_paca()->in_nmi == 0);
502 if (get_paca()->in_nmi > 1)
503 die("Unrecoverable nested System Reset", regs, SIGABRT);
505 /* Must die if the interrupt is not recoverable */
506 if (!(regs->msr & MSR_RI))
507 die("Unrecoverable System Reset", regs, SIGABRT);
510 mtspr(SPRN_HSRR0, hsrr0);
511 mtspr(SPRN_HSRR1, hsrr1);
516 this_cpu_set_ftrace_enabled(ftrace_enabled);
518 /* What should we do here? We could issue a shutdown or hard reset. */
522 * I/O accesses can cause machine checks on powermacs.
523 * Check if the NIP corresponds to the address of a sync
524 * instruction for which there is an entry in the exception
528 static inline int check_io_access(struct pt_regs *regs)
531 unsigned long msr = regs->msr;
532 const struct exception_table_entry *entry;
533 unsigned int *nip = (unsigned int *)regs->nip;
535 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
536 && (entry = search_exception_tables(regs->nip)) != NULL) {
538 * Check that it's a sync instruction, or somewhere
539 * in the twi; isync; nop sequence that inb/inw/inl uses.
540 * As the address is in the exception table
541 * we should be able to read the instr there.
542 * For the debug message, we look at the preceding
545 if (*nip == PPC_INST_NOP)
547 else if (*nip == PPC_INST_ISYNC)
549 if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) {
553 rb = (*nip >> 11) & 0x1f;
554 printk(KERN_DEBUG "%s bad port %lx at %p\n",
555 (*nip & 0x100)? "OUT to": "IN from",
556 regs->gpr[rb] - _IO_BASE, nip);
558 regs->nip = extable_fixup(entry);
562 #endif /* CONFIG_PPC32 */
566 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
567 /* On 4xx, the reason for the machine check or program exception
569 #define get_reason(regs) ((regs)->dsisr)
570 #define REASON_FP ESR_FP
571 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
572 #define REASON_PRIVILEGED ESR_PPR
573 #define REASON_TRAP ESR_PTR
574 #define REASON_PREFIXED 0
575 #define REASON_BOUNDARY 0
577 /* single-step stuff */
578 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
579 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
580 #define clear_br_trace(regs) do {} while(0)
582 /* On non-4xx, the reason for the machine check or program
583 exception is in the MSR. */
584 #define get_reason(regs) ((regs)->msr)
585 #define REASON_TM SRR1_PROGTM
586 #define REASON_FP SRR1_PROGFPE
587 #define REASON_ILLEGAL SRR1_PROGILL
588 #define REASON_PRIVILEGED SRR1_PROGPRIV
589 #define REASON_TRAP SRR1_PROGTRAP
590 #define REASON_PREFIXED SRR1_PREFIXED
591 #define REASON_BOUNDARY SRR1_BOUNDARY
593 #define single_stepping(regs) ((regs)->msr & MSR_SE)
594 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
595 #define clear_br_trace(regs) ((regs)->msr &= ~MSR_BE)
598 #define inst_length(reason) (((reason) & REASON_PREFIXED) ? 8 : 4)
600 #if defined(CONFIG_E500)
601 int machine_check_e500mc(struct pt_regs *regs)
603 unsigned long mcsr = mfspr(SPRN_MCSR);
604 unsigned long pvr = mfspr(SPRN_PVR);
605 unsigned long reason = mcsr;
608 if (reason & MCSR_LD) {
609 recoverable = fsl_rio_mcheck_exception(regs);
610 if (recoverable == 1)
614 printk("Machine check in kernel mode.\n");
615 printk("Caused by (from MCSR=%lx): ", reason);
617 if (reason & MCSR_MCP)
618 pr_cont("Machine Check Signal\n");
620 if (reason & MCSR_ICPERR) {
621 pr_cont("Instruction Cache Parity Error\n");
624 * This is recoverable by invalidating the i-cache.
626 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
627 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
631 * This will generally be accompanied by an instruction
632 * fetch error report -- only treat MCSR_IF as fatal
633 * if it wasn't due to an L1 parity error.
638 if (reason & MCSR_DCPERR_MC) {
639 pr_cont("Data Cache Parity Error\n");
642 * In write shadow mode we auto-recover from the error, but it
643 * may still get logged and cause a machine check. We should
644 * only treat the non-write shadow case as non-recoverable.
646 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
647 * is not implemented but L1 data cache always runs in write
648 * shadow mode. Hence on data cache parity errors HW will
649 * automatically invalidate the L1 Data Cache.
651 if (PVR_VER(pvr) != PVR_VER_E6500) {
652 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
657 if (reason & MCSR_L2MMU_MHIT) {
658 pr_cont("Hit on multiple TLB entries\n");
662 if (reason & MCSR_NMI)
663 pr_cont("Non-maskable interrupt\n");
665 if (reason & MCSR_IF) {
666 pr_cont("Instruction Fetch Error Report\n");
670 if (reason & MCSR_LD) {
671 pr_cont("Load Error Report\n");
675 if (reason & MCSR_ST) {
676 pr_cont("Store Error Report\n");
680 if (reason & MCSR_LDG) {
681 pr_cont("Guarded Load Error Report\n");
685 if (reason & MCSR_TLBSYNC)
686 pr_cont("Simultaneous tlbsync operations\n");
688 if (reason & MCSR_BSL2_ERR) {
689 pr_cont("Level 2 Cache Error\n");
693 if (reason & MCSR_MAV) {
696 addr = mfspr(SPRN_MCAR);
697 addr |= (u64)mfspr(SPRN_MCARU) << 32;
699 pr_cont("Machine Check %s Address: %#llx\n",
700 reason & MCSR_MEA ? "Effective" : "Physical", addr);
704 mtspr(SPRN_MCSR, mcsr);
705 return mfspr(SPRN_MCSR) == 0 && recoverable;
708 int machine_check_e500(struct pt_regs *regs)
710 unsigned long reason = mfspr(SPRN_MCSR);
712 if (reason & MCSR_BUS_RBERR) {
713 if (fsl_rio_mcheck_exception(regs))
715 if (fsl_pci_mcheck_exception(regs))
719 printk("Machine check in kernel mode.\n");
720 printk("Caused by (from MCSR=%lx): ", reason);
722 if (reason & MCSR_MCP)
723 pr_cont("Machine Check Signal\n");
724 if (reason & MCSR_ICPERR)
725 pr_cont("Instruction Cache Parity Error\n");
726 if (reason & MCSR_DCP_PERR)
727 pr_cont("Data Cache Push Parity Error\n");
728 if (reason & MCSR_DCPERR)
729 pr_cont("Data Cache Parity Error\n");
730 if (reason & MCSR_BUS_IAERR)
731 pr_cont("Bus - Instruction Address Error\n");
732 if (reason & MCSR_BUS_RAERR)
733 pr_cont("Bus - Read Address Error\n");
734 if (reason & MCSR_BUS_WAERR)
735 pr_cont("Bus - Write Address Error\n");
736 if (reason & MCSR_BUS_IBERR)
737 pr_cont("Bus - Instruction Data Error\n");
738 if (reason & MCSR_BUS_RBERR)
739 pr_cont("Bus - Read Data Bus Error\n");
740 if (reason & MCSR_BUS_WBERR)
741 pr_cont("Bus - Write Data Bus Error\n");
742 if (reason & MCSR_BUS_IPERR)
743 pr_cont("Bus - Instruction Parity Error\n");
744 if (reason & MCSR_BUS_RPERR)
745 pr_cont("Bus - Read Parity Error\n");
750 int machine_check_generic(struct pt_regs *regs)
754 #elif defined(CONFIG_E200)
755 int machine_check_e200(struct pt_regs *regs)
757 unsigned long reason = mfspr(SPRN_MCSR);
759 printk("Machine check in kernel mode.\n");
760 printk("Caused by (from MCSR=%lx): ", reason);
762 if (reason & MCSR_MCP)
763 pr_cont("Machine Check Signal\n");
764 if (reason & MCSR_CP_PERR)
765 pr_cont("Cache Push Parity Error\n");
766 if (reason & MCSR_CPERR)
767 pr_cont("Cache Parity Error\n");
768 if (reason & MCSR_EXCP_ERR)
769 pr_cont("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
770 if (reason & MCSR_BUS_IRERR)
771 pr_cont("Bus - Read Bus Error on instruction fetch\n");
772 if (reason & MCSR_BUS_DRERR)
773 pr_cont("Bus - Read Bus Error on data load\n");
774 if (reason & MCSR_BUS_WRERR)
775 pr_cont("Bus - Write Bus Error on buffered store or cache line push\n");
779 #elif defined(CONFIG_PPC32)
780 int machine_check_generic(struct pt_regs *regs)
782 unsigned long reason = regs->msr;
784 printk("Machine check in kernel mode.\n");
785 printk("Caused by (from SRR1=%lx): ", reason);
786 switch (reason & 0x601F0000) {
788 pr_cont("Machine check signal\n");
791 case 0x140000: /* 7450 MSS error and TEA */
792 pr_cont("Transfer error ack signal\n");
795 pr_cont("Data parity error signal\n");
798 pr_cont("Address parity error signal\n");
801 pr_cont("L1 Data Cache error\n");
804 pr_cont("L1 Instruction Cache error\n");
807 pr_cont("L2 data cache parity error\n");
810 pr_cont("Unknown values in msr\n");
814 #endif /* everything else */
816 void machine_check_exception(struct pt_regs *regs)
821 * BOOK3S_64 does not call this handler as a non-maskable interrupt
822 * (it uses its own early real-mode handler to handle the MCE proper
823 * and then raises irq_work to call this handler when interrupts are
826 * This is silly. The BOOK3S_64 should just call a different function
827 * rather than expecting semantics to magically change. Something
828 * like 'non_nmi_machine_check_exception()', perhaps?
830 const bool nmi = !IS_ENABLED(CONFIG_PPC_BOOK3S_64);
832 if (nmi) nmi_enter();
834 __this_cpu_inc(irq_stat.mce_exceptions);
836 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
838 /* See if any machine dependent calls. In theory, we would want
839 * to call the CPU first, and call the ppc_md. one if the CPU
840 * one returns a positive number. However there is existing code
841 * that assumes the board gets a first chance, so let's keep it
842 * that way for now and fix things later. --BenH.
844 if (ppc_md.machine_check_exception)
845 recover = ppc_md.machine_check_exception(regs);
846 else if (cur_cpu_spec->machine_check)
847 recover = cur_cpu_spec->machine_check(regs);
852 if (debugger_fault_handler(regs))
855 if (check_io_access(regs))
860 die("Machine check", regs, SIGBUS);
862 /* Must die if the interrupt is not recoverable */
863 if (!(regs->msr & MSR_RI))
864 die("Unrecoverable Machine check", regs, SIGBUS);
872 void SMIException(struct pt_regs *regs)
874 die("System Management Interrupt", regs, SIGABRT);
878 static void p9_hmi_special_emu(struct pt_regs *regs)
880 unsigned int ra, rb, t, i, sel, instr, rc;
881 const void __user *addr;
882 u8 vbuf[16] __aligned(16), *vdst;
883 unsigned long ea, msr, msr_mask;
886 if (__get_user_inatomic(instr, (unsigned int __user *)regs->nip))
890 * lxvb16x opcode: 0x7c0006d8
891 * lxvd2x opcode: 0x7c000698
892 * lxvh8x opcode: 0x7c000658
893 * lxvw4x opcode: 0x7c000618
895 if ((instr & 0xfc00073e) != 0x7c000618) {
896 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx"
898 smp_processor_id(), current->comm, current->pid,
903 /* Grab vector registers into the task struct */
904 msr = regs->msr; /* Grab msr before we flush the bits */
905 flush_vsx_to_thread(current);
906 enable_kernel_altivec();
909 * Is userspace running with a different endian (this is rare but
912 swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
914 /* Decode the instruction */
915 ra = (instr >> 16) & 0x1f;
916 rb = (instr >> 11) & 0x1f;
917 t = (instr >> 21) & 0x1f;
919 vdst = (u8 *)¤t->thread.vr_state.vr[t];
921 vdst = (u8 *)¤t->thread.fp_state.fpr[t][0];
923 /* Grab the vector address */
924 ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0);
927 addr = (__force const void __user *)ea;
930 if (!access_ok(addr, 16)) {
931 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx"
932 " instr=%08x addr=%016lx\n",
933 smp_processor_id(), current->comm, current->pid,
934 regs->nip, instr, (unsigned long)addr);
938 /* Read the vector */
940 if ((unsigned long)addr & 0xfUL)
942 rc = __copy_from_user_inatomic(vbuf, addr, 16);
944 __get_user_atomic_128_aligned(vbuf, addr, rc);
946 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx"
947 " instr=%08x addr=%016lx\n",
948 smp_processor_id(), current->comm, current->pid,
949 regs->nip, instr, (unsigned long)addr);
953 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx"
954 " instr=%08x addr=%016lx\n",
955 smp_processor_id(), current->comm, current->pid, regs->nip,
956 instr, (unsigned long) addr);
958 /* Grab instruction "selector" */
959 sel = (instr >> 6) & 3;
962 * Check to make sure the facility is actually enabled. This
963 * could happen if we get a false positive hit.
965 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2
966 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3
969 if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */
971 if (!(msr & msr_mask)) {
972 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx"
973 " instr=%08x msr:%016lx\n",
974 smp_processor_id(), current->comm, current->pid,
975 regs->nip, instr, msr);
979 /* Do logging here before we modify sel based on endian */
982 PPC_WARN_EMULATED(lxvw4x, regs);
985 PPC_WARN_EMULATED(lxvh8x, regs);
988 PPC_WARN_EMULATED(lxvd2x, regs);
990 case 3: /* lxvb16x */
991 PPC_WARN_EMULATED(lxvb16x, regs);
995 #ifdef __LITTLE_ENDIAN__
997 * An LE kernel stores the vector in the task struct as an LE
998 * byte array (effectively swapping both the components and
999 * the content of the components). Those instructions expect
1000 * the components to remain in ascending address order, so we
1003 * If we are running a BE user space, the expectation is that
1004 * of a simple memcpy, so forcing the emulation to look like
1005 * a lxvb16x should do the trick.
1011 case 0: /* lxvw4x */
1012 for (i = 0; i < 4; i++)
1013 ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i];
1015 case 1: /* lxvh8x */
1016 for (i = 0; i < 8; i++)
1017 ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i];
1019 case 2: /* lxvd2x */
1020 for (i = 0; i < 2; i++)
1021 ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i];
1023 case 3: /* lxvb16x */
1024 for (i = 0; i < 16; i++)
1025 vdst[i] = vbuf[15-i];
1028 #else /* __LITTLE_ENDIAN__ */
1029 /* On a big endian kernel, a BE userspace only needs a memcpy */
1033 /* Otherwise, we need to swap the content of the components */
1035 case 0: /* lxvw4x */
1036 for (i = 0; i < 4; i++)
1037 ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]);
1039 case 1: /* lxvh8x */
1040 for (i = 0; i < 8; i++)
1041 ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]);
1043 case 2: /* lxvd2x */
1044 for (i = 0; i < 2; i++)
1045 ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]);
1047 case 3: /* lxvb16x */
1048 memcpy(vdst, vbuf, 16);
1051 #endif /* !__LITTLE_ENDIAN__ */
1053 /* Go to next instruction */
1056 #endif /* CONFIG_VSX */
1058 void handle_hmi_exception(struct pt_regs *regs)
1060 struct pt_regs *old_regs;
1062 old_regs = set_irq_regs(regs);
1066 /* Real mode flagged P9 special emu is needed */
1067 if (local_paca->hmi_p9_special_emu) {
1068 local_paca->hmi_p9_special_emu = 0;
1071 * We don't want to take page faults while doing the
1072 * emulation, we just replay the instruction if necessary.
1074 pagefault_disable();
1075 p9_hmi_special_emu(regs);
1078 #endif /* CONFIG_VSX */
1080 if (ppc_md.handle_hmi_exception)
1081 ppc_md.handle_hmi_exception(regs);
1084 set_irq_regs(old_regs);
1087 void unknown_exception(struct pt_regs *regs)
1089 enum ctx_state prev_state = exception_enter();
1091 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
1092 regs->nip, regs->msr, regs->trap);
1094 _exception(SIGTRAP, regs, TRAP_UNK, 0);
1096 exception_exit(prev_state);
1099 void instruction_breakpoint_exception(struct pt_regs *regs)
1101 enum ctx_state prev_state = exception_enter();
1103 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
1104 5, SIGTRAP) == NOTIFY_STOP)
1106 if (debugger_iabr_match(regs))
1108 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1111 exception_exit(prev_state);
1114 void RunModeException(struct pt_regs *regs)
1116 _exception(SIGTRAP, regs, TRAP_UNK, 0);
1119 void single_step_exception(struct pt_regs *regs)
1121 enum ctx_state prev_state = exception_enter();
1123 clear_single_step(regs);
1124 clear_br_trace(regs);
1126 if (kprobe_post_handler(regs))
1129 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1130 5, SIGTRAP) == NOTIFY_STOP)
1132 if (debugger_sstep(regs))
1135 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1138 exception_exit(prev_state);
1140 NOKPROBE_SYMBOL(single_step_exception);
1143 * After we have successfully emulated an instruction, we have to
1144 * check if the instruction was being single-stepped, and if so,
1145 * pretend we got a single-step exception. This was pointed out
1146 * by Kumar Gala. -- paulus
1148 static void emulate_single_step(struct pt_regs *regs)
1150 if (single_stepping(regs))
1151 single_step_exception(regs);
1154 static inline int __parse_fpscr(unsigned long fpscr)
1156 int ret = FPE_FLTUNK;
1158 /* Invalid operation */
1159 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
1163 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
1167 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
1170 /* Divide by zero */
1171 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
1174 /* Inexact result */
1175 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
1181 static void parse_fpe(struct pt_regs *regs)
1185 flush_fp_to_thread(current);
1187 #ifdef CONFIG_PPC_FPU_REGS
1188 code = __parse_fpscr(current->thread.fp_state.fpscr);
1191 _exception(SIGFPE, regs, code, regs->nip);
1195 * Illegal instruction emulation support. Originally written to
1196 * provide the PVR to user applications using the mfspr rd, PVR.
1197 * Return non-zero if we can't emulate, or -EFAULT if the associated
1198 * memory access caused an access fault. Return zero on success.
1200 * There are a couple of ways to do this, either "decode" the instruction
1201 * or directly match lots of bits. In this case, matching lots of
1202 * bits is faster and easier.
1205 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
1207 u8 rT = (instword >> 21) & 0x1f;
1208 u8 rA = (instword >> 16) & 0x1f;
1209 u8 NB_RB = (instword >> 11) & 0x1f;
1214 /* Early out if we are an invalid form of lswx */
1215 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
1216 if ((rT == rA) || (rT == NB_RB))
1219 EA = (rA == 0) ? 0 : regs->gpr[rA];
1221 switch (instword & PPC_INST_STRING_MASK) {
1223 case PPC_INST_STSWX:
1225 num_bytes = regs->xer & 0x7f;
1228 case PPC_INST_STSWI:
1229 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
1235 while (num_bytes != 0)
1238 u32 shift = 8 * (3 - (pos & 0x3));
1240 /* if process is 32-bit, clear upper 32 bits of EA */
1241 if ((regs->msr & MSR_64BIT) == 0)
1244 switch ((instword & PPC_INST_STRING_MASK)) {
1247 if (get_user(val, (u8 __user *)EA))
1249 /* first time updating this reg,
1253 regs->gpr[rT] |= val << shift;
1255 case PPC_INST_STSWI:
1256 case PPC_INST_STSWX:
1257 val = regs->gpr[rT] >> shift;
1258 if (put_user(val, (u8 __user *)EA))
1262 /* move EA to next address */
1266 /* manage our position within the register */
1277 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
1282 ra = (instword >> 16) & 0x1f;
1283 rs = (instword >> 21) & 0x1f;
1285 tmp = regs->gpr[rs];
1286 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
1287 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
1288 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1289 regs->gpr[ra] = tmp;
1294 static int emulate_isel(struct pt_regs *regs, u32 instword)
1296 u8 rT = (instword >> 21) & 0x1f;
1297 u8 rA = (instword >> 16) & 0x1f;
1298 u8 rB = (instword >> 11) & 0x1f;
1299 u8 BC = (instword >> 6) & 0x1f;
1303 tmp = (rA == 0) ? 0 : regs->gpr[rA];
1304 bit = (regs->ccr >> (31 - BC)) & 0x1;
1306 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
1311 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1312 static inline bool tm_abort_check(struct pt_regs *regs, int cause)
1314 /* If we're emulating a load/store in an active transaction, we cannot
1315 * emulate it as the kernel operates in transaction suspended context.
1316 * We need to abort the transaction. This creates a persistent TM
1317 * abort so tell the user what caused it with a new code.
1319 if (MSR_TM_TRANSACTIONAL(regs->msr)) {
1327 static inline bool tm_abort_check(struct pt_regs *regs, int reason)
1333 static int emulate_instruction(struct pt_regs *regs)
1338 if (!user_mode(regs))
1340 CHECK_FULL_REGS(regs);
1342 if (get_user(instword, (u32 __user *)(regs->nip)))
1345 /* Emulate the mfspr rD, PVR. */
1346 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
1347 PPC_WARN_EMULATED(mfpvr, regs);
1348 rd = (instword >> 21) & 0x1f;
1349 regs->gpr[rd] = mfspr(SPRN_PVR);
1353 /* Emulating the dcba insn is just a no-op. */
1354 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
1355 PPC_WARN_EMULATED(dcba, regs);
1359 /* Emulate the mcrxr insn. */
1360 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
1361 int shift = (instword >> 21) & 0x1c;
1362 unsigned long msk = 0xf0000000UL >> shift;
1364 PPC_WARN_EMULATED(mcrxr, regs);
1365 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
1366 regs->xer &= ~0xf0000000UL;
1370 /* Emulate load/store string insn. */
1371 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
1372 if (tm_abort_check(regs,
1373 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
1375 PPC_WARN_EMULATED(string, regs);
1376 return emulate_string_inst(regs, instword);
1379 /* Emulate the popcntb (Population Count Bytes) instruction. */
1380 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
1381 PPC_WARN_EMULATED(popcntb, regs);
1382 return emulate_popcntb_inst(regs, instword);
1385 /* Emulate isel (Integer Select) instruction */
1386 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
1387 PPC_WARN_EMULATED(isel, regs);
1388 return emulate_isel(regs, instword);
1391 /* Emulate sync instruction variants */
1392 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
1393 PPC_WARN_EMULATED(sync, regs);
1394 asm volatile("sync");
1399 /* Emulate the mfspr rD, DSCR. */
1400 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
1401 PPC_INST_MFSPR_DSCR_USER) ||
1402 ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
1403 PPC_INST_MFSPR_DSCR)) &&
1404 cpu_has_feature(CPU_FTR_DSCR)) {
1405 PPC_WARN_EMULATED(mfdscr, regs);
1406 rd = (instword >> 21) & 0x1f;
1407 regs->gpr[rd] = mfspr(SPRN_DSCR);
1410 /* Emulate the mtspr DSCR, rD. */
1411 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
1412 PPC_INST_MTSPR_DSCR_USER) ||
1413 ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
1414 PPC_INST_MTSPR_DSCR)) &&
1415 cpu_has_feature(CPU_FTR_DSCR)) {
1416 PPC_WARN_EMULATED(mtdscr, regs);
1417 rd = (instword >> 21) & 0x1f;
1418 current->thread.dscr = regs->gpr[rd];
1419 current->thread.dscr_inherit = 1;
1420 mtspr(SPRN_DSCR, current->thread.dscr);
1428 int is_valid_bugaddr(unsigned long addr)
1430 return is_kernel_addr(addr);
1433 #ifdef CONFIG_MATH_EMULATION
1434 static int emulate_math(struct pt_regs *regs)
1437 extern int do_mathemu(struct pt_regs *regs);
1439 ret = do_mathemu(regs);
1441 PPC_WARN_EMULATED(math, regs);
1445 emulate_single_step(regs);
1449 code = __parse_fpscr(current->thread.fp_state.fpscr);
1450 _exception(SIGFPE, regs, code, regs->nip);
1454 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1461 static inline int emulate_math(struct pt_regs *regs) { return -1; }
1464 void program_check_exception(struct pt_regs *regs)
1466 enum ctx_state prev_state = exception_enter();
1467 unsigned int reason = get_reason(regs);
1469 /* We can now get here via a FP Unavailable exception if the core
1470 * has no FPU, in that case the reason flags will be 0 */
1472 if (reason & REASON_FP) {
1473 /* IEEE FP exception */
1477 if (reason & REASON_TRAP) {
1478 unsigned long bugaddr;
1479 /* Debugger is first in line to stop recursive faults in
1480 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1481 if (debugger_bpt(regs))
1484 if (kprobe_handler(regs))
1487 /* trap exception */
1488 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1492 bugaddr = regs->nip;
1494 * Fixup bugaddr for BUG_ON() in real mode
1496 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR))
1497 bugaddr += PAGE_OFFSET;
1499 if (!(regs->msr & MSR_PR) && /* not user-mode */
1500 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) {
1504 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1507 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1508 if (reason & REASON_TM) {
1509 /* This is a TM "Bad Thing Exception" program check.
1511 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1512 * transition in TM states.
1513 * - A trechkpt is attempted when transactional.
1514 * - A treclaim is attempted when non transactional.
1515 * - A tend is illegally attempted.
1516 * - writing a TM SPR when transactional.
1518 * If usermode caused this, it's done something illegal and
1519 * gets a SIGILL slap on the wrist. We call it an illegal
1520 * operand to distinguish from the instruction just being bad
1521 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1522 * illegal /placement/ of a valid instruction.
1524 if (user_mode(regs)) {
1525 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1528 printk(KERN_EMERG "Unexpected TM Bad Thing exception "
1529 "at %lx (msr 0x%lx) tm_scratch=%llx\n",
1530 regs->nip, regs->msr, get_paca()->tm_scratch);
1531 die("Unrecoverable exception", regs, SIGABRT);
1537 * If we took the program check in the kernel skip down to sending a
1538 * SIGILL. The subsequent cases all relate to emulating instructions
1539 * which we should only do for userspace. We also do not want to enable
1540 * interrupts for kernel faults because that might lead to further
1541 * faults, and loose the context of the original exception.
1543 if (!user_mode(regs))
1546 /* We restore the interrupt state now */
1547 if (!arch_irq_disabled_regs(regs))
1550 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1551 * but there seems to be a hardware bug on the 405GP (RevD)
1552 * that means ESR is sometimes set incorrectly - either to
1553 * ESR_DST (!?) or 0. In the process of chasing this with the
1554 * hardware people - not sure if it can happen on any illegal
1555 * instruction or only on FP instructions, whether there is a
1556 * pattern to occurrences etc. -dgibson 31/Mar/2003
1558 if (!emulate_math(regs))
1561 /* Try to emulate it if we should. */
1562 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1563 switch (emulate_instruction(regs)) {
1566 emulate_single_step(regs);
1569 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1575 if (reason & REASON_PRIVILEGED)
1576 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1578 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1581 exception_exit(prev_state);
1583 NOKPROBE_SYMBOL(program_check_exception);
1586 * This occurs when running in hypervisor mode on POWER6 or later
1587 * and an illegal instruction is encountered.
1589 void emulation_assist_interrupt(struct pt_regs *regs)
1591 regs->msr |= REASON_ILLEGAL;
1592 program_check_exception(regs);
1594 NOKPROBE_SYMBOL(emulation_assist_interrupt);
1596 void alignment_exception(struct pt_regs *regs)
1598 enum ctx_state prev_state = exception_enter();
1599 int sig, code, fixed = 0;
1600 unsigned long reason;
1602 /* We restore the interrupt state now */
1603 if (!arch_irq_disabled_regs(regs))
1606 reason = get_reason(regs);
1608 if (reason & REASON_BOUNDARY) {
1614 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
1617 /* we don't implement logging of alignment exceptions */
1618 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1619 fixed = fix_alignment(regs);
1622 /* skip over emulated instruction */
1623 regs->nip += inst_length(reason);
1624 emulate_single_step(regs);
1628 /* Operand address was bad */
1629 if (fixed == -EFAULT) {
1637 if (user_mode(regs))
1638 _exception(sig, regs, code, regs->dar);
1640 bad_page_fault(regs, regs->dar, sig);
1643 exception_exit(prev_state);
1646 void StackOverflow(struct pt_regs *regs)
1648 pr_crit("Kernel stack overflow in process %s[%d], r1=%lx\n",
1649 current->comm, task_pid_nr(current), regs->gpr[1]);
1652 panic("kernel stack overflow");
1655 void stack_overflow_exception(struct pt_regs *regs)
1657 enum ctx_state prev_state = exception_enter();
1659 die("Kernel stack overflow", regs, SIGSEGV);
1661 exception_exit(prev_state);
1664 void kernel_fp_unavailable_exception(struct pt_regs *regs)
1666 enum ctx_state prev_state = exception_enter();
1668 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1669 "%lx at %lx\n", regs->trap, regs->nip);
1670 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1672 exception_exit(prev_state);
1675 void altivec_unavailable_exception(struct pt_regs *regs)
1677 enum ctx_state prev_state = exception_enter();
1679 if (user_mode(regs)) {
1680 /* A user program has executed an altivec instruction,
1681 but this kernel doesn't support altivec. */
1682 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1686 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1687 "%lx at %lx\n", regs->trap, regs->nip);
1688 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1691 exception_exit(prev_state);
1694 void vsx_unavailable_exception(struct pt_regs *regs)
1696 if (user_mode(regs)) {
1697 /* A user program has executed an vsx instruction,
1698 but this kernel doesn't support vsx. */
1699 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1703 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1704 "%lx at %lx\n", regs->trap, regs->nip);
1705 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1709 static void tm_unavailable(struct pt_regs *regs)
1711 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1712 if (user_mode(regs)) {
1713 current->thread.load_tm++;
1714 regs->msr |= MSR_TM;
1716 tm_restore_sprs(¤t->thread);
1720 pr_emerg("Unrecoverable TM Unavailable Exception "
1721 "%lx at %lx\n", regs->trap, regs->nip);
1722 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT);
1725 void facility_unavailable_exception(struct pt_regs *regs)
1727 static char *facility_strings[] = {
1728 [FSCR_FP_LG] = "FPU",
1729 [FSCR_VECVSX_LG] = "VMX/VSX",
1730 [FSCR_DSCR_LG] = "DSCR",
1731 [FSCR_PM_LG] = "PMU SPRs",
1732 [FSCR_BHRB_LG] = "BHRB",
1733 [FSCR_TM_LG] = "TM",
1734 [FSCR_EBB_LG] = "EBB",
1735 [FSCR_TAR_LG] = "TAR",
1736 [FSCR_MSGP_LG] = "MSGP",
1737 [FSCR_SCV_LG] = "SCV",
1738 [FSCR_PREFIX_LG] = "PREFIX",
1740 char *facility = "unknown";
1746 hv = (TRAP(regs) == 0xf80);
1748 value = mfspr(SPRN_HFSCR);
1750 value = mfspr(SPRN_FSCR);
1752 status = value >> 56;
1753 if ((hv || status >= 2) &&
1754 (status < ARRAY_SIZE(facility_strings)) &&
1755 facility_strings[status])
1756 facility = facility_strings[status];
1758 /* We should not have taken this interrupt in kernel */
1759 if (!user_mode(regs)) {
1760 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n",
1761 facility, status, regs->nip);
1762 die("Unexpected facility unavailable exception", regs, SIGABRT);
1765 /* We restore the interrupt state now */
1766 if (!arch_irq_disabled_regs(regs))
1769 if (status == FSCR_DSCR_LG) {
1771 * User is accessing the DSCR register using the problem
1772 * state only SPR number (0x03) either through a mfspr or
1773 * a mtspr instruction. If it is a write attempt through
1774 * a mtspr, then we set the inherit bit. This also allows
1775 * the user to write or read the register directly in the
1776 * future by setting via the FSCR DSCR bit. But in case it
1777 * is a read DSCR attempt through a mfspr instruction, we
1778 * just emulate the instruction instead. This code path will
1779 * always emulate all the mfspr instructions till the user
1780 * has attempted at least one mtspr instruction. This way it
1781 * preserves the same behaviour when the user is accessing
1782 * the DSCR through privilege level only SPR number (0x11)
1783 * which is emulated through illegal instruction exception.
1784 * We always leave HFSCR DSCR set.
1786 if (get_user(instword, (u32 __user *)(regs->nip))) {
1787 pr_err("Failed to fetch the user instruction\n");
1791 /* Write into DSCR (mtspr 0x03, RS) */
1792 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK)
1793 == PPC_INST_MTSPR_DSCR_USER) {
1794 rd = (instword >> 21) & 0x1f;
1795 current->thread.dscr = regs->gpr[rd];
1796 current->thread.dscr_inherit = 1;
1797 current->thread.fscr |= FSCR_DSCR;
1798 mtspr(SPRN_FSCR, current->thread.fscr);
1801 /* Read from DSCR (mfspr RT, 0x03) */
1802 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK)
1803 == PPC_INST_MFSPR_DSCR_USER) {
1804 if (emulate_instruction(regs)) {
1805 pr_err("DSCR based mfspr emulation failed\n");
1809 emulate_single_step(regs);
1814 if (status == FSCR_TM_LG) {
1816 * If we're here then the hardware is TM aware because it
1817 * generated an exception with FSRM_TM set.
1819 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
1820 * told us not to do TM, or the kernel is not built with TM
1823 * If both of those things are true, then userspace can spam the
1824 * console by triggering the printk() below just by continually
1825 * doing tbegin (or any TM instruction). So in that case just
1826 * send the process a SIGILL immediately.
1828 if (!cpu_has_feature(CPU_FTR_TM))
1831 tm_unavailable(regs);
1835 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1836 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr);
1839 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1843 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1845 void fp_unavailable_tm(struct pt_regs *regs)
1847 /* Note: This does not handle any kind of FP laziness. */
1849 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1850 regs->nip, regs->msr);
1852 /* We can only have got here if the task started using FP after
1853 * beginning the transaction. So, the transactional regs are just a
1854 * copy of the checkpointed ones. But, we still need to recheckpoint
1855 * as we're enabling FP for the process; it will return, abort the
1856 * transaction, and probably retry but now with FP enabled. So the
1857 * checkpointed FP registers need to be loaded.
1859 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1862 * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and
1863 * then it was overwrite by the thr->fp_state by tm_reclaim_thread().
1865 * At this point, ck{fp,vr}_state contains the exact values we want to
1869 /* Enable FP for the task: */
1870 current->thread.load_fp = 1;
1873 * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers.
1875 tm_recheckpoint(¤t->thread);
1878 void altivec_unavailable_tm(struct pt_regs *regs)
1880 /* See the comments in fp_unavailable_tm(). This function operates
1884 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1886 regs->nip, regs->msr);
1887 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1888 current->thread.load_vec = 1;
1889 tm_recheckpoint(¤t->thread);
1890 current->thread.used_vr = 1;
1893 void vsx_unavailable_tm(struct pt_regs *regs)
1895 /* See the comments in fp_unavailable_tm(). This works similarly,
1896 * though we're loading both FP and VEC registers in here.
1898 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1899 * regs. Either way, set MSR_VSX.
1902 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1904 regs->nip, regs->msr);
1906 current->thread.used_vsr = 1;
1908 /* This reclaims FP and/or VR regs if they're already enabled */
1909 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1911 current->thread.load_vec = 1;
1912 current->thread.load_fp = 1;
1914 tm_recheckpoint(¤t->thread);
1916 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1918 void performance_monitor_exception(struct pt_regs *regs)
1920 __this_cpu_inc(irq_stat.pmu_irqs);
1925 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1926 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1930 * Determine the cause of the debug event, clear the
1931 * event flags and send a trap to the handler. Torez
1933 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1934 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1935 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1936 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
1938 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status,
1941 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1942 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1943 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status,
1946 } else if (debug_status & DBSR_IAC1) {
1947 current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
1948 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1949 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status,
1952 } else if (debug_status & DBSR_IAC2) {
1953 current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
1954 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status,
1957 } else if (debug_status & DBSR_IAC3) {
1958 current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
1959 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1960 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status,
1963 } else if (debug_status & DBSR_IAC4) {
1964 current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
1965 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status,
1970 * At the point this routine was called, the MSR(DE) was turned off.
1971 * Check all other debug flags and see if that bit needs to be turned
1974 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1975 current->thread.debug.dbcr1))
1976 regs->msr |= MSR_DE;
1978 /* Make sure the IDM flag is off */
1979 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1982 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
1985 void DebugException(struct pt_regs *regs, unsigned long debug_status)
1987 current->thread.debug.dbsr = debug_status;
1989 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1990 * on server, it stops on the target of the branch. In order to simulate
1991 * the server behaviour, we thus restart right away with a single step
1992 * instead of stopping here when hitting a BT
1994 if (debug_status & DBSR_BT) {
1995 regs->msr &= ~MSR_DE;
1998 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1999 /* Clear the BT event */
2000 mtspr(SPRN_DBSR, DBSR_BT);
2002 /* Do the single step trick only when coming from userspace */
2003 if (user_mode(regs)) {
2004 current->thread.debug.dbcr0 &= ~DBCR0_BT;
2005 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
2006 regs->msr |= MSR_DE;
2010 if (kprobe_post_handler(regs))
2013 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
2014 5, SIGTRAP) == NOTIFY_STOP) {
2017 if (debugger_sstep(regs))
2019 } else if (debug_status & DBSR_IC) { /* Instruction complete */
2020 regs->msr &= ~MSR_DE;
2022 /* Disable instruction completion */
2023 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
2024 /* Clear the instruction completion event */
2025 mtspr(SPRN_DBSR, DBSR_IC);
2027 if (kprobe_post_handler(regs))
2030 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
2031 5, SIGTRAP) == NOTIFY_STOP) {
2035 if (debugger_sstep(regs))
2038 if (user_mode(regs)) {
2039 current->thread.debug.dbcr0 &= ~DBCR0_IC;
2040 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
2041 current->thread.debug.dbcr1))
2042 regs->msr |= MSR_DE;
2044 /* Make sure the IDM bit is off */
2045 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
2048 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
2050 handle_debug(regs, debug_status);
2052 NOKPROBE_SYMBOL(DebugException);
2053 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2055 #ifdef CONFIG_ALTIVEC
2056 void altivec_assist_exception(struct pt_regs *regs)
2060 if (!user_mode(regs)) {
2061 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
2062 " at %lx\n", regs->nip);
2063 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
2066 flush_altivec_to_thread(current);
2068 PPC_WARN_EMULATED(altivec, regs);
2069 err = emulate_altivec(regs);
2071 regs->nip += 4; /* skip emulated instruction */
2072 emulate_single_step(regs);
2076 if (err == -EFAULT) {
2077 /* got an error reading the instruction */
2078 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2080 /* didn't recognize the instruction */
2081 /* XXX quick hack for now: set the non-Java bit in the VSCR */
2082 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
2083 "in %s at %lx\n", current->comm, regs->nip);
2084 current->thread.vr_state.vscr.u[3] |= 0x10000;
2087 #endif /* CONFIG_ALTIVEC */
2089 #ifdef CONFIG_FSL_BOOKE
2090 void CacheLockingException(struct pt_regs *regs, unsigned long address,
2091 unsigned long error_code)
2093 /* We treat cache locking instructions from the user
2094 * as priv ops, in the future we could try to do
2097 if (error_code & (ESR_DLK|ESR_ILK))
2098 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
2101 #endif /* CONFIG_FSL_BOOKE */
2104 void SPEFloatingPointException(struct pt_regs *regs)
2106 extern int do_spe_mathemu(struct pt_regs *regs);
2107 unsigned long spefscr;
2109 int code = FPE_FLTUNK;
2112 /* We restore the interrupt state now */
2113 if (!arch_irq_disabled_regs(regs))
2116 flush_spe_to_thread(current);
2118 spefscr = current->thread.spefscr;
2119 fpexc_mode = current->thread.fpexc_mode;
2121 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
2124 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
2127 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
2129 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
2132 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
2135 err = do_spe_mathemu(regs);
2137 regs->nip += 4; /* skip emulated instruction */
2138 emulate_single_step(regs);
2142 if (err == -EFAULT) {
2143 /* got an error reading the instruction */
2144 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2145 } else if (err == -EINVAL) {
2146 /* didn't recognize the instruction */
2147 printk(KERN_ERR "unrecognized spe instruction "
2148 "in %s at %lx\n", current->comm, regs->nip);
2150 _exception(SIGFPE, regs, code, regs->nip);
2156 void SPEFloatingPointRoundException(struct pt_regs *regs)
2158 extern int speround_handler(struct pt_regs *regs);
2161 /* We restore the interrupt state now */
2162 if (!arch_irq_disabled_regs(regs))
2166 if (regs->msr & MSR_SPE)
2167 giveup_spe(current);
2171 err = speround_handler(regs);
2173 regs->nip += 4; /* skip emulated instruction */
2174 emulate_single_step(regs);
2178 if (err == -EFAULT) {
2179 /* got an error reading the instruction */
2180 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2181 } else if (err == -EINVAL) {
2182 /* didn't recognize the instruction */
2183 printk(KERN_ERR "unrecognized spe instruction "
2184 "in %s at %lx\n", current->comm, regs->nip);
2186 _exception(SIGFPE, regs, FPE_FLTUNK, regs->nip);
2193 * We enter here if we get an unrecoverable exception, that is, one
2194 * that happened at a point where the RI (recoverable interrupt) bit
2195 * in the MSR is 0. This indicates that SRR0/1 are live, and that
2196 * we therefore lost state by taking this exception.
2198 void unrecoverable_exception(struct pt_regs *regs)
2200 pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n",
2201 regs->trap, regs->nip, regs->msr);
2202 die("Unrecoverable exception", regs, SIGABRT);
2204 NOKPROBE_SYMBOL(unrecoverable_exception);
2206 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
2208 * Default handler for a Watchdog exception,
2209 * spins until a reboot occurs
2211 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
2213 /* Generic WatchdogHandler, implement your own */
2214 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
2218 void WatchdogException(struct pt_regs *regs)
2220 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
2221 WatchdogHandler(regs);
2226 * We enter here if we discover during exception entry that we are
2227 * running in supervisor mode with a userspace value in the stack pointer.
2229 void kernel_bad_stack(struct pt_regs *regs)
2231 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
2232 regs->gpr[1], regs->nip);
2233 die("Bad kernel stack pointer", regs, SIGABRT);
2235 NOKPROBE_SYMBOL(kernel_bad_stack);
2237 void __init trap_init(void)
2242 #ifdef CONFIG_PPC_EMULATED_STATS
2244 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
2246 struct ppc_emulated ppc_emulated = {
2247 #ifdef CONFIG_ALTIVEC
2248 WARN_EMULATED_SETUP(altivec),
2250 WARN_EMULATED_SETUP(dcba),
2251 WARN_EMULATED_SETUP(dcbz),
2252 WARN_EMULATED_SETUP(fp_pair),
2253 WARN_EMULATED_SETUP(isel),
2254 WARN_EMULATED_SETUP(mcrxr),
2255 WARN_EMULATED_SETUP(mfpvr),
2256 WARN_EMULATED_SETUP(multiple),
2257 WARN_EMULATED_SETUP(popcntb),
2258 WARN_EMULATED_SETUP(spe),
2259 WARN_EMULATED_SETUP(string),
2260 WARN_EMULATED_SETUP(sync),
2261 WARN_EMULATED_SETUP(unaligned),
2262 #ifdef CONFIG_MATH_EMULATION
2263 WARN_EMULATED_SETUP(math),
2266 WARN_EMULATED_SETUP(vsx),
2269 WARN_EMULATED_SETUP(mfdscr),
2270 WARN_EMULATED_SETUP(mtdscr),
2271 WARN_EMULATED_SETUP(lq_stq),
2272 WARN_EMULATED_SETUP(lxvw4x),
2273 WARN_EMULATED_SETUP(lxvh8x),
2274 WARN_EMULATED_SETUP(lxvd2x),
2275 WARN_EMULATED_SETUP(lxvb16x),
2279 u32 ppc_warn_emulated;
2281 void ppc_warn_emulated_print(const char *type)
2283 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
2287 static int __init ppc_warn_emulated_init(void)
2291 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
2293 dir = debugfs_create_dir("emulated_instructions",
2294 powerpc_debugfs_root);
2296 debugfs_create_u32("do_warn", 0644, dir, &ppc_warn_emulated);
2298 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++)
2299 debugfs_create_u32(entries[i].name, 0644, dir,
2300 (u32 *)&entries[i].val.counter);
2305 device_initcall(ppc_warn_emulated_init);
2307 #endif /* CONFIG_PPC_EMULATED_STATS */