1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great
6 * deal of code from the sparc and intel versions.
8 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
10 * PowerPC-64 Support added by Dave Engebretsen, Peter Bergner, and
11 * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/sched/mm.h>
19 #include <linux/sched/task_stack.h>
20 #include <linux/sched/topology.h>
21 #include <linux/smp.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/init.h>
25 #include <linux/spinlock.h>
26 #include <linux/cache.h>
27 #include <linux/err.h>
28 #include <linux/device.h>
29 #include <linux/cpu.h>
30 #include <linux/notifier.h>
31 #include <linux/topology.h>
32 #include <linux/profile.h>
33 #include <linux/processor.h>
34 #include <linux/random.h>
35 #include <linux/stackprotector.h>
36 #include <linux/pgtable.h>
37 #include <linux/clockchips.h>
38 #include <linux/kexec.h>
40 #include <asm/ptrace.h>
41 #include <linux/atomic.h>
43 #include <asm/hw_irq.h>
44 #include <asm/kvm_ppc.h>
45 #include <asm/dbell.h>
49 #include <asm/machdep.h>
50 #include <asm/mmu_context.h>
51 #include <asm/cputhreads.h>
52 #include <asm/cputable.h>
54 #include <asm/vdso_datapage.h>
59 #include <asm/debug.h>
60 #include <asm/cpu_has_feature.h>
61 #include <asm/ftrace.h>
63 #include <asm/fadump.h>
65 #include <trace/events/ipi.h>
69 #define DBG(fmt...) udbg_printf(fmt)
74 #ifdef CONFIG_HOTPLUG_CPU
75 /* State of each CPU during hotplug phases */
76 static DEFINE_PER_CPU(int, cpu_state) = { 0 };
79 struct task_struct *secondary_current;
80 bool has_big_cores __ro_after_init;
81 bool coregroup_enabled __ro_after_init;
82 bool thread_group_shares_l2 __ro_after_init;
83 bool thread_group_shares_l3 __ro_after_init;
85 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
86 DEFINE_PER_CPU(cpumask_var_t, cpu_smallcore_map);
87 DEFINE_PER_CPU(cpumask_var_t, cpu_l2_cache_map);
88 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
89 static DEFINE_PER_CPU(cpumask_var_t, cpu_coregroup_map);
91 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
92 EXPORT_PER_CPU_SYMBOL(cpu_l2_cache_map);
93 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
94 EXPORT_SYMBOL_GPL(has_big_cores);
96 #define MAX_THREAD_LIST_SIZE 8
97 #define THREAD_GROUP_SHARE_L1 1
98 #define THREAD_GROUP_SHARE_L2_L3 2
99 struct thread_groups {
100 unsigned int property;
101 unsigned int nr_groups;
102 unsigned int threads_per_group;
103 unsigned int thread_list[MAX_THREAD_LIST_SIZE];
106 /* Maximum number of properties that groups of threads within a core can share */
107 #define MAX_THREAD_GROUP_PROPERTIES 2
109 struct thread_groups_list {
110 unsigned int nr_properties;
111 struct thread_groups property_tgs[MAX_THREAD_GROUP_PROPERTIES];
114 static struct thread_groups_list tgl[NR_CPUS] __initdata;
116 * On big-cores system, thread_group_l1_cache_map for each CPU corresponds to
117 * the set its siblings that share the L1-cache.
119 DEFINE_PER_CPU(cpumask_var_t, thread_group_l1_cache_map);
122 * On some big-cores system, thread_group_l2_cache_map for each CPU
123 * corresponds to the set its siblings within the core that share the
126 DEFINE_PER_CPU(cpumask_var_t, thread_group_l2_cache_map);
129 * On P10, thread_group_l3_cache_map for each CPU is equal to the
130 * thread_group_l2_cache_map
132 DEFINE_PER_CPU(cpumask_var_t, thread_group_l3_cache_map);
134 /* SMP operations for this machine */
135 struct smp_ops_t *smp_ops;
137 /* Can't be static due to PowerMac hackery */
138 volatile unsigned int cpu_callin_map[NR_CPUS];
140 int smt_enabled_at_boot = 1;
143 * Returns 1 if the specified cpu should be brought up during boot.
144 * Used to inhibit booting threads if they've been disabled or
145 * limited on the command line
147 int smp_generic_cpu_bootable(unsigned int nr)
149 /* Special case - we inhibit secondary thread startup
150 * during boot if the user requests it.
152 if (system_state < SYSTEM_RUNNING && cpu_has_feature(CPU_FTR_SMT)) {
153 if (!smt_enabled_at_boot && cpu_thread_in_core(nr) != 0)
155 if (smt_enabled_at_boot
156 && cpu_thread_in_core(nr) >= smt_enabled_at_boot)
165 int smp_generic_kick_cpu(int nr)
167 if (nr < 0 || nr >= nr_cpu_ids)
171 * The processor is currently spinning, waiting for the
172 * cpu_start field to become non-zero After we set cpu_start,
173 * the processor will continue on to secondary_start
175 if (!paca_ptrs[nr]->cpu_start) {
176 paca_ptrs[nr]->cpu_start = 1;
181 #ifdef CONFIG_HOTPLUG_CPU
183 * Ok it's not there, so it might be soft-unplugged, let's
184 * try to bring it back
186 generic_set_cpu_up(nr);
188 smp_send_reschedule(nr);
189 #endif /* CONFIG_HOTPLUG_CPU */
193 #endif /* CONFIG_PPC64 */
195 static irqreturn_t call_function_action(int irq, void *data)
197 generic_smp_call_function_interrupt();
201 static irqreturn_t reschedule_action(int irq, void *data)
207 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
208 static irqreturn_t tick_broadcast_ipi_action(int irq, void *data)
210 timer_broadcast_interrupt();
215 #ifdef CONFIG_NMI_IPI
216 static irqreturn_t nmi_ipi_action(int irq, void *data)
218 smp_handle_nmi_ipi(get_irq_regs());
223 static irq_handler_t smp_ipi_action[] = {
224 [PPC_MSG_CALL_FUNCTION] = call_function_action,
225 [PPC_MSG_RESCHEDULE] = reschedule_action,
226 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
227 [PPC_MSG_TICK_BROADCAST] = tick_broadcast_ipi_action,
229 #ifdef CONFIG_NMI_IPI
230 [PPC_MSG_NMI_IPI] = nmi_ipi_action,
235 * The NMI IPI is a fallback and not truly non-maskable. It is simpler
236 * than going through the call function infrastructure, and strongly
237 * serialized, so it is more appropriate for debugging.
239 const char *smp_ipi_name[] = {
240 [PPC_MSG_CALL_FUNCTION] = "ipi call function",
241 [PPC_MSG_RESCHEDULE] = "ipi reschedule",
242 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
243 [PPC_MSG_TICK_BROADCAST] = "ipi tick-broadcast",
245 #ifdef CONFIG_NMI_IPI
246 [PPC_MSG_NMI_IPI] = "nmi ipi",
250 /* optional function to request ipi, for controllers with >= 4 ipis */
251 int smp_request_message_ipi(int virq, int msg)
255 if (msg < 0 || msg > PPC_MSG_NMI_IPI)
257 #ifndef CONFIG_NMI_IPI
258 if (msg == PPC_MSG_NMI_IPI)
262 err = request_irq(virq, smp_ipi_action[msg],
263 IRQF_PERCPU | IRQF_NO_THREAD | IRQF_NO_SUSPEND,
264 smp_ipi_name[msg], NULL);
265 WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n",
266 virq, smp_ipi_name[msg], err);
271 #ifdef CONFIG_PPC_SMP_MUXED_IPI
272 struct cpu_messages {
273 long messages; /* current messages */
275 static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_messages, ipi_message);
277 void smp_muxed_ipi_set_message(int cpu, int msg)
279 struct cpu_messages *info = &per_cpu(ipi_message, cpu);
280 char *message = (char *)&info->messages;
283 * Order previous accesses before accesses in the IPI handler.
286 WRITE_ONCE(message[msg], 1);
289 void smp_muxed_ipi_message_pass(int cpu, int msg)
291 smp_muxed_ipi_set_message(cpu, msg);
294 * cause_ipi functions are required to include a full barrier
295 * before doing whatever causes the IPI.
297 smp_ops->cause_ipi(cpu);
300 #ifdef __BIG_ENDIAN__
301 #define IPI_MESSAGE(A) (1uL << ((BITS_PER_LONG - 8) - 8 * (A)))
303 #define IPI_MESSAGE(A) (1uL << (8 * (A)))
306 irqreturn_t smp_ipi_demux(void)
308 mb(); /* order any irq clear */
310 return smp_ipi_demux_relaxed();
313 /* sync-free variant. Callers should ensure synchronization */
314 irqreturn_t smp_ipi_demux_relaxed(void)
316 struct cpu_messages *info;
319 info = this_cpu_ptr(&ipi_message);
321 all = xchg(&info->messages, 0);
322 #if defined(CONFIG_KVM_XICS) && defined(CONFIG_KVM_BOOK3S_HV_POSSIBLE)
324 * Must check for PPC_MSG_RM_HOST_ACTION messages
325 * before PPC_MSG_CALL_FUNCTION messages because when
326 * a VM is destroyed, we call kick_all_cpus_sync()
327 * to ensure that any pending PPC_MSG_RM_HOST_ACTION
328 * messages have completed before we free any VCPUs.
330 if (all & IPI_MESSAGE(PPC_MSG_RM_HOST_ACTION))
331 kvmppc_xics_ipi_action();
333 if (all & IPI_MESSAGE(PPC_MSG_CALL_FUNCTION))
334 generic_smp_call_function_interrupt();
335 if (all & IPI_MESSAGE(PPC_MSG_RESCHEDULE))
337 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
338 if (all & IPI_MESSAGE(PPC_MSG_TICK_BROADCAST))
339 timer_broadcast_interrupt();
341 #ifdef CONFIG_NMI_IPI
342 if (all & IPI_MESSAGE(PPC_MSG_NMI_IPI))
343 nmi_ipi_action(0, NULL);
345 } while (READ_ONCE(info->messages));
349 #endif /* CONFIG_PPC_SMP_MUXED_IPI */
351 static inline void do_message_pass(int cpu, int msg)
353 if (smp_ops->message_pass)
354 smp_ops->message_pass(cpu, msg);
355 #ifdef CONFIG_PPC_SMP_MUXED_IPI
357 smp_muxed_ipi_message_pass(cpu, msg);
361 void arch_smp_send_reschedule(int cpu)
364 do_message_pass(cpu, PPC_MSG_RESCHEDULE);
366 EXPORT_SYMBOL_GPL(arch_smp_send_reschedule);
368 void arch_send_call_function_single_ipi(int cpu)
370 do_message_pass(cpu, PPC_MSG_CALL_FUNCTION);
373 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
377 for_each_cpu(cpu, mask)
378 do_message_pass(cpu, PPC_MSG_CALL_FUNCTION);
381 #ifdef CONFIG_NMI_IPI
386 * NMI IPIs may not be recoverable, so should not be used as ongoing part of
387 * a running system. They can be used for crash, debug, halt/reboot, etc.
389 * The IPI call waits with interrupts disabled until all targets enter the
390 * NMI handler, then returns. Subsequent IPIs can be issued before targets
391 * have returned from their handlers, so there is no guarantee about
392 * concurrency or re-entrancy.
394 * A new NMI can be issued before all targets exit the handler.
396 * The IPI call may time out without all targets entering the NMI handler.
397 * In that case, there is some logic to recover (and ignore subsequent
398 * NMI interrupts that may eventually be raised), but the platform interrupt
399 * handler may not be able to distinguish this from other exception causes,
400 * which may cause a crash.
403 static atomic_t __nmi_ipi_lock = ATOMIC_INIT(0);
404 static struct cpumask nmi_ipi_pending_mask;
405 static bool nmi_ipi_busy = false;
406 static void (*nmi_ipi_function)(struct pt_regs *) = NULL;
408 noinstr static void nmi_ipi_lock_start(unsigned long *flags)
410 raw_local_irq_save(*flags);
412 while (raw_atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1) {
413 raw_local_irq_restore(*flags);
414 spin_until_cond(raw_atomic_read(&__nmi_ipi_lock) == 0);
415 raw_local_irq_save(*flags);
420 noinstr static void nmi_ipi_lock(void)
422 while (raw_atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1)
423 spin_until_cond(raw_atomic_read(&__nmi_ipi_lock) == 0);
426 noinstr static void nmi_ipi_unlock(void)
429 WARN_ON(raw_atomic_read(&__nmi_ipi_lock) != 1);
430 raw_atomic_set(&__nmi_ipi_lock, 0);
433 noinstr static void nmi_ipi_unlock_end(unsigned long *flags)
436 raw_local_irq_restore(*flags);
440 * Platform NMI handler calls this to ack
442 noinstr int smp_handle_nmi_ipi(struct pt_regs *regs)
444 void (*fn)(struct pt_regs *) = NULL;
446 int me = raw_smp_processor_id();
450 * Unexpected NMIs are possible here because the interrupt may not
451 * be able to distinguish NMI IPIs from other types of NMIs, or
452 * because the caller may have timed out.
454 nmi_ipi_lock_start(&flags);
455 if (cpumask_test_cpu(me, &nmi_ipi_pending_mask)) {
456 cpumask_clear_cpu(me, &nmi_ipi_pending_mask);
457 fn = READ_ONCE(nmi_ipi_function);
461 nmi_ipi_unlock_end(&flags);
469 static void do_smp_send_nmi_ipi(int cpu, bool safe)
471 if (!safe && smp_ops->cause_nmi_ipi && smp_ops->cause_nmi_ipi(cpu))
475 do_message_pass(cpu, PPC_MSG_NMI_IPI);
479 for_each_online_cpu(c) {
480 if (c == raw_smp_processor_id())
482 do_message_pass(c, PPC_MSG_NMI_IPI);
488 * - cpu is the target CPU (must not be this CPU), or NMI_IPI_ALL_OTHERS.
489 * - fn is the target callback function.
490 * - delay_us > 0 is the delay before giving up waiting for targets to
491 * begin executing the handler, == 0 specifies indefinite delay.
493 static int __smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *),
494 u64 delay_us, bool safe)
497 int me = raw_smp_processor_id();
501 BUG_ON(cpu < 0 && cpu != NMI_IPI_ALL_OTHERS);
503 if (unlikely(!smp_ops))
506 nmi_ipi_lock_start(&flags);
507 while (nmi_ipi_busy) {
508 nmi_ipi_unlock_end(&flags);
509 spin_until_cond(!nmi_ipi_busy);
510 nmi_ipi_lock_start(&flags);
513 nmi_ipi_function = fn;
515 WARN_ON_ONCE(!cpumask_empty(&nmi_ipi_pending_mask));
519 cpumask_copy(&nmi_ipi_pending_mask, cpu_online_mask);
520 cpumask_clear_cpu(me, &nmi_ipi_pending_mask);
522 cpumask_set_cpu(cpu, &nmi_ipi_pending_mask);
527 /* Interrupts remain hard disabled */
529 do_smp_send_nmi_ipi(cpu, safe);
532 /* nmi_ipi_busy is set here, so unlock/lock is okay */
533 while (!cpumask_empty(&nmi_ipi_pending_mask)) {
544 if (!cpumask_empty(&nmi_ipi_pending_mask)) {
545 /* Timeout waiting for CPUs to call smp_handle_nmi_ipi */
547 cpumask_clear(&nmi_ipi_pending_mask);
550 nmi_ipi_function = NULL;
551 nmi_ipi_busy = false;
553 nmi_ipi_unlock_end(&flags);
558 int smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us)
560 return __smp_send_nmi_ipi(cpu, fn, delay_us, false);
563 int smp_send_safe_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us)
565 return __smp_send_nmi_ipi(cpu, fn, delay_us, true);
567 #endif /* CONFIG_NMI_IPI */
569 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
570 void tick_broadcast(const struct cpumask *mask)
574 for_each_cpu(cpu, mask)
575 do_message_pass(cpu, PPC_MSG_TICK_BROADCAST);
579 #ifdef CONFIG_DEBUGGER
580 static void debugger_ipi_callback(struct pt_regs *regs)
585 void smp_send_debugger_break(void)
587 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, debugger_ipi_callback, 1000000);
591 #ifdef CONFIG_KEXEC_CORE
592 void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *))
596 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, crash_ipi_callback, 1000000);
597 if (kdump_in_progress() && crash_wake_offline) {
598 for_each_present_cpu(cpu) {
602 * crash_ipi_callback will wait for
603 * all cpus, including offline CPUs.
604 * We don't care about nmi_ipi_function.
605 * Offline cpus will jump straight into
606 * crash_ipi_callback, we can skip the
607 * entire NMI dance and waiting for
608 * cpus to clear pending mask, etc.
610 do_smp_send_nmi_ipi(cpu, false);
616 void crash_smp_send_stop(void)
618 static bool stopped = false;
621 * In case of fadump, register data for all CPUs is captured by f/w
622 * on ibm,os-term rtas call. Skip IPI callbacks to other CPUs before
623 * this rtas call to avoid tricky post processing of those CPUs'
626 if (should_fadump_crash())
634 #ifdef CONFIG_KEXEC_CORE
635 if (kexec_crash_image) {
636 crash_kexec_prepare();
644 #ifdef CONFIG_NMI_IPI
645 static void nmi_stop_this_cpu(struct pt_regs *regs)
648 * IRQs are already hard disabled by the smp_handle_nmi_ipi.
650 set_cpu_online(smp_processor_id(), false);
657 void smp_send_stop(void)
659 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, nmi_stop_this_cpu, 1000000);
662 #else /* CONFIG_NMI_IPI */
664 static void stop_this_cpu(void *dummy)
669 * Offlining CPUs in stop_this_cpu can result in scheduler warnings,
670 * (see commit de6e5d38417e), but printk_safe_flush_on_panic() wants
671 * to know other CPUs are offline before it breaks locks to flush
672 * printk buffers, in case we panic()ed while holding the lock.
674 set_cpu_online(smp_processor_id(), false);
681 void smp_send_stop(void)
683 static bool stopped = false;
686 * Prevent waiting on csd lock from a previous smp_send_stop.
687 * This is racy, but in general callers try to do the right
688 * thing and only fire off one smp_send_stop (e.g., see
696 smp_call_function(stop_this_cpu, NULL, 0);
698 #endif /* CONFIG_NMI_IPI */
700 static struct task_struct *current_set[NR_CPUS];
702 static void smp_store_cpu_info(int id)
704 per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR);
705 #ifdef CONFIG_PPC_E500
706 per_cpu(next_tlbcam_idx, id)
707 = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1;
712 * Relationships between CPUs are maintained in a set of per-cpu cpumasks so
713 * rather than just passing around the cpumask we pass around a function that
714 * returns the that cpumask for the given CPU.
716 static void set_cpus_related(int i, int j, struct cpumask *(*get_cpumask)(int))
718 cpumask_set_cpu(i, get_cpumask(j));
719 cpumask_set_cpu(j, get_cpumask(i));
722 #ifdef CONFIG_HOTPLUG_CPU
723 static void set_cpus_unrelated(int i, int j,
724 struct cpumask *(*get_cpumask)(int))
726 cpumask_clear_cpu(i, get_cpumask(j));
727 cpumask_clear_cpu(j, get_cpumask(i));
732 * Extends set_cpus_related. Instead of setting one CPU at a time in
733 * dstmask, set srcmask at oneshot. dstmask should be super set of srcmask.
735 static void or_cpumasks_related(int i, int j, struct cpumask *(*srcmask)(int),
736 struct cpumask *(*dstmask)(int))
738 struct cpumask *mask;
742 for_each_cpu(k, srcmask(i))
743 cpumask_or(dstmask(k), dstmask(k), mask);
749 for_each_cpu(k, srcmask(j))
750 cpumask_or(dstmask(k), dstmask(k), mask);
754 * parse_thread_groups: Parses the "ibm,thread-groups" device tree
755 * property for the CPU device node @dn and stores
756 * the parsed output in the thread_groups_list
759 * @dn: The device node of the CPU device.
760 * @tglp: Pointer to a thread group list structure into which the parsed
761 * output of "ibm,thread-groups" is stored.
763 * ibm,thread-groups[0..N-1] array defines which group of threads in
764 * the CPU-device node can be grouped together based on the property.
766 * This array can represent thread groupings for multiple properties.
768 * ibm,thread-groups[i + 0] tells us the property based on which the
769 * threads are being grouped together. If this value is 1, it implies
770 * that the threads in the same group share L1, translation cache. If
771 * the value is 2, it implies that the threads in the same group share
774 * ibm,thread-groups[i+1] tells us how many such thread groups exist for the
775 * property ibm,thread-groups[i]
777 * ibm,thread-groups[i+2] tells us the number of threads in each such
779 * Suppose k = (ibm,thread-groups[i+1] * ibm,thread-groups[i+2]), then,
781 * ibm,thread-groups[i+3..i+k+2] (is the list of threads identified by
782 * "ibm,ppc-interrupt-server#s" arranged as per their membership in
786 * If "ibm,thread-groups" = [1,2,4,8,10,12,14,9,11,13,15,2,2,4,8,10,12,14,9,11,13,15]
787 * This can be decomposed up into two consecutive arrays:
788 * a) [1,2,4,8,10,12,14,9,11,13,15]
789 * b) [2,2,4,8,10,12,14,9,11,13,15]
793 * a) provides information of Property "1" being shared by "2" groups,
794 * each with "4" threads each. The "ibm,ppc-interrupt-server#s" of
795 * the first group is {8,10,12,14} and the
796 * "ibm,ppc-interrupt-server#s" of the second group is
797 * {9,11,13,15}. Property "1" is indicative of the thread in the
798 * group sharing L1 cache, translation cache and Instruction Data
801 * b) provides information of Property "2" being shared by "2" groups,
802 * each group with "4" threads. The "ibm,ppc-interrupt-server#s" of
803 * the first group is {8,10,12,14} and the
804 * "ibm,ppc-interrupt-server#s" of the second group is
805 * {9,11,13,15}. Property "2" indicates that the threads in each
806 * group share the L2-cache.
808 * Returns 0 on success, -EINVAL if the property does not exist,
809 * -ENODATA if property does not have a value, and -EOVERFLOW if the
810 * property data isn't large enough.
812 static int parse_thread_groups(struct device_node *dn,
813 struct thread_groups_list *tglp)
815 unsigned int property_idx = 0;
816 u32 *thread_group_array;
817 size_t total_threads;
822 count = of_property_count_u32_elems(dn, "ibm,thread-groups");
823 thread_group_array = kcalloc(count, sizeof(u32), GFP_KERNEL);
824 ret = of_property_read_u32_array(dn, "ibm,thread-groups",
825 thread_group_array, count);
829 while (i < count && property_idx < MAX_THREAD_GROUP_PROPERTIES) {
831 struct thread_groups *tg = &tglp->property_tgs[property_idx++];
833 tg->property = thread_group_array[i];
834 tg->nr_groups = thread_group_array[i + 1];
835 tg->threads_per_group = thread_group_array[i + 2];
836 total_threads = tg->nr_groups * tg->threads_per_group;
838 thread_list = &thread_group_array[i + 3];
840 for (j = 0; j < total_threads; j++)
841 tg->thread_list[j] = thread_list[j];
842 i = i + 3 + total_threads;
845 tglp->nr_properties = property_idx;
848 kfree(thread_group_array);
853 * get_cpu_thread_group_start : Searches the thread group in tg->thread_list
854 * that @cpu belongs to.
856 * @cpu : The logical CPU whose thread group is being searched.
857 * @tg : The thread-group structure of the CPU node which @cpu belongs
860 * Returns the index to tg->thread_list that points to the start
861 * of the thread_group that @cpu belongs to.
863 * Returns -1 if cpu doesn't belong to any of the groups pointed to by
866 static int get_cpu_thread_group_start(int cpu, struct thread_groups *tg)
868 int hw_cpu_id = get_hard_smp_processor_id(cpu);
871 for (i = 0; i < tg->nr_groups; i++) {
872 int group_start = i * tg->threads_per_group;
874 for (j = 0; j < tg->threads_per_group; j++) {
875 int idx = group_start + j;
877 if (tg->thread_list[idx] == hw_cpu_id)
885 static struct thread_groups *__init get_thread_groups(int cpu,
889 struct device_node *dn = of_get_cpu_node(cpu, NULL);
890 struct thread_groups_list *cpu_tgl = &tgl[cpu];
891 struct thread_groups *tg = NULL;
900 if (!cpu_tgl->nr_properties) {
901 *err = parse_thread_groups(dn, cpu_tgl);
906 for (i = 0; i < cpu_tgl->nr_properties; i++) {
907 if (cpu_tgl->property_tgs[i].property == group_property) {
908 tg = &cpu_tgl->property_tgs[i];
920 static int __init update_mask_from_threadgroup(cpumask_var_t *mask, struct thread_groups *tg,
921 int cpu, int cpu_group_start)
923 int first_thread = cpu_first_thread_sibling(cpu);
926 zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cpu));
928 for (i = first_thread; i < first_thread + threads_per_core; i++) {
929 int i_group_start = get_cpu_thread_group_start(i, tg);
931 if (unlikely(i_group_start == -1)) {
936 if (i_group_start == cpu_group_start)
937 cpumask_set_cpu(i, *mask);
943 static int __init init_thread_group_cache_map(int cpu, int cache_property)
946 int cpu_group_start = -1, err = 0;
947 struct thread_groups *tg = NULL;
948 cpumask_var_t *mask = NULL;
950 if (cache_property != THREAD_GROUP_SHARE_L1 &&
951 cache_property != THREAD_GROUP_SHARE_L2_L3)
954 tg = get_thread_groups(cpu, cache_property, &err);
959 cpu_group_start = get_cpu_thread_group_start(cpu, tg);
961 if (unlikely(cpu_group_start == -1)) {
966 if (cache_property == THREAD_GROUP_SHARE_L1) {
967 mask = &per_cpu(thread_group_l1_cache_map, cpu);
968 update_mask_from_threadgroup(mask, tg, cpu, cpu_group_start);
970 else if (cache_property == THREAD_GROUP_SHARE_L2_L3) {
971 mask = &per_cpu(thread_group_l2_cache_map, cpu);
972 update_mask_from_threadgroup(mask, tg, cpu, cpu_group_start);
973 mask = &per_cpu(thread_group_l3_cache_map, cpu);
974 update_mask_from_threadgroup(mask, tg, cpu, cpu_group_start);
981 static bool shared_caches __ro_after_init;
983 #ifdef CONFIG_SCHED_SMT
984 /* cpumask of CPUs with asymmetric SMT dependency */
985 static int powerpc_smt_flags(void)
987 int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES;
989 if (cpu_has_feature(CPU_FTR_ASYM_SMT)) {
990 printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n");
991 flags |= SD_ASYM_PACKING;
998 * On shared processor LPARs scheduled on a big core (which has two or more
999 * independent thread groups per core), prefer lower numbered CPUs, so
1000 * that workload consolidates to lesser number of cores.
1002 static __ro_after_init DEFINE_STATIC_KEY_FALSE(splpar_asym_pack);
1005 * P9 has a slightly odd architecture where pairs of cores share an L2 cache.
1006 * This topology makes it *much* cheaper to migrate tasks between adjacent cores
1007 * since the migrated task remains cache hot. We want to take advantage of this
1008 * at the scheduler level so an extra topology level is required.
1010 static int powerpc_shared_cache_flags(void)
1012 if (static_branch_unlikely(&splpar_asym_pack))
1013 return SD_SHARE_PKG_RESOURCES | SD_ASYM_PACKING;
1015 return SD_SHARE_PKG_RESOURCES;
1018 static int powerpc_shared_proc_flags(void)
1020 if (static_branch_unlikely(&splpar_asym_pack))
1021 return SD_ASYM_PACKING;
1027 * We can't just pass cpu_l2_cache_mask() directly because
1028 * returns a non-const pointer and the compiler barfs on that.
1030 static const struct cpumask *shared_cache_mask(int cpu)
1032 return per_cpu(cpu_l2_cache_map, cpu);
1035 #ifdef CONFIG_SCHED_SMT
1036 static const struct cpumask *smallcore_smt_mask(int cpu)
1038 return cpu_smallcore_mask(cpu);
1042 static struct cpumask *cpu_coregroup_mask(int cpu)
1044 return per_cpu(cpu_coregroup_map, cpu);
1047 static bool has_coregroup_support(void)
1049 /* Coregroup identification not available on shared systems */
1050 if (is_shared_processor())
1053 return coregroup_enabled;
1056 static const struct cpumask *cpu_mc_mask(int cpu)
1058 return cpu_coregroup_mask(cpu);
1061 static int __init init_big_cores(void)
1065 for_each_possible_cpu(cpu) {
1066 int err = init_thread_group_cache_map(cpu, THREAD_GROUP_SHARE_L1);
1071 zalloc_cpumask_var_node(&per_cpu(cpu_smallcore_map, cpu),
1076 has_big_cores = true;
1078 for_each_possible_cpu(cpu) {
1079 int err = init_thread_group_cache_map(cpu, THREAD_GROUP_SHARE_L2_L3);
1085 thread_group_shares_l2 = true;
1086 thread_group_shares_l3 = true;
1087 pr_debug("L2/L3 cache only shared by the threads in the small core\n");
1092 void __init smp_prepare_cpus(unsigned int max_cpus)
1094 unsigned int cpu, num_threads;
1096 DBG("smp_prepare_cpus\n");
1099 * setup_cpu may need to be called on the boot cpu. We haven't
1100 * spun any cpus up but lets be paranoid.
1102 BUG_ON(boot_cpuid != smp_processor_id());
1104 /* Fixup boot cpu */
1105 smp_store_cpu_info(boot_cpuid);
1106 cpu_callin_map[boot_cpuid] = 1;
1108 for_each_possible_cpu(cpu) {
1109 zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu),
1110 GFP_KERNEL, cpu_to_node(cpu));
1111 zalloc_cpumask_var_node(&per_cpu(cpu_l2_cache_map, cpu),
1112 GFP_KERNEL, cpu_to_node(cpu));
1113 zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu),
1114 GFP_KERNEL, cpu_to_node(cpu));
1115 if (has_coregroup_support())
1116 zalloc_cpumask_var_node(&per_cpu(cpu_coregroup_map, cpu),
1117 GFP_KERNEL, cpu_to_node(cpu));
1121 * numa_node_id() works after this.
1123 if (cpu_present(cpu)) {
1124 set_cpu_numa_node(cpu, numa_cpu_lookup_table[cpu]);
1125 set_cpu_numa_mem(cpu,
1126 local_memory_node(numa_cpu_lookup_table[cpu]));
1131 /* Init the cpumasks so the boot CPU is related to itself */
1132 cpumask_set_cpu(boot_cpuid, cpu_sibling_mask(boot_cpuid));
1133 cpumask_set_cpu(boot_cpuid, cpu_l2_cache_mask(boot_cpuid));
1134 cpumask_set_cpu(boot_cpuid, cpu_core_mask(boot_cpuid));
1136 if (has_coregroup_support())
1137 cpumask_set_cpu(boot_cpuid, cpu_coregroup_mask(boot_cpuid));
1140 if (has_big_cores) {
1141 cpumask_set_cpu(boot_cpuid,
1142 cpu_smallcore_mask(boot_cpuid));
1145 if (cpu_to_chip_id(boot_cpuid) != -1) {
1146 int idx = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1149 * All threads of a core will all belong to the same core,
1150 * chip_id_lookup_table will have one entry per core.
1151 * Assumption: if boot_cpuid doesn't have a chip-id, then no
1152 * other CPUs, will also not have chip-id.
1154 chip_id_lookup_table = kcalloc(idx, sizeof(int), GFP_KERNEL);
1155 if (chip_id_lookup_table)
1156 memset(chip_id_lookup_table, -1, sizeof(int) * idx);
1159 if (smp_ops && smp_ops->probe)
1162 // Initalise the generic SMT topology support
1164 if (smt_enabled_at_boot)
1165 num_threads = smt_enabled_at_boot;
1166 cpu_smt_set_num_threads(num_threads, threads_per_core);
1169 void smp_prepare_boot_cpu(void)
1171 BUG_ON(smp_processor_id() != boot_cpuid);
1173 paca_ptrs[boot_cpuid]->__current = current;
1175 set_numa_node(numa_cpu_lookup_table[boot_cpuid]);
1176 current_set[boot_cpuid] = current;
1179 #ifdef CONFIG_HOTPLUG_CPU
1181 int generic_cpu_disable(void)
1183 unsigned int cpu = smp_processor_id();
1185 if (cpu == boot_cpuid)
1188 set_cpu_online(cpu, false);
1190 vdso_data->processorCount--;
1192 /* Update affinity of all IRQs previously aimed at this CPU */
1193 irq_migrate_all_off_this_cpu();
1196 * Depending on the details of the interrupt controller, it's possible
1197 * that one of the interrupts we just migrated away from this CPU is
1198 * actually already pending on this CPU. If we leave it in that state
1199 * the interrupt will never be EOI'ed, and will never fire again. So
1200 * temporarily enable interrupts here, to allow any pending interrupt to
1201 * be received (and EOI'ed), before we take this CPU offline.
1205 local_irq_disable();
1210 void generic_cpu_die(unsigned int cpu)
1214 for (i = 0; i < 100; i++) {
1216 if (is_cpu_dead(cpu))
1220 printk(KERN_ERR "CPU%d didn't die...\n", cpu);
1223 void generic_set_cpu_dead(unsigned int cpu)
1225 per_cpu(cpu_state, cpu) = CPU_DEAD;
1229 * The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise
1230 * the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(),
1231 * which makes the delay in generic_cpu_die() not happen.
1233 void generic_set_cpu_up(unsigned int cpu)
1235 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1238 int generic_check_cpu_restart(unsigned int cpu)
1240 return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE;
1243 int is_cpu_dead(unsigned int cpu)
1245 return per_cpu(cpu_state, cpu) == CPU_DEAD;
1248 static bool secondaries_inhibited(void)
1250 return kvm_hv_mode_active();
1253 #else /* HOTPLUG_CPU */
1255 #define secondaries_inhibited() 0
1259 static void cpu_idle_thread_init(unsigned int cpu, struct task_struct *idle)
1262 paca_ptrs[cpu]->__current = idle;
1263 paca_ptrs[cpu]->kstack = (unsigned long)task_stack_page(idle) +
1264 THREAD_SIZE - STACK_FRAME_MIN_SIZE;
1266 task_thread_info(idle)->cpu = cpu;
1267 secondary_current = current_set[cpu] = idle;
1270 int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1272 const unsigned long boot_spin_ms = 5 * MSEC_PER_SEC;
1273 const bool booting = system_state < SYSTEM_RUNNING;
1274 const unsigned long hp_spin_ms = 1;
1275 unsigned long deadline;
1277 const unsigned long spin_wait_ms = booting ? boot_spin_ms : hp_spin_ms;
1280 * Don't allow secondary threads to come online if inhibited
1282 if (threads_per_core > 1 && secondaries_inhibited() &&
1283 cpu_thread_in_subcore(cpu))
1286 if (smp_ops == NULL ||
1287 (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu)))
1290 cpu_idle_thread_init(cpu, tidle);
1293 * The platform might need to allocate resources prior to bringing
1296 if (smp_ops->prepare_cpu) {
1297 rc = smp_ops->prepare_cpu(cpu);
1302 /* Make sure callin-map entry is 0 (can be leftover a CPU
1305 cpu_callin_map[cpu] = 0;
1307 /* The information for processor bringup must
1308 * be written out to main store before we release
1314 DBG("smp: kicking cpu %d\n", cpu);
1315 rc = smp_ops->kick_cpu(cpu);
1317 pr_err("smp: failed starting cpu %d (rc %d)\n", cpu, rc);
1322 * At boot time, simply spin on the callin word until the
1325 * At run time, spin for an optimistic amount of time to avoid
1326 * sleeping in the common case.
1328 deadline = jiffies + msecs_to_jiffies(spin_wait_ms);
1329 spin_until_cond(cpu_callin_map[cpu] || time_is_before_jiffies(deadline));
1331 if (!cpu_callin_map[cpu] && system_state >= SYSTEM_RUNNING) {
1332 const unsigned long sleep_interval_us = 10 * USEC_PER_MSEC;
1333 const unsigned long sleep_wait_ms = 100 * MSEC_PER_SEC;
1335 deadline = jiffies + msecs_to_jiffies(sleep_wait_ms);
1336 while (!cpu_callin_map[cpu] && time_is_after_jiffies(deadline))
1337 fsleep(sleep_interval_us);
1340 if (!cpu_callin_map[cpu]) {
1341 printk(KERN_ERR "Processor %u is stuck.\n", cpu);
1345 DBG("Processor %u found.\n", cpu);
1347 if (smp_ops->give_timebase)
1348 smp_ops->give_timebase();
1350 /* Wait until cpu puts itself in the online & active maps */
1351 spin_until_cond(cpu_online(cpu));
1356 /* Return the value of the reg property corresponding to the given
1359 int cpu_to_core_id(int cpu)
1361 struct device_node *np;
1364 np = of_get_cpu_node(cpu, NULL);
1368 id = of_get_cpu_hwid(np, 0);
1373 EXPORT_SYMBOL_GPL(cpu_to_core_id);
1375 /* Helper routines for cpu to core mapping */
1376 int cpu_core_index_of_thread(int cpu)
1378 return cpu >> threads_shift;
1380 EXPORT_SYMBOL_GPL(cpu_core_index_of_thread);
1382 int cpu_first_thread_of_core(int core)
1384 return core << threads_shift;
1386 EXPORT_SYMBOL_GPL(cpu_first_thread_of_core);
1388 /* Must be called when no change can occur to cpu_present_mask,
1389 * i.e. during cpu online or offline.
1391 static struct device_node *cpu_to_l2cache(int cpu)
1393 struct device_node *np;
1394 struct device_node *cache;
1396 if (!cpu_present(cpu))
1399 np = of_get_cpu_node(cpu, NULL);
1403 cache = of_find_next_cache_node(np);
1410 static bool update_mask_by_l2(int cpu, cpumask_var_t *mask)
1412 struct cpumask *(*submask_fn)(int) = cpu_sibling_mask;
1413 struct device_node *l2_cache, *np;
1417 submask_fn = cpu_smallcore_mask;
1420 * If the threads in a thread-group share L2 cache, then the
1421 * L2-mask can be obtained from thread_group_l2_cache_map.
1423 if (thread_group_shares_l2) {
1424 cpumask_set_cpu(cpu, cpu_l2_cache_mask(cpu));
1426 for_each_cpu(i, per_cpu(thread_group_l2_cache_map, cpu)) {
1428 set_cpus_related(i, cpu, cpu_l2_cache_mask);
1431 /* Verify that L1-cache siblings are a subset of L2 cache-siblings */
1432 if (!cpumask_equal(submask_fn(cpu), cpu_l2_cache_mask(cpu)) &&
1433 !cpumask_subset(submask_fn(cpu), cpu_l2_cache_mask(cpu))) {
1434 pr_warn_once("CPU %d : Inconsistent L1 and L2 cache siblings\n",
1441 l2_cache = cpu_to_l2cache(cpu);
1442 if (!l2_cache || !*mask) {
1443 /* Assume only core siblings share cache with this CPU */
1444 for_each_cpu(i, cpu_sibling_mask(cpu))
1445 set_cpus_related(cpu, i, cpu_l2_cache_mask);
1450 cpumask_and(*mask, cpu_online_mask, cpu_cpu_mask(cpu));
1452 /* Update l2-cache mask with all the CPUs that are part of submask */
1453 or_cpumasks_related(cpu, cpu, submask_fn, cpu_l2_cache_mask);
1455 /* Skip all CPUs already part of current CPU l2-cache mask */
1456 cpumask_andnot(*mask, *mask, cpu_l2_cache_mask(cpu));
1458 for_each_cpu(i, *mask) {
1460 * when updating the marks the current CPU has not been marked
1461 * online, but we need to update the cache masks
1463 np = cpu_to_l2cache(i);
1465 /* Skip all CPUs already part of current CPU l2-cache */
1466 if (np == l2_cache) {
1467 or_cpumasks_related(cpu, i, submask_fn, cpu_l2_cache_mask);
1468 cpumask_andnot(*mask, *mask, submask_fn(i));
1470 cpumask_andnot(*mask, *mask, cpu_l2_cache_mask(i));
1475 of_node_put(l2_cache);
1480 #ifdef CONFIG_HOTPLUG_CPU
1481 static void remove_cpu_from_masks(int cpu)
1483 struct cpumask *(*mask_fn)(int) = cpu_sibling_mask;
1486 unmap_cpu_from_node(cpu);
1489 mask_fn = cpu_l2_cache_mask;
1491 for_each_cpu(i, mask_fn(cpu)) {
1492 set_cpus_unrelated(cpu, i, cpu_l2_cache_mask);
1493 set_cpus_unrelated(cpu, i, cpu_sibling_mask);
1495 set_cpus_unrelated(cpu, i, cpu_smallcore_mask);
1498 for_each_cpu(i, cpu_core_mask(cpu))
1499 set_cpus_unrelated(cpu, i, cpu_core_mask);
1501 if (has_coregroup_support()) {
1502 for_each_cpu(i, cpu_coregroup_mask(cpu))
1503 set_cpus_unrelated(cpu, i, cpu_coregroup_mask);
1508 static inline void add_cpu_to_smallcore_masks(int cpu)
1515 cpumask_set_cpu(cpu, cpu_smallcore_mask(cpu));
1517 for_each_cpu(i, per_cpu(thread_group_l1_cache_map, cpu)) {
1519 set_cpus_related(i, cpu, cpu_smallcore_mask);
1523 static void update_coregroup_mask(int cpu, cpumask_var_t *mask)
1525 struct cpumask *(*submask_fn)(int) = cpu_sibling_mask;
1526 int coregroup_id = cpu_to_coregroup_id(cpu);
1530 submask_fn = cpu_l2_cache_mask;
1533 /* Assume only siblings are part of this CPU's coregroup */
1534 for_each_cpu(i, submask_fn(cpu))
1535 set_cpus_related(cpu, i, cpu_coregroup_mask);
1540 cpumask_and(*mask, cpu_online_mask, cpu_cpu_mask(cpu));
1542 /* Update coregroup mask with all the CPUs that are part of submask */
1543 or_cpumasks_related(cpu, cpu, submask_fn, cpu_coregroup_mask);
1545 /* Skip all CPUs already part of coregroup mask */
1546 cpumask_andnot(*mask, *mask, cpu_coregroup_mask(cpu));
1548 for_each_cpu(i, *mask) {
1549 /* Skip all CPUs not part of this coregroup */
1550 if (coregroup_id == cpu_to_coregroup_id(i)) {
1551 or_cpumasks_related(cpu, i, submask_fn, cpu_coregroup_mask);
1552 cpumask_andnot(*mask, *mask, submask_fn(i));
1554 cpumask_andnot(*mask, *mask, cpu_coregroup_mask(i));
1559 static void add_cpu_to_masks(int cpu)
1561 struct cpumask *(*submask_fn)(int) = cpu_sibling_mask;
1562 int first_thread = cpu_first_thread_sibling(cpu);
1569 * This CPU will not be in the online mask yet so we need to manually
1570 * add it to it's own thread sibling mask.
1572 map_cpu_to_node(cpu, cpu_to_node(cpu));
1573 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
1574 cpumask_set_cpu(cpu, cpu_core_mask(cpu));
1576 for (i = first_thread; i < first_thread + threads_per_core; i++)
1578 set_cpus_related(i, cpu, cpu_sibling_mask);
1580 add_cpu_to_smallcore_masks(cpu);
1582 /* In CPU-hotplug path, hence use GFP_ATOMIC */
1583 ret = alloc_cpumask_var_node(&mask, GFP_ATOMIC, cpu_to_node(cpu));
1584 update_mask_by_l2(cpu, &mask);
1586 if (has_coregroup_support())
1587 update_coregroup_mask(cpu, &mask);
1589 if (chip_id_lookup_table && ret)
1590 chip_id = cpu_to_chip_id(cpu);
1593 submask_fn = cpu_l2_cache_mask;
1595 /* Update core_mask with all the CPUs that are part of submask */
1596 or_cpumasks_related(cpu, cpu, submask_fn, cpu_core_mask);
1598 /* Skip all CPUs already part of current CPU core mask */
1599 cpumask_andnot(mask, cpu_online_mask, cpu_core_mask(cpu));
1601 /* If chip_id is -1; limit the cpu_core_mask to within PKG */
1603 cpumask_and(mask, mask, cpu_cpu_mask(cpu));
1605 for_each_cpu(i, mask) {
1606 if (chip_id == cpu_to_chip_id(i)) {
1607 or_cpumasks_related(cpu, i, submask_fn, cpu_core_mask);
1608 cpumask_andnot(mask, mask, submask_fn(i));
1610 cpumask_andnot(mask, mask, cpu_core_mask(i));
1614 free_cpumask_var(mask);
1617 /* Activate a secondary processor. */
1618 __no_stack_protector
1619 void start_secondary(void *unused)
1621 unsigned int cpu = raw_smp_processor_id();
1623 /* PPC64 calls setup_kup() in early_setup_secondary() */
1624 if (IS_ENABLED(CONFIG_PPC32))
1627 mmgrab_lazy_tlb(&init_mm);
1628 current->active_mm = &init_mm;
1629 VM_WARN_ON(cpumask_test_cpu(smp_processor_id(), mm_cpumask(&init_mm)));
1630 cpumask_set_cpu(cpu, mm_cpumask(&init_mm));
1631 inc_mm_active_cpus(&init_mm);
1633 smp_store_cpu_info(cpu);
1634 set_dec(tb_ticks_per_jiffy);
1635 rcutree_report_cpu_starting(cpu);
1636 cpu_callin_map[cpu] = 1;
1638 if (smp_ops->setup_cpu)
1639 smp_ops->setup_cpu(cpu);
1640 if (smp_ops->take_timebase)
1641 smp_ops->take_timebase();
1643 secondary_cpu_time_init();
1646 if (system_state == SYSTEM_RUNNING)
1647 vdso_data->processorCount++;
1651 set_numa_node(numa_cpu_lookup_table[cpu]);
1652 set_numa_mem(local_memory_node(numa_cpu_lookup_table[cpu]));
1654 /* Update topology CPU masks */
1655 add_cpu_to_masks(cpu);
1658 * Check for any shared caches. Note that this must be done on a
1659 * per-core basis because one core in the pair might be disabled.
1661 if (!shared_caches) {
1662 struct cpumask *(*sibling_mask)(int) = cpu_sibling_mask;
1663 struct cpumask *mask = cpu_l2_cache_mask(cpu);
1666 sibling_mask = cpu_smallcore_mask;
1668 if (cpumask_weight(mask) > cpumask_weight(sibling_mask(cpu)))
1669 shared_caches = true;
1673 notify_cpu_starting(cpu);
1674 set_cpu_online(cpu, true);
1676 boot_init_stack_canary();
1680 /* We can enable ftrace for secondary cpus now */
1681 this_cpu_enable_ftrace();
1683 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
1688 static struct sched_domain_topology_level powerpc_topology[6];
1690 static void __init build_sched_topology(void)
1694 if (is_shared_processor() && has_big_cores)
1695 static_branch_enable(&splpar_asym_pack);
1697 #ifdef CONFIG_SCHED_SMT
1698 if (has_big_cores) {
1699 pr_info("Big cores detected but using small core scheduling\n");
1700 powerpc_topology[i++] = (struct sched_domain_topology_level){
1701 smallcore_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT)
1704 powerpc_topology[i++] = (struct sched_domain_topology_level){
1705 cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT)
1709 if (shared_caches) {
1710 powerpc_topology[i++] = (struct sched_domain_topology_level){
1711 shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE)
1714 if (has_coregroup_support()) {
1715 powerpc_topology[i++] = (struct sched_domain_topology_level){
1716 cpu_mc_mask, powerpc_shared_proc_flags, SD_INIT_NAME(MC)
1719 powerpc_topology[i++] = (struct sched_domain_topology_level){
1720 cpu_cpu_mask, powerpc_shared_proc_flags, SD_INIT_NAME(PKG)
1723 /* There must be one trailing NULL entry left. */
1724 BUG_ON(i >= ARRAY_SIZE(powerpc_topology) - 1);
1726 set_sched_topology(powerpc_topology);
1729 void __init smp_cpus_done(unsigned int max_cpus)
1732 * We are running pinned to the boot CPU, see rest_init().
1734 if (smp_ops && smp_ops->setup_cpu)
1735 smp_ops->setup_cpu(boot_cpuid);
1737 if (smp_ops && smp_ops->bringup_done)
1738 smp_ops->bringup_done();
1740 dump_numa_cpu_topology();
1741 build_sched_topology();
1745 * For asym packing, by default lower numbered CPU has higher priority.
1746 * On shared processors, pack to lower numbered core. However avoid moving
1747 * between thread_groups within the same core.
1749 int arch_asym_cpu_priority(int cpu)
1751 if (static_branch_unlikely(&splpar_asym_pack))
1752 return -cpu / threads_per_core;
1757 #ifdef CONFIG_HOTPLUG_CPU
1758 int __cpu_disable(void)
1760 int cpu = smp_processor_id();
1763 if (!smp_ops->cpu_disable)
1766 this_cpu_disable_ftrace();
1768 err = smp_ops->cpu_disable();
1772 /* Update sibling maps */
1773 remove_cpu_from_masks(cpu);
1778 void __cpu_die(unsigned int cpu)
1781 * This could perhaps be a generic call in idlea_task_dead(), but
1782 * that requires testing from all archs, so first put it here to
1784 VM_WARN_ON_ONCE(!cpumask_test_cpu(cpu, mm_cpumask(&init_mm)));
1785 dec_mm_active_cpus(&init_mm);
1786 cpumask_clear_cpu(cpu, mm_cpumask(&init_mm));
1788 if (smp_ops->cpu_die)
1789 smp_ops->cpu_die(cpu);
1792 void __noreturn arch_cpu_idle_dead(void)
1795 * Disable on the down path. This will be re-enabled by
1796 * start_secondary() via start_secondary_resume() below
1798 this_cpu_disable_ftrace();
1800 if (smp_ops->cpu_offline_self)
1801 smp_ops->cpu_offline_self();
1803 /* If we return, we re-enter start_secondary */
1804 start_secondary_resume();