1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Common boot and setup code.
6 * Copyright (C) 2001 PPC64 Team, IBM Corp
9 #include <linux/export.h>
10 #include <linux/string.h>
11 #include <linux/sched.h>
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/reboot.h>
15 #include <linux/delay.h>
16 #include <linux/initrd.h>
17 #include <linux/seq_file.h>
18 #include <linux/ioport.h>
19 #include <linux/console.h>
20 #include <linux/utsname.h>
21 #include <linux/tty.h>
22 #include <linux/root_dev.h>
23 #include <linux/notifier.h>
24 #include <linux/cpu.h>
25 #include <linux/unistd.h>
26 #include <linux/serial.h>
27 #include <linux/serial_8250.h>
28 #include <linux/memblock.h>
29 #include <linux/pci.h>
30 #include <linux/lockdep.h>
31 #include <linux/memory.h>
32 #include <linux/nmi.h>
33 #include <linux/pgtable.h>
35 #include <asm/kvm_guest.h>
37 #include <asm/kdump.h>
39 #include <asm/processor.h>
42 #include <asm/machdep.h>
45 #include <asm/cputable.h>
46 #include <asm/dt_cpu_ftrs.h>
47 #include <asm/sections.h>
48 #include <asm/btext.h>
49 #include <asm/nvram.h>
50 #include <asm/setup.h>
52 #include <asm/iommu.h>
53 #include <asm/serial.h>
54 #include <asm/cache.h>
57 #include <asm/firmware.h>
60 #include <asm/kexec.h>
61 #include <asm/code-patching.h>
62 #include <asm/livepatch.h>
64 #include <asm/cputhreads.h>
65 #include <asm/hw_irq.h>
66 #include <asm/feature-fixups.h>
68 #include <asm/early_ioremap.h>
69 #include <asm/pgalloc.h>
73 int spinning_secondaries;
76 struct ppc64_caches ppc64_caches = {
86 EXPORT_SYMBOL_GPL(ppc64_caches);
88 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
89 void __init setup_tlb_core_data(void)
93 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
95 for_each_possible_cpu(cpu) {
96 int first = cpu_first_thread_sibling(cpu);
99 * If we boot via kdump on a non-primary thread,
100 * make sure we point at the thread that actually
103 if (cpu_first_thread_sibling(boot_cpuid) == first)
106 paca_ptrs[cpu]->tcd_ptr = &paca_ptrs[first]->tcd;
109 * If we have threads, we need either tlbsrx.
110 * or e6500 tablewalk mode, or else TLB handlers
111 * will be racy and could produce duplicate entries.
112 * Should we panic instead?
114 WARN_ONCE(smt_enabled_at_boot >= 2 &&
115 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
116 book3e_htw_mode != PPC_HTW_E6500,
117 "%s: unsupported MMU configuration\n", __func__);
124 static char *smt_enabled_cmdline;
126 /* Look for ibm,smt-enabled OF option */
127 void __init check_smt_enabled(void)
129 struct device_node *dn;
130 const char *smt_option;
132 /* Default to enabling all threads */
133 smt_enabled_at_boot = threads_per_core;
135 /* Allow the command line to overrule the OF option */
136 if (smt_enabled_cmdline) {
137 if (!strcmp(smt_enabled_cmdline, "on"))
138 smt_enabled_at_boot = threads_per_core;
139 else if (!strcmp(smt_enabled_cmdline, "off"))
140 smt_enabled_at_boot = 0;
145 rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
147 smt_enabled_at_boot =
148 min(threads_per_core, smt);
151 dn = of_find_node_by_path("/options");
153 smt_option = of_get_property(dn, "ibm,smt-enabled",
157 if (!strcmp(smt_option, "on"))
158 smt_enabled_at_boot = threads_per_core;
159 else if (!strcmp(smt_option, "off"))
160 smt_enabled_at_boot = 0;
168 /* Look for smt-enabled= cmdline option */
169 static int __init early_smt_enabled(char *p)
171 smt_enabled_cmdline = p;
174 early_param("smt-enabled", early_smt_enabled);
176 #endif /* CONFIG_SMP */
178 /** Fix up paca fields required for the boot cpu */
179 static void __init fixup_boot_paca(void)
181 /* The boot cpu is started */
182 get_paca()->cpu_start = 1;
183 /* Allow percpu accesses to work until we setup percpu data */
184 get_paca()->data_offset = 0;
185 /* Mark interrupts disabled in PACA */
186 irq_soft_mask_set(IRQS_DISABLED);
189 static void __init configure_exceptions(void)
192 * Setup the trampolines from the lowmem exception vectors
193 * to the kdump kernel when not using a relocatable kernel.
195 setup_kdump_trampoline();
197 /* Under a PAPR hypervisor, we need hypercalls */
198 if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
199 /* Enable AIL if possible */
200 if (!pseries_enable_reloc_on_exc()) {
201 init_task.thread.fscr &= ~FSCR_SCV;
202 cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_SCV;
206 * Tell the hypervisor that we want our exceptions to
207 * be taken in little endian mode.
209 * We don't call this for big endian as our calling convention
210 * makes us always enter in BE, and the call may fail under
211 * some circumstances with kdump.
213 #ifdef __LITTLE_ENDIAN__
214 pseries_little_endian_exceptions();
217 /* Set endian mode using OPAL */
218 if (firmware_has_feature(FW_FEATURE_OPAL))
219 opal_configure_cores();
221 /* AIL on native is done in cpu_ready_for_interrupts() */
225 static void cpu_ready_for_interrupts(void)
228 * Enable AIL if supported, and we are in hypervisor mode. This
229 * is called once for every processor.
231 * If we are not in hypervisor mode the job is done once for
232 * the whole partition in configure_exceptions().
234 if (cpu_has_feature(CPU_FTR_HVMODE)) {
235 unsigned long lpcr = mfspr(SPRN_LPCR);
236 unsigned long new_lpcr = lpcr;
238 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
239 /* P10 DD1 does not have HAIL */
240 if (pvr_version_is(PVR_POWER10) &&
241 (mfspr(SPRN_PVR) & 0xf00) == 0x100)
242 new_lpcr |= LPCR_AIL_3;
244 new_lpcr |= LPCR_HAIL;
245 } else if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
246 new_lpcr |= LPCR_AIL_3;
249 if (new_lpcr != lpcr)
250 mtspr(SPRN_LPCR, new_lpcr);
254 * Set HFSCR:TM based on CPU features:
255 * In the special case of TM no suspend (P9N DD2.1), Linux is
256 * told TM is off via the dt-ftrs but told to (partially) use
257 * it via OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED. So HFSCR[TM]
258 * will be off from dt-ftrs but we need to turn it on for the
261 if (cpu_has_feature(CPU_FTR_HVMODE)) {
262 if (cpu_has_feature(CPU_FTR_TM_COMP))
263 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) | HFSCR_TM);
265 mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
268 /* Set IR and DR in PACA MSR */
269 get_paca()->kernel_msr = MSR_KERNEL;
272 unsigned long spr_default_dscr = 0;
274 static void __init record_spr_defaults(void)
276 if (early_cpu_has_feature(CPU_FTR_DSCR))
277 spr_default_dscr = mfspr(SPRN_DSCR);
281 * Early initialization entry point. This is called by head.S
282 * with MMU translation disabled. We rely on the "feature" of
283 * the CPU that ignores the top 2 bits of the address in real
284 * mode so we can access kernel globals normally provided we
285 * only toy with things in the RMO region. From here, we do
286 * some early parsing of the device-tree to setup out MEMBLOCK
287 * data structures, and allocate & initialize the hash table
288 * and segment tables so we can start running with translation
291 * It is this function which will call the probe() callback of
292 * the various platform types and copy the matching one to the
293 * global ppc_md structure. Your platform can eventually do
294 * some very early initializations from the probe() routine, but
295 * this is not recommended, be very careful as, for example, the
296 * device-tree is not accessible via normal means at this point.
299 void __init early_setup(unsigned long dt_ptr)
301 static __initdata struct paca_struct boot_paca;
303 /* -------- printk is _NOT_ safe to use here ! ------- */
306 * Assume we're on cpu 0 for now.
308 * We need to load a PACA very early for a few reasons.
310 * The stack protector canary is stored in the paca, so as soon as we
311 * call any stack protected code we need r13 pointing somewhere valid.
313 * If we are using kcov it will call in_task() in its instrumentation,
314 * which relies on the current task from the PACA.
316 * dt_cpu_ftrs_init() calls into generic OF/fdt code, as well as
317 * printk(), which can trigger both stack protector and kcov.
319 * percpu variables and spin locks also use the paca.
321 * So set up a temporary paca. It will be replaced below once we know
322 * what CPU we are on.
324 initialise_paca(&boot_paca, 0);
325 setup_paca(&boot_paca);
328 /* -------- printk is now safe to use ------- */
330 /* Try new device tree based feature discovery ... */
331 if (!dt_cpu_ftrs_init(__va(dt_ptr)))
332 /* Otherwise use the old style CPU table */
333 identify_cpu(0, mfspr(SPRN_PVR));
335 /* Enable early debugging if any specified (see udbg.h) */
338 udbg_printf(" -> %s(), dt_ptr: 0x%lx\n", __func__, dt_ptr);
341 * Do early initialization using the flattened device
342 * tree, such as retrieving the physical memory map or
343 * calculating/retrieving the hash table size.
345 early_init_devtree(__va(dt_ptr));
347 /* Now we know the logical id of our boot cpu, setup the paca. */
348 if (boot_cpuid != 0) {
349 /* Poison paca_ptrs[0] again if it's not the boot cpu */
350 memset(&paca_ptrs[0], 0x88, sizeof(paca_ptrs[0]));
352 setup_paca(paca_ptrs[boot_cpuid]);
356 * Configure exception handlers. This include setting up trampolines
357 * if needed, setting exception endian mode, etc...
359 configure_exceptions();
362 * Configure Kernel Userspace Protection. This needs to happen before
363 * feature fixups for platforms that implement this using features.
367 /* Apply all the dynamic patching */
368 apply_feature_fixups();
369 setup_feature_keys();
371 /* Initialize the hash table or TLB handling */
374 early_ioremap_setup();
377 * After firmware and early platform setup code has set things up,
378 * we note the SPR values for configurable control/performance
379 * registers, and use those as initial defaults.
381 record_spr_defaults();
384 * At this point, we can let interrupts switch to virtual mode
385 * (the MMU has been setup), so adjust the MSR in the PACA to
386 * have IR and DR set and enable AIL if it exists
388 cpu_ready_for_interrupts();
391 * We enable ftrace here, but since we only support DYNAMIC_FTRACE, it
392 * will only actually get enabled on the boot cpu much later once
393 * ftrace itself has been initialized.
395 this_cpu_enable_ftrace();
397 udbg_printf(" <- %s()\n", __func__);
399 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
401 * This needs to be done *last* (after the above udbg_printf() even)
403 * Right after we return from this function, we turn on the MMU
404 * which means the real-mode access trick that btext does will
405 * no longer work, it needs to switch to using a real MMU
406 * mapping. This call will ensure that it does
409 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
413 void early_setup_secondary(void)
415 /* Mark interrupts disabled in PACA */
416 irq_soft_mask_set(IRQS_DISABLED);
418 /* Initialize the hash table or TLB handling */
419 early_init_mmu_secondary();
421 /* Perform any KUP setup that is per-cpu */
425 * At this point, we can let interrupts switch to virtual mode
426 * (the MMU has been setup), so adjust the MSR in the PACA to
427 * have IR and DR set.
429 cpu_ready_for_interrupts();
432 #endif /* CONFIG_SMP */
434 void panic_smp_self_stop(void)
442 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
443 static bool use_spinloop(void)
445 if (IS_ENABLED(CONFIG_PPC_BOOK3S)) {
447 * See comments in head_64.S -- not all platforms insert
448 * secondaries at __secondary_hold and wait at the spin
451 if (firmware_has_feature(FW_FEATURE_OPAL))
457 * When book3e boots from kexec, the ePAPR spin table does
460 return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
463 void smp_release_cpus(void)
471 /* All secondary cpus are spinning on a common spinloop, release them
472 * all now so they can start to spin on their individual paca
473 * spinloops. For non SMP kernels, the secondary cpus never get out
474 * of the common spinloop.
477 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
479 *ptr = ppc_function_entry(generic_secondary_smp_init);
481 /* And wait a bit for them to catch up */
482 for (i = 0; i < 100000; i++) {
485 if (spinning_secondaries == 0)
489 pr_debug("spinning_secondaries = %d\n", spinning_secondaries);
491 #endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
494 * Initialize some remaining members of the ppc64_caches and systemcfg
496 * (at least until we get rid of them completely). This is mostly some
497 * cache informations about the CPU that will be used by cache flush
498 * routines and/or provided to userland
501 static void __init init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
506 info->line_size = lsize;
507 info->block_size = bsize;
508 info->log_block_size = __ilog2(bsize);
510 info->blocks_per_page = PAGE_SIZE / bsize;
512 info->blocks_per_page = 0;
515 info->assoc = 0xffff;
517 info->assoc = size / (sets * lsize);
520 static bool __init parse_cache_info(struct device_node *np,
522 struct ppc_cache_info *info)
524 static const char *ipropnames[] __initdata = {
527 "i-cache-block-size",
530 static const char *dpropnames[] __initdata = {
533 "d-cache-block-size",
536 const char **propnames = icache ? ipropnames : dpropnames;
537 const __be32 *sizep, *lsizep, *bsizep, *setsp;
538 u32 size, lsize, bsize, sets;
543 lsize = bsize = cur_cpu_spec->dcache_bsize;
544 sizep = of_get_property(np, propnames[0], NULL);
546 size = be32_to_cpu(*sizep);
547 setsp = of_get_property(np, propnames[1], NULL);
549 sets = be32_to_cpu(*setsp);
550 bsizep = of_get_property(np, propnames[2], NULL);
551 lsizep = of_get_property(np, propnames[3], NULL);
557 lsize = be32_to_cpu(*lsizep);
559 bsize = be32_to_cpu(*bsizep);
560 if (sizep == NULL || bsizep == NULL || lsizep == NULL)
564 * OF is weird .. it represents fully associative caches
565 * as "1 way" which doesn't make much sense and doesn't
566 * leave room for direct mapped. We'll assume that 0
567 * in OF means direct mapped for that reason.
574 init_cache_info(info, size, lsize, bsize, sets);
579 void __init initialize_cache_info(void)
581 struct device_node *cpu = NULL, *l2, *l3 = NULL;
585 * All shipping POWER8 machines have a firmware bug that
586 * puts incorrect information in the device-tree. This will
587 * be (hopefully) fixed for future chips but for now hard
588 * code the values if we are running on one of these
590 pvr = PVR_VER(mfspr(SPRN_PVR));
591 if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
592 pvr == PVR_POWER8NVL) {
593 /* size lsize blk sets */
594 init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32);
595 init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64);
596 init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512);
597 init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192);
599 cpu = of_find_node_by_type(NULL, "cpu");
602 * We're assuming *all* of the CPUs have the same
603 * d-cache and i-cache sizes... -Peter
606 if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
607 pr_warn("Argh, can't find dcache properties !\n");
609 if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
610 pr_warn("Argh, can't find icache properties !\n");
613 * Try to find the L2 and L3 if any. Assume they are
614 * unified and use the D-side properties.
616 l2 = of_find_next_cache_node(cpu);
619 parse_cache_info(l2, false, &ppc64_caches.l2);
620 l3 = of_find_next_cache_node(l2);
624 parse_cache_info(l3, false, &ppc64_caches.l3);
629 /* For use by binfmt_elf */
630 dcache_bsize = ppc64_caches.l1d.block_size;
631 icache_bsize = ppc64_caches.l1i.block_size;
633 cur_cpu_spec->dcache_bsize = dcache_bsize;
634 cur_cpu_spec->icache_bsize = icache_bsize;
638 * This returns the limit below which memory accesses to the linear
639 * mapping are guarnateed not to cause an architectural exception (e.g.,
640 * TLB or SLB miss fault).
642 * This is used to allocate PACAs and various interrupt stacks that
643 * that are accessed early in interrupt handlers that must not cause
644 * re-entrant interrupts.
646 __init u64 ppc64_bolted_size(void)
648 #ifdef CONFIG_PPC_BOOK3E
649 /* Freescale BookE bolts the entire linear mapping */
650 /* XXX: BookE ppc64_rma_limit setup seems to disagree? */
651 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E))
652 return linear_map_top;
653 /* Other BookE, we assume the first GB is bolted */
656 /* BookS radix, does not take faults on linear mapping */
657 if (early_radix_enabled())
660 /* BookS hash, the first segment is bolted */
661 if (early_mmu_has_feature(MMU_FTR_1T_SEGMENT))
662 return 1UL << SID_SHIFT_1T;
663 return 1UL << SID_SHIFT;
667 static void *__init alloc_stack(unsigned long limit, int cpu)
671 BUILD_BUG_ON(STACK_INT_FRAME_SIZE % 16);
673 ptr = memblock_alloc_try_nid(THREAD_SIZE, THREAD_ALIGN,
674 MEMBLOCK_LOW_LIMIT, limit,
675 early_cpu_to_node(cpu));
677 panic("cannot allocate stacks");
682 void __init irqstack_early_init(void)
684 u64 limit = ppc64_bolted_size();
688 * Interrupt stacks must be in the first segment since we
689 * cannot afford to take SLB misses on them. They are not
690 * accessed in realmode.
692 for_each_possible_cpu(i) {
693 softirq_ctx[i] = alloc_stack(limit, i);
694 hardirq_ctx[i] = alloc_stack(limit, i);
698 #ifdef CONFIG_PPC_BOOK3E
699 void __init exc_lvl_early_init(void)
703 for_each_possible_cpu(i) {
706 sp = alloc_stack(ULONG_MAX, i);
708 paca_ptrs[i]->crit_kstack = sp + THREAD_SIZE;
710 sp = alloc_stack(ULONG_MAX, i);
712 paca_ptrs[i]->dbg_kstack = sp + THREAD_SIZE;
714 sp = alloc_stack(ULONG_MAX, i);
715 mcheckirq_ctx[i] = sp;
716 paca_ptrs[i]->mc_kstack = sp + THREAD_SIZE;
719 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
720 patch_exception(0x040, exc_debug_debug_book3e);
725 * Stack space used when we detect a bad kernel stack pointer, and
726 * early in SMP boots before relocation is enabled. Exclusive emergency
727 * stack for machine checks.
729 void __init emergency_stack_init(void)
731 u64 limit, mce_limit;
735 * Emergency stacks must be under 256MB, we cannot afford to take
736 * SLB misses on them. The ABI also requires them to be 128-byte
739 * Since we use these as temporary stacks during secondary CPU
740 * bringup, machine check, system reset, and HMI, we need to get
741 * at them in real mode. This means they must also be within the RMO
744 * The IRQ stacks allocated elsewhere in this file are zeroed and
745 * initialized in kernel/irq.c. These are initialized here in order
746 * to have emergency stacks available as early as possible.
748 limit = mce_limit = min(ppc64_bolted_size(), ppc64_rma_size);
751 * Machine check on pseries calls rtas, but can't use the static
752 * rtas_args due to a machine check hitting while the lock is held.
753 * rtas args have to be under 4GB, so the machine check stack is
754 * limited to 4GB so args can be put on stack.
756 if (firmware_has_feature(FW_FEATURE_LPAR) && mce_limit > SZ_4G)
759 for_each_possible_cpu(i) {
760 paca_ptrs[i]->emergency_sp = alloc_stack(limit, i) + THREAD_SIZE;
762 #ifdef CONFIG_PPC_BOOK3S_64
763 /* emergency stack for NMI exception handling. */
764 paca_ptrs[i]->nmi_emergency_sp = alloc_stack(limit, i) + THREAD_SIZE;
766 /* emergency stack for machine check exception handling. */
767 paca_ptrs[i]->mc_emergency_sp = alloc_stack(mce_limit, i) + THREAD_SIZE;
773 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
775 if (early_cpu_to_node(from) == early_cpu_to_node(to))
776 return LOCAL_DISTANCE;
778 return REMOTE_DISTANCE;
781 static __init int pcpu_cpu_to_node(int cpu)
783 return early_cpu_to_node(cpu);
786 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
787 EXPORT_SYMBOL(__per_cpu_offset);
789 void __init setup_per_cpu_areas(void)
791 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
798 * BookE and BookS radix are historical values and should be revisited.
800 if (IS_ENABLED(CONFIG_PPC_BOOK3E)) {
802 } else if (radix_enabled()) {
803 atom_size = PAGE_SIZE;
804 } else if (IS_ENABLED(CONFIG_PPC_64S_HASH_MMU)) {
806 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
807 * to group units. For larger mappings, use 1M atom which
808 * should be large enough to contain a number of units.
810 if (mmu_linear_psize == MMU_PAGE_4K)
811 atom_size = PAGE_SIZE;
816 if (pcpu_chosen_fc != PCPU_FC_PAGE) {
817 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
820 pr_warn("PERCPU: %s allocator failed (%d), "
821 "falling back to page size\n",
822 pcpu_fc_names[pcpu_chosen_fc], rc);
826 rc = pcpu_page_first_chunk(0, pcpu_cpu_to_node);
828 panic("cannot initialize percpu area (err=%d)", rc);
830 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
831 for_each_possible_cpu(cpu) {
832 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
833 paca_ptrs[cpu]->data_offset = __per_cpu_offset[cpu];
838 #ifdef CONFIG_MEMORY_HOTPLUG
839 unsigned long memory_block_size_bytes(void)
841 if (ppc_md.memory_block_size)
842 return ppc_md.memory_block_size();
844 return MIN_MEMORY_BLOCK_SIZE;
848 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
849 struct ppc_pci_io ppc_pci_io;
850 EXPORT_SYMBOL(ppc_pci_io);
853 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
854 u64 hw_nmi_get_sample_period(int watchdog_thresh)
856 return ppc_proc_freq * watchdog_thresh;
861 * The perf based hardlockup detector breaks PMU event based branches, so
862 * disable it by default. Book3S has a soft-nmi hardlockup detector based
863 * on the decrementer interrupt, so it does not suffer from this problem.
865 * It is likely to get false positives in KVM guests, so disable it there
866 * by default too. PowerVM will not stop or arbitrarily oversubscribe
867 * CPUs, but give a minimum regular allotment even with SPLPAR, so enable
868 * the detector for non-KVM guests, assume PowerVM.
870 static int __init disable_hardlockup_detector(void)
872 #ifdef CONFIG_HARDLOCKUP_DETECTOR_PERF
873 hardlockup_detector_disable();
875 if (firmware_has_feature(FW_FEATURE_LPAR)) {
877 hardlockup_detector_disable();
883 early_initcall(disable_hardlockup_detector);