3 * Common boot and setup code.
5 * Copyright (C) 2001 PPC64 Team, IBM Corp
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
15 #include <linux/export.h>
16 #include <linux/string.h>
17 #include <linux/sched.h>
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/reboot.h>
21 #include <linux/delay.h>
22 #include <linux/initrd.h>
23 #include <linux/seq_file.h>
24 #include <linux/ioport.h>
25 #include <linux/console.h>
26 #include <linux/utsname.h>
27 #include <linux/tty.h>
28 #include <linux/root_dev.h>
29 #include <linux/notifier.h>
30 #include <linux/cpu.h>
31 #include <linux/unistd.h>
32 #include <linux/serial.h>
33 #include <linux/serial_8250.h>
34 #include <linux/bootmem.h>
35 #include <linux/pci.h>
36 #include <linux/lockdep.h>
37 #include <linux/memblock.h>
38 #include <linux/hugetlb.h>
39 #include <linux/memory.h>
40 #include <linux/nmi.h>
43 #include <asm/kdump.h>
45 #include <asm/processor.h>
46 #include <asm/pgtable.h>
49 #include <asm/machdep.h>
52 #include <asm/cputable.h>
53 #include <asm/sections.h>
54 #include <asm/btext.h>
55 #include <asm/nvram.h>
56 #include <asm/setup.h>
58 #include <asm/iommu.h>
59 #include <asm/serial.h>
60 #include <asm/cache.h>
63 #include <asm/firmware.h>
66 #include <asm/kexec.h>
67 #include <asm/mmu_context.h>
68 #include <asm/code-patching.h>
69 #include <asm/kvm_ppc.h>
70 #include <asm/hugetlb.h>
71 #include <asm/epapr_hcalls.h>
74 #define DBG(fmt...) udbg_printf(fmt)
79 int spinning_secondaries;
82 /* Pick defaults since we might want to patch instructions
83 * before we've read this from the device tree.
85 struct ppc64_caches ppc64_caches = {
91 EXPORT_SYMBOL_GPL(ppc64_caches);
94 * These are used in binfmt_elf.c to put aux entries on the stack
95 * for each elf executable being started.
101 #if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
102 static void setup_tlb_core_data(void)
106 BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
108 for_each_possible_cpu(cpu) {
109 int first = cpu_first_thread_sibling(cpu);
112 * If we boot via kdump on a non-primary thread,
113 * make sure we point at the thread that actually
116 if (cpu_first_thread_sibling(boot_cpuid) == first)
119 paca[cpu].tcd_ptr = &paca[first].tcd;
122 * If we have threads, we need either tlbsrx.
123 * or e6500 tablewalk mode, or else TLB handlers
124 * will be racy and could produce duplicate entries.
126 if (smt_enabled_at_boot >= 2 &&
127 !mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
128 book3e_htw_mode != PPC_HTW_E6500) {
129 /* Should we panic instead? */
130 WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n",
136 static void setup_tlb_core_data(void)
143 static char *smt_enabled_cmdline;
145 /* Look for ibm,smt-enabled OF option */
146 static void check_smt_enabled(void)
148 struct device_node *dn;
149 const char *smt_option;
151 /* Default to enabling all threads */
152 smt_enabled_at_boot = threads_per_core;
154 /* Allow the command line to overrule the OF option */
155 if (smt_enabled_cmdline) {
156 if (!strcmp(smt_enabled_cmdline, "on"))
157 smt_enabled_at_boot = threads_per_core;
158 else if (!strcmp(smt_enabled_cmdline, "off"))
159 smt_enabled_at_boot = 0;
164 rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
166 smt_enabled_at_boot =
167 min(threads_per_core, smt);
170 dn = of_find_node_by_path("/options");
172 smt_option = of_get_property(dn, "ibm,smt-enabled",
176 if (!strcmp(smt_option, "on"))
177 smt_enabled_at_boot = threads_per_core;
178 else if (!strcmp(smt_option, "off"))
179 smt_enabled_at_boot = 0;
187 /* Look for smt-enabled= cmdline option */
188 static int __init early_smt_enabled(char *p)
190 smt_enabled_cmdline = p;
193 early_param("smt-enabled", early_smt_enabled);
196 #define check_smt_enabled()
197 #endif /* CONFIG_SMP */
199 /** Fix up paca fields required for the boot cpu */
200 static void fixup_boot_paca(void)
202 /* The boot cpu is started */
203 get_paca()->cpu_start = 1;
204 /* Allow percpu accesses to work until we setup percpu data */
205 get_paca()->data_offset = 0;
208 static void cpu_ready_for_interrupts(void)
210 /* Set IR and DR in PACA MSR */
211 get_paca()->kernel_msr = MSR_KERNEL;
214 * Enable AIL if supported, and we are in hypervisor mode. If we are
215 * not in hypervisor mode, we enable relocation-on interrupts later
216 * in pSeries_setup_arch() using the H_SET_MODE hcall.
218 if (cpu_has_feature(CPU_FTR_HVMODE) &&
219 cpu_has_feature(CPU_FTR_ARCH_207S)) {
220 unsigned long lpcr = mfspr(SPRN_LPCR);
221 mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
226 * Early initialization entry point. This is called by head.S
227 * with MMU translation disabled. We rely on the "feature" of
228 * the CPU that ignores the top 2 bits of the address in real
229 * mode so we can access kernel globals normally provided we
230 * only toy with things in the RMO region. From here, we do
231 * some early parsing of the device-tree to setup out MEMBLOCK
232 * data structures, and allocate & initialize the hash table
233 * and segment tables so we can start running with translation
236 * It is this function which will call the probe() callback of
237 * the various platform types and copy the matching one to the
238 * global ppc_md structure. Your platform can eventually do
239 * some very early initializations from the probe() routine, but
240 * this is not recommended, be very careful as, for example, the
241 * device-tree is not accessible via normal means at this point.
244 void __init early_setup(unsigned long dt_ptr)
246 static __initdata struct paca_struct boot_paca;
248 /* -------- printk is _NOT_ safe to use here ! ------- */
250 /* Identify CPU type */
251 identify_cpu(0, mfspr(SPRN_PVR));
253 /* Assume we're on cpu 0 for now. Don't write to the paca yet! */
254 initialise_paca(&boot_paca, 0);
255 setup_paca(&boot_paca);
258 /* Initialize lockdep early or else spinlocks will blow */
261 /* -------- printk is now safe to use ------- */
263 /* Enable early debugging if any specified (see udbg.h) */
266 DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
269 * Do early initialization using the flattened device
270 * tree, such as retrieving the physical memory map or
271 * calculating/retrieving the hash table size.
273 early_init_devtree(__va(dt_ptr));
275 epapr_paravirt_early_init();
277 /* Now we know the logical id of our boot cpu, setup the paca. */
278 setup_paca(&paca[boot_cpuid]);
281 /* Probe the machine type */
284 setup_kdump_trampoline();
286 DBG("Found, Initializing memory management...\n");
288 /* Initialize the hash table or TLB handling */
292 * At this point, we can let interrupts switch to virtual mode
293 * (the MMU has been setup), so adjust the MSR in the PACA to
294 * have IR and DR set and enable AIL if it exists
296 cpu_ready_for_interrupts();
298 /* Reserve large chunks of memory for use by CMA for KVM */
302 * Reserve any gigantic pages requested on the command line.
303 * memblock needs to have been initialized by the time this is
304 * called since this will reserve memory.
306 reserve_hugetlb_gpages();
308 DBG(" <- early_setup()\n");
310 #ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
312 * This needs to be done *last* (after the above DBG() even)
314 * Right after we return from this function, we turn on the MMU
315 * which means the real-mode access trick that btext does will
316 * no longer work, it needs to switch to using a real MMU
317 * mapping. This call will ensure that it does
320 #endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
324 void early_setup_secondary(void)
326 /* Mark interrupts enabled in PACA */
327 get_paca()->soft_enabled = 0;
329 /* Initialize the hash table or TLB handling */
330 early_init_mmu_secondary();
333 * At this point, we can let interrupts switch to virtual mode
334 * (the MMU has been setup), so adjust the MSR in the PACA to
335 * have IR and DR set.
337 cpu_ready_for_interrupts();
340 #endif /* CONFIG_SMP */
342 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
343 void smp_release_cpus(void)
348 DBG(" -> smp_release_cpus()\n");
350 /* All secondary cpus are spinning on a common spinloop, release them
351 * all now so they can start to spin on their individual paca
352 * spinloops. For non SMP kernels, the secondary cpus never get out
353 * of the common spinloop.
356 ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
358 *ptr = ppc_function_entry(generic_secondary_smp_init);
360 /* And wait a bit for them to catch up */
361 for (i = 0; i < 100000; i++) {
364 if (spinning_secondaries == 0)
368 DBG("spinning_secondaries = %d\n", spinning_secondaries);
370 DBG(" <- smp_release_cpus()\n");
372 #endif /* CONFIG_SMP || CONFIG_KEXEC */
375 * Initialize some remaining members of the ppc64_caches and systemcfg
377 * (at least until we get rid of them completely). This is mostly some
378 * cache informations about the CPU that will be used by cache flush
379 * routines and/or provided to userland
381 static void __init initialize_cache_info(void)
383 struct device_node *np;
384 unsigned long num_cpus = 0;
386 DBG(" -> initialize_cache_info()\n");
388 for_each_node_by_type(np, "cpu") {
392 * We're assuming *all* of the CPUs have the same
393 * d-cache and i-cache sizes... -Peter
396 const __be32 *sizep, *lsizep;
400 lsize = cur_cpu_spec->dcache_bsize;
401 sizep = of_get_property(np, "d-cache-size", NULL);
403 size = be32_to_cpu(*sizep);
404 lsizep = of_get_property(np, "d-cache-block-size",
406 /* fallback if block size missing */
408 lsizep = of_get_property(np,
412 lsize = be32_to_cpu(*lsizep);
413 if (sizep == NULL || lsizep == NULL)
414 DBG("Argh, can't find dcache properties ! "
415 "sizep: %p, lsizep: %p\n", sizep, lsizep);
417 ppc64_caches.dsize = size;
418 ppc64_caches.dline_size = lsize;
419 ppc64_caches.log_dline_size = __ilog2(lsize);
420 ppc64_caches.dlines_per_page = PAGE_SIZE / lsize;
423 lsize = cur_cpu_spec->icache_bsize;
424 sizep = of_get_property(np, "i-cache-size", NULL);
426 size = be32_to_cpu(*sizep);
427 lsizep = of_get_property(np, "i-cache-block-size",
430 lsizep = of_get_property(np,
434 lsize = be32_to_cpu(*lsizep);
435 if (sizep == NULL || lsizep == NULL)
436 DBG("Argh, can't find icache properties ! "
437 "sizep: %p, lsizep: %p\n", sizep, lsizep);
439 ppc64_caches.isize = size;
440 ppc64_caches.iline_size = lsize;
441 ppc64_caches.log_iline_size = __ilog2(lsize);
442 ppc64_caches.ilines_per_page = PAGE_SIZE / lsize;
446 DBG(" <- initialize_cache_info()\n");
451 * Do some initial setup of the system. The parameters are those which
452 * were passed in from the bootloader.
454 void __init setup_system(void)
456 DBG(" -> setup_system()\n");
458 /* Apply the CPUs-specific and firmware specific fixups to kernel
459 * text (nop out sections not relevant to this CPU or this firmware)
461 do_feature_fixups(cur_cpu_spec->cpu_features,
462 &__start___ftr_fixup, &__stop___ftr_fixup);
463 do_feature_fixups(cur_cpu_spec->mmu_features,
464 &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup);
465 do_feature_fixups(powerpc_firmware_features,
466 &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup);
467 do_lwsync_fixups(cur_cpu_spec->cpu_features,
468 &__start___lwsync_fixup, &__stop___lwsync_fixup);
472 * Unflatten the device-tree passed by prom_init or kexec
474 unflatten_device_tree();
477 * Fill the ppc64_caches & systemcfg structures with informations
478 * retrieved from the device-tree.
480 initialize_cache_info();
482 #ifdef CONFIG_PPC_RTAS
484 * Initialize RTAS if available
487 #endif /* CONFIG_PPC_RTAS */
490 * Check if we have an initrd provided via the device-tree
495 * Do some platform specific early initializations, that includes
496 * setting up the hash table pointers. It also sets up some interrupt-mapping
497 * related options that will be used by finish_device_tree()
499 if (ppc_md.init_early)
503 * We can discover serial ports now since the above did setup the
504 * hash table management for us, thus ioremap works. We do that early
505 * so that further code can be debugged
507 find_legacy_serial_ports();
510 * Register early console
512 register_early_udbg_console();
519 smp_setup_cpu_maps();
521 setup_tlb_core_data();
524 * Freescale Book3e parts spin in a loop provided by firmware,
525 * so smp_release_cpus() does nothing for them
527 #if defined(CONFIG_SMP) && !defined(CONFIG_PPC_FSL_BOOK3E)
528 /* Release secondary cpus out of their spinloops at 0x60 now that
529 * we can map physical -> logical CPU ids
534 pr_info("Starting Linux %s %s\n", init_utsname()->machine,
535 init_utsname()->version);
537 pr_info("-----------------------------------------------------\n");
538 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
539 pr_info("phys_mem_size = 0x%llx\n", memblock_phys_mem_size());
541 if (ppc64_caches.dline_size != 0x80)
542 pr_info("dcache_line_size = 0x%x\n", ppc64_caches.dline_size);
543 if (ppc64_caches.iline_size != 0x80)
544 pr_info("icache_line_size = 0x%x\n", ppc64_caches.iline_size);
546 pr_info("cpu_features = 0x%016lx\n", cur_cpu_spec->cpu_features);
547 pr_info(" possible = 0x%016lx\n", CPU_FTRS_POSSIBLE);
548 pr_info(" always = 0x%016lx\n", CPU_FTRS_ALWAYS);
549 pr_info("cpu_user_features = 0x%08x 0x%08x\n", cur_cpu_spec->cpu_user_features,
550 cur_cpu_spec->cpu_user_features2);
551 pr_info("mmu_features = 0x%08x\n", cur_cpu_spec->mmu_features);
552 pr_info("firmware_features = 0x%016lx\n", powerpc_firmware_features);
554 #ifdef CONFIG_PPC_STD_MMU_64
556 pr_info("htab_address = 0x%p\n", htab_address);
558 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask);
561 if (PHYSICAL_START > 0)
562 pr_info("physical_start = 0x%llx\n",
563 (unsigned long long)PHYSICAL_START);
564 pr_info("-----------------------------------------------------\n");
566 DBG(" <- setup_system()\n");
569 /* This returns the limit below which memory accesses to the linear
570 * mapping are guarnateed not to cause a TLB or SLB miss. This is
571 * used to allocate interrupt or emergency stacks for which our
572 * exception entry path doesn't deal with being interrupted.
574 static u64 safe_stack_limit(void)
576 #ifdef CONFIG_PPC_BOOK3E
577 /* Freescale BookE bolts the entire linear mapping */
578 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
579 return linear_map_top;
580 /* Other BookE, we assume the first GB is bolted */
583 /* BookS, the first segment is bolted */
584 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
585 return 1UL << SID_SHIFT_1T;
586 return 1UL << SID_SHIFT;
590 static void __init irqstack_early_init(void)
592 u64 limit = safe_stack_limit();
596 * Interrupt stacks must be in the first segment since we
597 * cannot afford to take SLB misses on them.
599 for_each_possible_cpu(i) {
600 softirq_ctx[i] = (struct thread_info *)
601 __va(memblock_alloc_base(THREAD_SIZE,
602 THREAD_SIZE, limit));
603 hardirq_ctx[i] = (struct thread_info *)
604 __va(memblock_alloc_base(THREAD_SIZE,
605 THREAD_SIZE, limit));
609 #ifdef CONFIG_PPC_BOOK3E
610 static void __init exc_lvl_early_init(void)
615 for_each_possible_cpu(i) {
616 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
617 critirq_ctx[i] = (struct thread_info *)__va(sp);
618 paca[i].crit_kstack = __va(sp + THREAD_SIZE);
620 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
621 dbgirq_ctx[i] = (struct thread_info *)__va(sp);
622 paca[i].dbg_kstack = __va(sp + THREAD_SIZE);
624 sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
625 mcheckirq_ctx[i] = (struct thread_info *)__va(sp);
626 paca[i].mc_kstack = __va(sp + THREAD_SIZE);
629 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
630 patch_exception(0x040, exc_debug_debug_book3e);
633 #define exc_lvl_early_init()
637 * Stack space used when we detect a bad kernel stack pointer, and
638 * early in SMP boots before relocation is enabled. Exclusive emergency
639 * stack for machine checks.
641 static void __init emergency_stack_init(void)
647 * Emergency stacks must be under 256MB, we cannot afford to take
648 * SLB misses on them. The ABI also requires them to be 128-byte
651 * Since we use these as temporary stacks during secondary CPU
652 * bringup, we need to get at them in real mode. This means they
653 * must also be within the RMO region.
655 limit = min(safe_stack_limit(), ppc64_rma_size);
657 for_each_possible_cpu(i) {
659 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
661 paca[i].emergency_sp = __va(sp);
663 #ifdef CONFIG_PPC_BOOK3S_64
664 /* emergency stack for machine check exception handling. */
665 sp = memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit);
667 paca[i].mc_emergency_sp = __va(sp);
673 * Called into from start_kernel this initializes memblock, which is used
674 * to manage page allocation until mem_init is called.
676 void __init setup_arch(char **cmdline_p)
678 *cmdline_p = boot_command_line;
681 * Set cache line size based on type of cpu as a default.
682 * Systems with OF can look in the properties on the cpu node(s)
683 * for a possibly more accurate value.
685 dcache_bsize = ppc64_caches.dline_size;
686 icache_bsize = ppc64_caches.iline_size;
691 init_mm.start_code = (unsigned long)_stext;
692 init_mm.end_code = (unsigned long) _etext;
693 init_mm.end_data = (unsigned long) _edata;
694 init_mm.brk = klimit;
695 #ifdef CONFIG_PPC_64K_PAGES
696 init_mm.context.pte_frag = NULL;
698 #ifdef CONFIG_SPAPR_TCE_IOMMU
699 mm_iommu_init(&init_mm.context);
701 irqstack_early_init();
702 exc_lvl_early_init();
703 emergency_stack_init();
707 #ifdef CONFIG_DUMMY_CONSOLE
708 conswitchp = &dummy_con;
711 if (ppc_md.setup_arch)
716 /* Initialize the MMU context management stuff */
719 /* Interrupt code needs to be 64K-aligned */
720 if ((unsigned long)_stext & 0xffff)
721 panic("Kernelbase not 64K-aligned (0x%lx)!\n",
722 (unsigned long)_stext);
726 #define PCPU_DYN_SIZE ()
728 static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
730 return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align,
731 __pa(MAX_DMA_ADDRESS));
734 static void __init pcpu_fc_free(void *ptr, size_t size)
736 free_bootmem(__pa(ptr), size);
739 static int pcpu_cpu_distance(unsigned int from, unsigned int to)
741 if (cpu_to_node(from) == cpu_to_node(to))
742 return LOCAL_DISTANCE;
744 return REMOTE_DISTANCE;
747 unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
748 EXPORT_SYMBOL(__per_cpu_offset);
750 void __init setup_per_cpu_areas(void)
752 const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
759 * Linear mapping is one of 4K, 1M and 16M. For 4K, no need
760 * to group units. For larger mappings, use 1M atom which
761 * should be large enough to contain a number of units.
763 if (mmu_linear_psize == MMU_PAGE_4K)
764 atom_size = PAGE_SIZE;
768 rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
769 pcpu_fc_alloc, pcpu_fc_free);
771 panic("cannot initialize percpu area (err=%d)", rc);
773 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
774 for_each_possible_cpu(cpu) {
775 __per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
776 paca[cpu].data_offset = __per_cpu_offset[cpu];
781 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
782 unsigned long memory_block_size_bytes(void)
784 if (ppc_md.memory_block_size)
785 return ppc_md.memory_block_size();
787 return MIN_MEMORY_BLOCK_SIZE;
791 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
792 struct ppc_pci_io ppc_pci_io;
793 EXPORT_SYMBOL(ppc_pci_io);
796 #ifdef CONFIG_HARDLOCKUP_DETECTOR
797 u64 hw_nmi_get_sample_period(int watchdog_thresh)
799 return ppc_proc_freq * watchdog_thresh;
803 * The hardlockup detector breaks PMU event based branches and is likely
804 * to get false positives in KVM guests, so disable it by default.
806 static int __init disable_hardlockup_detector(void)
808 hardlockup_detector_disable();
812 early_initcall(disable_hardlockup_detector);