1 // SPDX-License-Identifier: GPL-2.0+
3 // Security related flags and so on.
5 // Copyright 2018, Michael Ellerman, IBM Corporation.
7 #include <linux/kernel.h>
8 #include <linux/device.h>
9 #include <linux/seq_buf.h>
11 #include <asm/asm-prototypes.h>
12 #include <asm/code-patching.h>
13 #include <asm/debugfs.h>
14 #include <asm/security_features.h>
15 #include <asm/setup.h>
18 unsigned long powerpc_security_features __read_mostly = SEC_FTR_DEFAULT;
20 enum count_cache_flush_type {
21 COUNT_CACHE_FLUSH_NONE = 0x1,
22 COUNT_CACHE_FLUSH_SW = 0x2,
23 COUNT_CACHE_FLUSH_HW = 0x4,
25 static enum count_cache_flush_type count_cache_flush_type;
27 bool barrier_nospec_enabled;
28 static bool no_nospec;
30 static void enable_barrier_nospec(bool enable)
32 barrier_nospec_enabled = enable;
33 do_barrier_nospec_fixups(enable);
36 void setup_barrier_nospec(void)
41 * It would make sense to check SEC_FTR_SPEC_BAR_ORI31 below as well.
42 * But there's a good reason not to. The two flags we check below are
43 * both are enabled by default in the kernel, so if the hcall is not
44 * functional they will be enabled.
45 * On a system where the host firmware has been updated (so the ori
46 * functions as a barrier), but on which the hypervisor (KVM/Qemu) has
47 * not been updated, we would like to enable the barrier. Dropping the
48 * check for SEC_FTR_SPEC_BAR_ORI31 achieves that. The only downside is
49 * we potentially enable the barrier on systems where the host firmware
50 * is not updated, but that's harmless as it's a no-op.
52 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
53 security_ftr_enabled(SEC_FTR_BNDS_CHK_SPEC_BAR);
56 enable_barrier_nospec(enable);
59 static int __init handle_nospectre_v1(char *p)
65 early_param("nospectre_v1", handle_nospectre_v1);
67 #ifdef CONFIG_DEBUG_FS
68 static int barrier_nospec_set(void *data, u64 val)
78 if (!!val == !!barrier_nospec_enabled)
81 enable_barrier_nospec(!!val);
86 static int barrier_nospec_get(void *data, u64 *val)
88 *val = barrier_nospec_enabled ? 1 : 0;
92 DEFINE_SIMPLE_ATTRIBUTE(fops_barrier_nospec,
93 barrier_nospec_get, barrier_nospec_set, "%llu\n");
95 static __init int barrier_nospec_debugfs_init(void)
97 debugfs_create_file("barrier_nospec", 0600, powerpc_debugfs_root, NULL,
98 &fops_barrier_nospec);
101 device_initcall(barrier_nospec_debugfs_init);
102 #endif /* CONFIG_DEBUG_FS */
104 #ifdef CONFIG_PPC_BOOK3S_64
105 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
109 thread_priv = security_ftr_enabled(SEC_FTR_L1D_THREAD_PRIV);
111 if (rfi_flush || thread_priv) {
113 seq_buf_init(&s, buf, PAGE_SIZE - 1);
115 seq_buf_printf(&s, "Mitigation: ");
118 seq_buf_printf(&s, "RFI Flush");
120 if (rfi_flush && thread_priv)
121 seq_buf_printf(&s, ", ");
124 seq_buf_printf(&s, "L1D private per thread");
126 seq_buf_printf(&s, "\n");
131 if (!security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV) &&
132 !security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR))
133 return sprintf(buf, "Not affected\n");
135 return sprintf(buf, "Vulnerable\n");
139 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
143 seq_buf_init(&s, buf, PAGE_SIZE - 1);
145 if (security_ftr_enabled(SEC_FTR_BNDS_CHK_SPEC_BAR)) {
146 if (barrier_nospec_enabled)
147 seq_buf_printf(&s, "Mitigation: __user pointer sanitization");
149 seq_buf_printf(&s, "Vulnerable");
151 if (security_ftr_enabled(SEC_FTR_SPEC_BAR_ORI31))
152 seq_buf_printf(&s, ", ori31 speculation barrier enabled");
154 seq_buf_printf(&s, "\n");
156 seq_buf_printf(&s, "Not affected\n");
161 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
166 seq_buf_init(&s, buf, PAGE_SIZE - 1);
168 bcs = security_ftr_enabled(SEC_FTR_BCCTRL_SERIALISED);
169 ccd = security_ftr_enabled(SEC_FTR_COUNT_CACHE_DISABLED);
171 if (bcs || ccd || count_cache_flush_type != COUNT_CACHE_FLUSH_NONE) {
173 seq_buf_printf(&s, "Mitigation: ");
176 seq_buf_printf(&s, "Indirect branch serialisation (kernel only)");
182 seq_buf_printf(&s, ", ");
183 seq_buf_printf(&s, "Indirect branch cache disabled");
188 seq_buf_printf(&s, ", ");
190 seq_buf_printf(&s, "Software count cache flush");
192 if (count_cache_flush_type == COUNT_CACHE_FLUSH_HW)
193 seq_buf_printf(&s, "(hardware accelerated)");
195 seq_buf_printf(&s, "Vulnerable");
197 seq_buf_printf(&s, "\n");
202 #ifdef CONFIG_PPC_BOOK3S_64
204 * Store-forwarding barrier support.
207 static enum stf_barrier_type stf_enabled_flush_types;
208 static bool no_stf_barrier;
211 static int __init handle_no_stf_barrier(char *p)
213 pr_info("stf-barrier: disabled on command line.");
214 no_stf_barrier = true;
218 early_param("no_stf_barrier", handle_no_stf_barrier);
220 /* This is the generic flag used by other architectures */
221 static int __init handle_ssbd(char *p)
223 if (!p || strncmp(p, "auto", 5) == 0 || strncmp(p, "on", 2) == 0 ) {
224 /* Until firmware tells us, we have the barrier with auto */
226 } else if (strncmp(p, "off", 3) == 0) {
227 handle_no_stf_barrier(NULL);
234 early_param("spec_store_bypass_disable", handle_ssbd);
236 /* This is the generic flag used by other architectures */
237 static int __init handle_no_ssbd(char *p)
239 handle_no_stf_barrier(NULL);
242 early_param("nospec_store_bypass_disable", handle_no_ssbd);
244 static void stf_barrier_enable(bool enable)
247 do_stf_barrier_fixups(stf_enabled_flush_types);
249 do_stf_barrier_fixups(STF_BARRIER_NONE);
251 stf_barrier = enable;
254 void setup_stf_barrier(void)
256 enum stf_barrier_type type;
259 hv = cpu_has_feature(CPU_FTR_HVMODE);
261 /* Default to fallback in case fw-features are not available */
262 if (cpu_has_feature(CPU_FTR_ARCH_300))
263 type = STF_BARRIER_EIEIO;
264 else if (cpu_has_feature(CPU_FTR_ARCH_207S))
265 type = STF_BARRIER_SYNC_ORI;
266 else if (cpu_has_feature(CPU_FTR_ARCH_206))
267 type = STF_BARRIER_FALLBACK;
269 type = STF_BARRIER_NONE;
271 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
272 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR) ||
273 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV) && hv));
275 if (type == STF_BARRIER_FALLBACK) {
276 pr_info("stf-barrier: fallback barrier available\n");
277 } else if (type == STF_BARRIER_SYNC_ORI) {
278 pr_info("stf-barrier: hwsync barrier available\n");
279 } else if (type == STF_BARRIER_EIEIO) {
280 pr_info("stf-barrier: eieio barrier available\n");
283 stf_enabled_flush_types = type;
286 stf_barrier_enable(enable);
289 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
291 if (stf_barrier && stf_enabled_flush_types != STF_BARRIER_NONE) {
293 switch (stf_enabled_flush_types) {
294 case STF_BARRIER_EIEIO:
297 case STF_BARRIER_SYNC_ORI:
300 case STF_BARRIER_FALLBACK:
306 return sprintf(buf, "Mitigation: Kernel entry/exit barrier (%s)\n", type);
309 if (!security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV) &&
310 !security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR))
311 return sprintf(buf, "Not affected\n");
313 return sprintf(buf, "Vulnerable\n");
316 #ifdef CONFIG_DEBUG_FS
317 static int stf_barrier_set(void *data, u64 val)
328 /* Only do anything if we're changing state */
329 if (enable != stf_barrier)
330 stf_barrier_enable(enable);
335 static int stf_barrier_get(void *data, u64 *val)
337 *val = stf_barrier ? 1 : 0;
341 DEFINE_SIMPLE_ATTRIBUTE(fops_stf_barrier, stf_barrier_get, stf_barrier_set, "%llu\n");
343 static __init int stf_barrier_debugfs_init(void)
345 debugfs_create_file("stf_barrier", 0600, powerpc_debugfs_root, NULL, &fops_stf_barrier);
348 device_initcall(stf_barrier_debugfs_init);
349 #endif /* CONFIG_DEBUG_FS */
351 static void toggle_count_cache_flush(bool enable)
353 if (!enable || !security_ftr_enabled(SEC_FTR_FLUSH_COUNT_CACHE)) {
354 patch_instruction_site(&patch__call_flush_count_cache, PPC_INST_NOP);
355 count_cache_flush_type = COUNT_CACHE_FLUSH_NONE;
356 pr_info("count-cache-flush: software flush disabled.\n");
360 patch_branch_site(&patch__call_flush_count_cache,
361 (u64)&flush_count_cache, BRANCH_SET_LINK);
363 if (!security_ftr_enabled(SEC_FTR_BCCTR_FLUSH_ASSIST)) {
364 count_cache_flush_type = COUNT_CACHE_FLUSH_SW;
365 pr_info("count-cache-flush: full software flush sequence enabled.\n");
369 patch_instruction_site(&patch__flush_count_cache_return, PPC_INST_BLR);
370 count_cache_flush_type = COUNT_CACHE_FLUSH_HW;
371 pr_info("count-cache-flush: hardware assisted flush sequence enabled\n");
374 void setup_count_cache_flush(void)
376 toggle_count_cache_flush(true);
379 #ifdef CONFIG_DEBUG_FS
380 static int count_cache_flush_set(void *data, u64 val)
391 toggle_count_cache_flush(enable);
396 static int count_cache_flush_get(void *data, u64 *val)
398 if (count_cache_flush_type == COUNT_CACHE_FLUSH_NONE)
406 DEFINE_SIMPLE_ATTRIBUTE(fops_count_cache_flush, count_cache_flush_get,
407 count_cache_flush_set, "%llu\n");
409 static __init int count_cache_flush_debugfs_init(void)
411 debugfs_create_file("count_cache_flush", 0600, powerpc_debugfs_root,
412 NULL, &fops_count_cache_flush);
415 device_initcall(count_cache_flush_debugfs_init);
416 #endif /* CONFIG_DEBUG_FS */
417 #endif /* CONFIG_PPC_BOOK3S_64 */