1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Derived from "arch/i386/kernel/process.c"
4 * Copyright (C) 1995 Linus Torvalds
6 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
7 * Paul Mackerras (paulus@cs.anu.edu.au)
10 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
13 #include <linux/errno.h>
14 #include <linux/sched.h>
15 #include <linux/sched/debug.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/task_stack.h>
18 #include <linux/kernel.h>
20 #include <linux/smp.h>
21 #include <linux/stddef.h>
22 #include <linux/unistd.h>
23 #include <linux/ptrace.h>
24 #include <linux/slab.h>
25 #include <linux/user.h>
26 #include <linux/elf.h>
27 #include <linux/prctl.h>
28 #include <linux/init_task.h>
29 #include <linux/export.h>
30 #include <linux/kallsyms.h>
31 #include <linux/mqueue.h>
32 #include <linux/hardirq.h>
33 #include <linux/utsname.h>
34 #include <linux/ftrace.h>
35 #include <linux/kernel_stat.h>
36 #include <linux/personality.h>
37 #include <linux/random.h>
38 #include <linux/hw_breakpoint.h>
39 #include <linux/uaccess.h>
40 #include <linux/elf-randomize.h>
41 #include <linux/pkeys.h>
42 #include <linux/seq_buf.h>
44 #include <asm/pgtable.h>
46 #include <asm/processor.h>
49 #include <asm/machdep.h>
51 #include <asm/runlatch.h>
52 #include <asm/syscalls.h>
53 #include <asm/switch_to.h>
55 #include <asm/debug.h>
57 #include <asm/firmware.h>
58 #include <asm/hw_irq.h>
60 #include <asm/code-patching.h>
62 #include <asm/livepatch.h>
63 #include <asm/cpu_has_feature.h>
64 #include <asm/asm-prototypes.h>
65 #include <asm/stacktrace.h>
66 #include <asm/hw_breakpoint.h>
68 #include <linux/kprobes.h>
69 #include <linux/kdebug.h>
71 /* Transactional Memory debug */
73 #define TM_DEBUG(x...) printk(KERN_INFO x)
75 #define TM_DEBUG(x...) do { } while(0)
78 extern unsigned long _get_SP(void);
80 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
82 * Are we running in "Suspend disabled" mode? If so we have to block any
83 * sigreturn that would get us into suspended state, and we also warn in some
84 * other paths that we should never reach with suspend disabled.
86 bool tm_suspend_disabled __ro_after_init = false;
88 static void check_if_tm_restore_required(struct task_struct *tsk)
91 * If we are saving the current thread's registers, and the
92 * thread is in a transactional state, set the TIF_RESTORE_TM
93 * bit so that we know to restore the registers before
94 * returning to userspace.
96 if (tsk == current && tsk->thread.regs &&
97 MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
98 !test_thread_flag(TIF_RESTORE_TM)) {
99 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
100 set_thread_flag(TIF_RESTORE_TM);
105 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
106 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
108 bool strict_msr_control;
109 EXPORT_SYMBOL(strict_msr_control);
111 static int __init enable_strict_msr_control(char *str)
113 strict_msr_control = true;
114 pr_info("Enabling strict facility control\n");
118 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
120 /* notrace because it's called by restore_math */
121 unsigned long notrace msr_check_and_set(unsigned long bits)
123 unsigned long oldmsr = mfmsr();
124 unsigned long newmsr;
126 newmsr = oldmsr | bits;
129 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
133 if (oldmsr != newmsr)
138 EXPORT_SYMBOL_GPL(msr_check_and_set);
140 /* notrace because it's called by restore_math */
141 void notrace __msr_check_and_clear(unsigned long bits)
143 unsigned long oldmsr = mfmsr();
144 unsigned long newmsr;
146 newmsr = oldmsr & ~bits;
149 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
153 if (oldmsr != newmsr)
156 EXPORT_SYMBOL(__msr_check_and_clear);
158 #ifdef CONFIG_PPC_FPU
159 static void __giveup_fpu(struct task_struct *tsk)
164 msr = tsk->thread.regs->msr;
165 msr &= ~(MSR_FP|MSR_FE0|MSR_FE1);
167 if (cpu_has_feature(CPU_FTR_VSX))
170 tsk->thread.regs->msr = msr;
173 void giveup_fpu(struct task_struct *tsk)
175 check_if_tm_restore_required(tsk);
177 msr_check_and_set(MSR_FP);
179 msr_check_and_clear(MSR_FP);
181 EXPORT_SYMBOL(giveup_fpu);
184 * Make sure the floating-point register state in the
185 * the thread_struct is up to date for task tsk.
187 void flush_fp_to_thread(struct task_struct *tsk)
189 if (tsk->thread.regs) {
191 * We need to disable preemption here because if we didn't,
192 * another process could get scheduled after the regs->msr
193 * test but before we have finished saving the FP registers
194 * to the thread_struct. That process could take over the
195 * FPU, and then when we get scheduled again we would store
196 * bogus values for the remaining FP registers.
199 if (tsk->thread.regs->msr & MSR_FP) {
201 * This should only ever be called for current or
202 * for a stopped child process. Since we save away
203 * the FP register state on context switch,
204 * there is something wrong if a stopped child appears
205 * to still have its FP state in the CPU registers.
207 BUG_ON(tsk != current);
213 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
215 void enable_kernel_fp(void)
217 unsigned long cpumsr;
219 WARN_ON(preemptible());
221 cpumsr = msr_check_and_set(MSR_FP);
223 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
224 check_if_tm_restore_required(current);
226 * If a thread has already been reclaimed then the
227 * checkpointed registers are on the CPU but have definitely
228 * been saved by the reclaim code. Don't need to and *cannot*
229 * giveup as this would save to the 'live' structure not the
230 * checkpointed structure.
232 if (!MSR_TM_ACTIVE(cpumsr) &&
233 MSR_TM_ACTIVE(current->thread.regs->msr))
235 __giveup_fpu(current);
238 EXPORT_SYMBOL(enable_kernel_fp);
239 #endif /* CONFIG_PPC_FPU */
241 #ifdef CONFIG_ALTIVEC
242 static void __giveup_altivec(struct task_struct *tsk)
247 msr = tsk->thread.regs->msr;
250 if (cpu_has_feature(CPU_FTR_VSX))
253 tsk->thread.regs->msr = msr;
256 void giveup_altivec(struct task_struct *tsk)
258 check_if_tm_restore_required(tsk);
260 msr_check_and_set(MSR_VEC);
261 __giveup_altivec(tsk);
262 msr_check_and_clear(MSR_VEC);
264 EXPORT_SYMBOL(giveup_altivec);
266 void enable_kernel_altivec(void)
268 unsigned long cpumsr;
270 WARN_ON(preemptible());
272 cpumsr = msr_check_and_set(MSR_VEC);
274 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
275 check_if_tm_restore_required(current);
277 * If a thread has already been reclaimed then the
278 * checkpointed registers are on the CPU but have definitely
279 * been saved by the reclaim code. Don't need to and *cannot*
280 * giveup as this would save to the 'live' structure not the
281 * checkpointed structure.
283 if (!MSR_TM_ACTIVE(cpumsr) &&
284 MSR_TM_ACTIVE(current->thread.regs->msr))
286 __giveup_altivec(current);
289 EXPORT_SYMBOL(enable_kernel_altivec);
292 * Make sure the VMX/Altivec register state in the
293 * the thread_struct is up to date for task tsk.
295 void flush_altivec_to_thread(struct task_struct *tsk)
297 if (tsk->thread.regs) {
299 if (tsk->thread.regs->msr & MSR_VEC) {
300 BUG_ON(tsk != current);
306 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
307 #endif /* CONFIG_ALTIVEC */
310 static void __giveup_vsx(struct task_struct *tsk)
312 unsigned long msr = tsk->thread.regs->msr;
315 * We should never be ssetting MSR_VSX without also setting
318 WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC)));
320 /* __giveup_fpu will clear MSR_VSX */
324 __giveup_altivec(tsk);
327 static void giveup_vsx(struct task_struct *tsk)
329 check_if_tm_restore_required(tsk);
331 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
333 msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
336 void enable_kernel_vsx(void)
338 unsigned long cpumsr;
340 WARN_ON(preemptible());
342 cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
344 if (current->thread.regs &&
345 (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) {
346 check_if_tm_restore_required(current);
348 * If a thread has already been reclaimed then the
349 * checkpointed registers are on the CPU but have definitely
350 * been saved by the reclaim code. Don't need to and *cannot*
351 * giveup as this would save to the 'live' structure not the
352 * checkpointed structure.
354 if (!MSR_TM_ACTIVE(cpumsr) &&
355 MSR_TM_ACTIVE(current->thread.regs->msr))
357 __giveup_vsx(current);
360 EXPORT_SYMBOL(enable_kernel_vsx);
362 void flush_vsx_to_thread(struct task_struct *tsk)
364 if (tsk->thread.regs) {
366 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) {
367 BUG_ON(tsk != current);
373 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
374 #endif /* CONFIG_VSX */
377 void giveup_spe(struct task_struct *tsk)
379 check_if_tm_restore_required(tsk);
381 msr_check_and_set(MSR_SPE);
383 msr_check_and_clear(MSR_SPE);
385 EXPORT_SYMBOL(giveup_spe);
387 void enable_kernel_spe(void)
389 WARN_ON(preemptible());
391 msr_check_and_set(MSR_SPE);
393 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
394 check_if_tm_restore_required(current);
395 __giveup_spe(current);
398 EXPORT_SYMBOL(enable_kernel_spe);
400 void flush_spe_to_thread(struct task_struct *tsk)
402 if (tsk->thread.regs) {
404 if (tsk->thread.regs->msr & MSR_SPE) {
405 BUG_ON(tsk != current);
406 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
412 #endif /* CONFIG_SPE */
414 static unsigned long msr_all_available;
416 static int __init init_msr_all_available(void)
418 #ifdef CONFIG_PPC_FPU
419 msr_all_available |= MSR_FP;
421 #ifdef CONFIG_ALTIVEC
422 if (cpu_has_feature(CPU_FTR_ALTIVEC))
423 msr_all_available |= MSR_VEC;
426 if (cpu_has_feature(CPU_FTR_VSX))
427 msr_all_available |= MSR_VSX;
430 if (cpu_has_feature(CPU_FTR_SPE))
431 msr_all_available |= MSR_SPE;
436 early_initcall(init_msr_all_available);
438 void giveup_all(struct task_struct *tsk)
440 unsigned long usermsr;
442 if (!tsk->thread.regs)
445 check_if_tm_restore_required(tsk);
447 usermsr = tsk->thread.regs->msr;
449 if ((usermsr & msr_all_available) == 0)
452 msr_check_and_set(msr_all_available);
454 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
456 #ifdef CONFIG_PPC_FPU
457 if (usermsr & MSR_FP)
460 #ifdef CONFIG_ALTIVEC
461 if (usermsr & MSR_VEC)
462 __giveup_altivec(tsk);
465 if (usermsr & MSR_SPE)
469 msr_check_and_clear(msr_all_available);
471 EXPORT_SYMBOL(giveup_all);
473 #ifdef CONFIG_PPC_BOOK3S_64
474 #ifdef CONFIG_PPC_FPU
475 static int restore_fp(struct task_struct *tsk)
477 if (tsk->thread.load_fp) {
478 load_fp_state(¤t->thread.fp_state);
479 current->thread.load_fp++;
485 static int restore_fp(struct task_struct *tsk) { return 0; }
486 #endif /* CONFIG_PPC_FPU */
488 #ifdef CONFIG_ALTIVEC
489 #define loadvec(thr) ((thr).load_vec)
490 static int restore_altivec(struct task_struct *tsk)
492 if (cpu_has_feature(CPU_FTR_ALTIVEC) && (tsk->thread.load_vec)) {
493 load_vr_state(&tsk->thread.vr_state);
494 tsk->thread.used_vr = 1;
495 tsk->thread.load_vec++;
502 #define loadvec(thr) 0
503 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
504 #endif /* CONFIG_ALTIVEC */
507 static int restore_vsx(struct task_struct *tsk)
509 if (cpu_has_feature(CPU_FTR_VSX)) {
510 tsk->thread.used_vsr = 1;
517 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
518 #endif /* CONFIG_VSX */
521 * The exception exit path calls restore_math() with interrupts hard disabled
522 * but the soft irq state not "reconciled". ftrace code that calls
523 * local_irq_save/restore causes warnings.
525 * Rather than complicate the exit path, just don't trace restore_math. This
526 * could be done by having ftrace entry code check for this un-reconciled
527 * condition where MSR[EE]=0 and PACA_IRQ_HARD_DIS is not set, and
528 * temporarily fix it up for the duration of the ftrace call.
530 void notrace restore_math(struct pt_regs *regs)
534 if (!MSR_TM_ACTIVE(regs->msr) &&
535 !current->thread.load_fp && !loadvec(current->thread))
539 msr_check_and_set(msr_all_available);
542 * Only reload if the bit is not set in the user MSR, the bit BEING set
543 * indicates that the registers are hot
545 if ((!(msr & MSR_FP)) && restore_fp(current))
546 msr |= MSR_FP | current->thread.fpexc_mode;
548 if ((!(msr & MSR_VEC)) && restore_altivec(current))
551 if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
552 restore_vsx(current)) {
556 msr_check_and_clear(msr_all_available);
562 static void save_all(struct task_struct *tsk)
564 unsigned long usermsr;
566 if (!tsk->thread.regs)
569 usermsr = tsk->thread.regs->msr;
571 if ((usermsr & msr_all_available) == 0)
574 msr_check_and_set(msr_all_available);
576 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
578 if (usermsr & MSR_FP)
581 if (usermsr & MSR_VEC)
584 if (usermsr & MSR_SPE)
587 msr_check_and_clear(msr_all_available);
588 thread_pkey_regs_save(&tsk->thread);
591 void flush_all_to_thread(struct task_struct *tsk)
593 if (tsk->thread.regs) {
595 BUG_ON(tsk != current);
597 if (tsk->thread.regs->msr & MSR_SPE)
598 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
605 EXPORT_SYMBOL(flush_all_to_thread);
607 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
608 void do_send_trap(struct pt_regs *regs, unsigned long address,
609 unsigned long error_code, int breakpt)
611 current->thread.trap_nr = TRAP_HWBKPT;
612 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
613 11, SIGSEGV) == NOTIFY_STOP)
616 /* Deliver the signal to userspace */
617 force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */
618 (void __user *)address);
620 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
621 void do_break (struct pt_regs *regs, unsigned long address,
622 unsigned long error_code)
624 current->thread.trap_nr = TRAP_HWBKPT;
625 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
626 11, SIGSEGV) == NOTIFY_STOP)
629 if (debugger_break_match(regs))
632 /* Clear the breakpoint */
633 hw_breakpoint_disable();
635 /* Deliver the signal to userspace */
636 force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)address);
638 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
640 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
642 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
644 * Set the debug registers back to their default "safe" values.
646 static void set_debug_reg_defaults(struct thread_struct *thread)
648 thread->debug.iac1 = thread->debug.iac2 = 0;
649 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
650 thread->debug.iac3 = thread->debug.iac4 = 0;
652 thread->debug.dac1 = thread->debug.dac2 = 0;
653 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
654 thread->debug.dvc1 = thread->debug.dvc2 = 0;
656 thread->debug.dbcr0 = 0;
659 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
661 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
662 DBCR1_IAC3US | DBCR1_IAC4US;
664 * Force Data Address Compare User/Supervisor bits to be User-only
665 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
667 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
669 thread->debug.dbcr1 = 0;
673 static void prime_debug_regs(struct debug_reg *debug)
676 * We could have inherited MSR_DE from userspace, since
677 * it doesn't get cleared on exception entry. Make sure
678 * MSR_DE is clear before we enable any debug events.
680 mtmsr(mfmsr() & ~MSR_DE);
682 mtspr(SPRN_IAC1, debug->iac1);
683 mtspr(SPRN_IAC2, debug->iac2);
684 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
685 mtspr(SPRN_IAC3, debug->iac3);
686 mtspr(SPRN_IAC4, debug->iac4);
688 mtspr(SPRN_DAC1, debug->dac1);
689 mtspr(SPRN_DAC2, debug->dac2);
690 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
691 mtspr(SPRN_DVC1, debug->dvc1);
692 mtspr(SPRN_DVC2, debug->dvc2);
694 mtspr(SPRN_DBCR0, debug->dbcr0);
695 mtspr(SPRN_DBCR1, debug->dbcr1);
697 mtspr(SPRN_DBCR2, debug->dbcr2);
701 * Unless neither the old or new thread are making use of the
702 * debug registers, set the debug registers from the values
703 * stored in the new thread.
705 void switch_booke_debug_regs(struct debug_reg *new_debug)
707 if ((current->thread.debug.dbcr0 & DBCR0_IDM)
708 || (new_debug->dbcr0 & DBCR0_IDM))
709 prime_debug_regs(new_debug);
711 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
712 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
713 #ifndef CONFIG_HAVE_HW_BREAKPOINT
714 static void set_breakpoint(struct arch_hw_breakpoint *brk)
717 __set_breakpoint(brk);
721 static void set_debug_reg_defaults(struct thread_struct *thread)
723 thread->hw_brk.address = 0;
724 thread->hw_brk.type = 0;
725 thread->hw_brk.len = 0;
726 thread->hw_brk.hw_len = 0;
727 if (ppc_breakpoint_available())
728 set_breakpoint(&thread->hw_brk);
730 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
731 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
733 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
734 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
736 mtspr(SPRN_DAC1, dabr);
737 #ifdef CONFIG_PPC_47x
742 #elif defined(CONFIG_PPC_BOOK3S)
743 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
745 mtspr(SPRN_DABR, dabr);
746 if (cpu_has_feature(CPU_FTR_DABRX))
747 mtspr(SPRN_DABRX, dabrx);
751 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
757 static inline int set_dabr(struct arch_hw_breakpoint *brk)
759 unsigned long dabr, dabrx;
761 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
762 dabrx = ((brk->type >> 3) & 0x7);
765 return ppc_md.set_dabr(dabr, dabrx);
767 return __set_dabr(dabr, dabrx);
770 static inline int set_breakpoint_8xx(struct arch_hw_breakpoint *brk)
772 unsigned long lctrl1 = LCTRL1_CTE_GT | LCTRL1_CTF_LT | LCTRL1_CRWE_RW |
774 unsigned long lctrl2 = LCTRL2_LW0EN | LCTRL2_LW0LADC | LCTRL2_SLW0EN;
775 unsigned long start_addr = brk->address & ~HW_BREAKPOINT_ALIGN;
776 unsigned long end_addr = (brk->address + brk->len - 1) | HW_BREAKPOINT_ALIGN;
779 lctrl2 |= LCTRL2_LW0LA_F;
780 else if (end_addr == ~0U)
781 lctrl2 |= LCTRL2_LW0LA_E;
783 lctrl2 |= LCTRL2_LW0LA_EandF;
785 mtspr(SPRN_LCTRL2, 0);
787 if ((brk->type & HW_BRK_TYPE_RDWR) == 0)
790 if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
791 lctrl1 |= LCTRL1_CRWE_RO | LCTRL1_CRWF_RO;
792 if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
793 lctrl1 |= LCTRL1_CRWE_WO | LCTRL1_CRWF_WO;
795 mtspr(SPRN_CMPE, start_addr - 1);
796 mtspr(SPRN_CMPF, end_addr + 1);
797 mtspr(SPRN_LCTRL1, lctrl1);
798 mtspr(SPRN_LCTRL2, lctrl2);
803 void __set_breakpoint(struct arch_hw_breakpoint *brk)
805 memcpy(this_cpu_ptr(¤t_brk), brk, sizeof(*brk));
810 else if (IS_ENABLED(CONFIG_PPC_8xx))
811 set_breakpoint_8xx(brk);
812 else if (!cpu_has_feature(CPU_FTR_ARCH_207S))
816 // Shouldn't happen due to higher level checks
820 /* Check if we have DAWR or DABR hardware */
821 bool ppc_breakpoint_available(void)
824 return true; /* POWER8 DAWR or POWER9 forced DAWR */
825 if (cpu_has_feature(CPU_FTR_ARCH_207S))
826 return false; /* POWER9 with DAWR disabled */
827 /* DABR: Everything but POWER8 and POWER9 */
830 EXPORT_SYMBOL_GPL(ppc_breakpoint_available);
832 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
833 struct arch_hw_breakpoint *b)
835 if (a->address != b->address)
837 if (a->type != b->type)
839 if (a->len != b->len)
841 /* no need to check hw_len. it's calculated from address and len */
845 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
847 static inline bool tm_enabled(struct task_struct *tsk)
849 return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
852 static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause)
855 * Use the current MSR TM suspended bit to track if we have
856 * checkpointed state outstanding.
857 * On signal delivery, we'd normally reclaim the checkpointed
858 * state to obtain stack pointer (see:get_tm_stackpointer()).
859 * This will then directly return to userspace without going
860 * through __switch_to(). However, if the stack frame is bad,
861 * we need to exit this thread which calls __switch_to() which
862 * will again attempt to reclaim the already saved tm state.
863 * Hence we need to check that we've not already reclaimed
865 * We do this using the current MSR, rather tracking it in
866 * some specific thread_struct bit, as it has the additional
867 * benefit of checking for a potential TM bad thing exception.
869 if (!MSR_TM_SUSPENDED(mfmsr()))
872 giveup_all(container_of(thr, struct task_struct, thread));
874 tm_reclaim(thr, cause);
877 * If we are in a transaction and FP is off then we can't have
878 * used FP inside that transaction. Hence the checkpointed
879 * state is the same as the live state. We need to copy the
880 * live state to the checkpointed state so that when the
881 * transaction is restored, the checkpointed state is correct
882 * and the aborted transaction sees the correct state. We use
883 * ckpt_regs.msr here as that's what tm_reclaim will use to
884 * determine if it's going to write the checkpointed state or
885 * not. So either this will write the checkpointed registers,
886 * or reclaim will. Similarly for VMX.
888 if ((thr->ckpt_regs.msr & MSR_FP) == 0)
889 memcpy(&thr->ckfp_state, &thr->fp_state,
890 sizeof(struct thread_fp_state));
891 if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
892 memcpy(&thr->ckvr_state, &thr->vr_state,
893 sizeof(struct thread_vr_state));
896 void tm_reclaim_current(uint8_t cause)
899 tm_reclaim_thread(¤t->thread, cause);
902 static inline void tm_reclaim_task(struct task_struct *tsk)
904 /* We have to work out if we're switching from/to a task that's in the
905 * middle of a transaction.
907 * In switching we need to maintain a 2nd register state as
908 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
909 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
912 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
914 struct thread_struct *thr = &tsk->thread;
919 if (!MSR_TM_ACTIVE(thr->regs->msr))
920 goto out_and_saveregs;
922 WARN_ON(tm_suspend_disabled);
924 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
925 "ccr=%lx, msr=%lx, trap=%lx)\n",
926 tsk->pid, thr->regs->nip,
927 thr->regs->ccr, thr->regs->msr,
930 tm_reclaim_thread(thr, TM_CAUSE_RESCHED);
932 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
936 /* Always save the regs here, even if a transaction's not active.
937 * This context-switches a thread's TM info SPRs. We do it here to
938 * be consistent with the restore path (in recheckpoint) which
939 * cannot happen later in _switch().
944 extern void __tm_recheckpoint(struct thread_struct *thread);
946 void tm_recheckpoint(struct thread_struct *thread)
950 if (!(thread->regs->msr & MSR_TM))
953 /* We really can't be interrupted here as the TEXASR registers can't
954 * change and later in the trecheckpoint code, we have a userspace R1.
955 * So let's hard disable over this region.
957 local_irq_save(flags);
960 /* The TM SPRs are restored here, so that TEXASR.FS can be set
961 * before the trecheckpoint and no explosion occurs.
963 tm_restore_sprs(thread);
965 __tm_recheckpoint(thread);
967 local_irq_restore(flags);
970 static inline void tm_recheckpoint_new_task(struct task_struct *new)
972 if (!cpu_has_feature(CPU_FTR_TM))
975 /* Recheckpoint the registers of the thread we're about to switch to.
977 * If the task was using FP, we non-lazily reload both the original and
978 * the speculative FP register states. This is because the kernel
979 * doesn't see if/when a TM rollback occurs, so if we take an FP
980 * unavailable later, we are unable to determine which set of FP regs
981 * need to be restored.
983 if (!tm_enabled(new))
986 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
987 tm_restore_sprs(&new->thread);
990 /* Recheckpoint to restore original checkpointed register state. */
991 TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
992 new->pid, new->thread.regs->msr);
994 tm_recheckpoint(&new->thread);
997 * The checkpointed state has been restored but the live state has
998 * not, ensure all the math functionality is turned off to trigger
999 * restore_math() to reload.
1001 new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
1003 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1004 "(kernel msr 0x%lx)\n",
1008 static inline void __switch_to_tm(struct task_struct *prev,
1009 struct task_struct *new)
1011 if (cpu_has_feature(CPU_FTR_TM)) {
1012 if (tm_enabled(prev) || tm_enabled(new))
1015 if (tm_enabled(prev)) {
1016 prev->thread.load_tm++;
1017 tm_reclaim_task(prev);
1018 if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
1019 prev->thread.regs->msr &= ~MSR_TM;
1022 tm_recheckpoint_new_task(new);
1027 * This is called if we are on the way out to userspace and the
1028 * TIF_RESTORE_TM flag is set. It checks if we need to reload
1029 * FP and/or vector state and does so if necessary.
1030 * If userspace is inside a transaction (whether active or
1031 * suspended) and FP/VMX/VSX instructions have ever been enabled
1032 * inside that transaction, then we have to keep them enabled
1033 * and keep the FP/VMX/VSX state loaded while ever the transaction
1034 * continues. The reason is that if we didn't, and subsequently
1035 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1036 * we don't know whether it's the same transaction, and thus we
1037 * don't know which of the checkpointed state and the transactional
1040 void restore_tm_state(struct pt_regs *regs)
1042 unsigned long msr_diff;
1045 * This is the only moment we should clear TIF_RESTORE_TM as
1046 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1047 * again, anything else could lead to an incorrect ckpt_msr being
1048 * saved and therefore incorrect signal contexts.
1050 clear_thread_flag(TIF_RESTORE_TM);
1051 if (!MSR_TM_ACTIVE(regs->msr))
1054 msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1055 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1057 /* Ensure that restore_math() will restore */
1058 if (msr_diff & MSR_FP)
1059 current->thread.load_fp = 1;
1060 #ifdef CONFIG_ALTIVEC
1061 if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1062 current->thread.load_vec = 1;
1066 regs->msr |= msr_diff;
1070 #define tm_recheckpoint_new_task(new)
1071 #define __switch_to_tm(prev, new)
1072 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1074 static inline void save_sprs(struct thread_struct *t)
1076 #ifdef CONFIG_ALTIVEC
1077 if (cpu_has_feature(CPU_FTR_ALTIVEC))
1078 t->vrsave = mfspr(SPRN_VRSAVE);
1080 #ifdef CONFIG_PPC_BOOK3S_64
1081 if (cpu_has_feature(CPU_FTR_DSCR))
1082 t->dscr = mfspr(SPRN_DSCR);
1084 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1085 t->bescr = mfspr(SPRN_BESCR);
1086 t->ebbhr = mfspr(SPRN_EBBHR);
1087 t->ebbrr = mfspr(SPRN_EBBRR);
1089 t->fscr = mfspr(SPRN_FSCR);
1092 * Note that the TAR is not available for use in the kernel.
1093 * (To provide this, the TAR should be backed up/restored on
1094 * exception entry/exit instead, and be in pt_regs. FIXME,
1095 * this should be in pt_regs anyway (for debug).)
1097 t->tar = mfspr(SPRN_TAR);
1101 thread_pkey_regs_save(t);
1104 static inline void restore_sprs(struct thread_struct *old_thread,
1105 struct thread_struct *new_thread)
1107 #ifdef CONFIG_ALTIVEC
1108 if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1109 old_thread->vrsave != new_thread->vrsave)
1110 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1112 #ifdef CONFIG_PPC_BOOK3S_64
1113 if (cpu_has_feature(CPU_FTR_DSCR)) {
1114 u64 dscr = get_paca()->dscr_default;
1115 if (new_thread->dscr_inherit)
1116 dscr = new_thread->dscr;
1118 if (old_thread->dscr != dscr)
1119 mtspr(SPRN_DSCR, dscr);
1122 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1123 if (old_thread->bescr != new_thread->bescr)
1124 mtspr(SPRN_BESCR, new_thread->bescr);
1125 if (old_thread->ebbhr != new_thread->ebbhr)
1126 mtspr(SPRN_EBBHR, new_thread->ebbhr);
1127 if (old_thread->ebbrr != new_thread->ebbrr)
1128 mtspr(SPRN_EBBRR, new_thread->ebbrr);
1130 if (old_thread->fscr != new_thread->fscr)
1131 mtspr(SPRN_FSCR, new_thread->fscr);
1133 if (old_thread->tar != new_thread->tar)
1134 mtspr(SPRN_TAR, new_thread->tar);
1137 if (cpu_has_feature(CPU_FTR_P9_TIDR) &&
1138 old_thread->tidr != new_thread->tidr)
1139 mtspr(SPRN_TIDR, new_thread->tidr);
1142 thread_pkey_regs_restore(new_thread, old_thread);
1145 struct task_struct *__switch_to(struct task_struct *prev,
1146 struct task_struct *new)
1148 struct thread_struct *new_thread, *old_thread;
1149 struct task_struct *last;
1150 #ifdef CONFIG_PPC_BOOK3S_64
1151 struct ppc64_tlb_batch *batch;
1154 new_thread = &new->thread;
1155 old_thread = ¤t->thread;
1157 WARN_ON(!irqs_disabled());
1159 #ifdef CONFIG_PPC_BOOK3S_64
1160 batch = this_cpu_ptr(&ppc64_tlb_batch);
1161 if (batch->active) {
1162 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1164 __flush_tlb_pending(batch);
1167 #endif /* CONFIG_PPC_BOOK3S_64 */
1169 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1170 switch_booke_debug_regs(&new->thread.debug);
1173 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1176 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1177 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk), &new->thread.hw_brk)))
1178 __set_breakpoint(&new->thread.hw_brk);
1179 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1183 * We need to save SPRs before treclaim/trecheckpoint as these will
1184 * change a number of them.
1186 save_sprs(&prev->thread);
1188 /* Save FPU, Altivec, VSX and SPE state */
1191 __switch_to_tm(prev, new);
1193 if (!radix_enabled()) {
1195 * We can't take a PMU exception inside _switch() since there
1196 * is a window where the kernel stack SLB and the kernel stack
1197 * are out of sync. Hard disable here.
1203 * Call restore_sprs() before calling _switch(). If we move it after
1204 * _switch() then we miss out on calling it for new tasks. The reason
1205 * for this is we manually create a stack frame for new tasks that
1206 * directly returns through ret_from_fork() or
1207 * ret_from_kernel_thread(). See copy_thread() for details.
1209 restore_sprs(old_thread, new_thread);
1211 last = _switch(old_thread, new_thread);
1213 #ifdef CONFIG_PPC_BOOK3S_64
1214 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1215 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1216 batch = this_cpu_ptr(&ppc64_tlb_batch);
1220 if (current->thread.regs) {
1221 restore_math(current->thread.regs);
1224 * The copy-paste buffer can only store into foreign real
1225 * addresses, so unprivileged processes can not see the
1226 * data or use it in any way unless they have foreign real
1227 * mappings. If the new process has the foreign real address
1228 * mappings, we must issue a cp_abort to clear any state and
1229 * prevent snooping, corruption or a covert channel.
1231 if (current->thread.used_vas)
1232 asm volatile(PPC_CP_ABORT);
1234 #endif /* CONFIG_PPC_BOOK3S_64 */
1239 #define NR_INSN_TO_PRINT 16
1241 static void show_instructions(struct pt_regs *regs)
1244 unsigned long pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1246 printk("Instruction dump:");
1248 for (i = 0; i < NR_INSN_TO_PRINT; i++) {
1254 #if !defined(CONFIG_BOOKE)
1255 /* If executing with the IMMU off, adjust pc rather
1256 * than print XXXXXXXX.
1258 if (!(regs->msr & MSR_IR))
1259 pc = (unsigned long)phys_to_virt(pc);
1262 if (!__kernel_text_address(pc) ||
1263 probe_kernel_address((const void *)pc, instr)) {
1264 pr_cont("XXXXXXXX ");
1266 if (regs->nip == pc)
1267 pr_cont("<%08x> ", instr);
1269 pr_cont("%08x ", instr);
1278 void show_user_instructions(struct pt_regs *regs)
1281 int n = NR_INSN_TO_PRINT;
1283 char buf[96]; /* enough for 8 times 9 + 2 chars */
1285 pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1287 seq_buf_init(&s, buf, sizeof(buf));
1294 for (i = 0; i < 8 && n; i++, n--, pc += sizeof(int)) {
1297 if (probe_user_read(&instr, (void __user *)pc, sizeof(instr))) {
1298 seq_buf_printf(&s, "XXXXXXXX ");
1301 seq_buf_printf(&s, regs->nip == pc ? "<%08x> " : "%08x ", instr);
1304 if (!seq_buf_has_overflowed(&s))
1305 pr_info("%s[%d]: code: %s\n", current->comm,
1306 current->pid, s.buffer);
1315 static struct regbit msr_bits[] = {
1316 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1338 #ifndef CONFIG_BOOKE
1345 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1349 for (; bits->bit; ++bits)
1350 if (val & bits->bit) {
1351 pr_cont("%s%s", s, bits->name);
1356 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1357 static struct regbit msr_tm_bits[] = {
1364 static void print_tm_bits(unsigned long val)
1367 * This only prints something if at least one of the TM bit is set.
1368 * Inside the TM[], the output means:
1369 * E: Enabled (bit 32)
1370 * S: Suspended (bit 33)
1371 * T: Transactional (bit 34)
1373 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1375 print_bits(val, msr_tm_bits, "");
1380 static void print_tm_bits(unsigned long val) {}
1383 static void print_msr_bits(unsigned long val)
1386 print_bits(val, msr_bits, ",");
1392 #define REG "%016lx"
1393 #define REGS_PER_LINE 4
1394 #define LAST_VOLATILE 13
1397 #define REGS_PER_LINE 8
1398 #define LAST_VOLATILE 12
1401 void show_regs(struct pt_regs * regs)
1405 show_regs_print_info(KERN_DEFAULT);
1407 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1408 regs->nip, regs->link, regs->ctr);
1409 printk("REGS: %px TRAP: %04lx %s (%s)\n",
1410 regs, regs->trap, print_tainted(), init_utsname()->release);
1411 printk("MSR: "REG" ", regs->msr);
1412 print_msr_bits(regs->msr);
1413 pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
1415 if ((TRAP(regs) != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1416 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1417 if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1418 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1419 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1421 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1424 pr_cont("IRQMASK: %lx ", regs->softe);
1426 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1427 if (MSR_TM_ACTIVE(regs->msr))
1428 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1431 for (i = 0; i < 32; i++) {
1432 if ((i % REGS_PER_LINE) == 0)
1433 pr_cont("\nGPR%02d: ", i);
1434 pr_cont(REG " ", regs->gpr[i]);
1435 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1439 #ifdef CONFIG_KALLSYMS
1441 * Lookup NIP late so we have the best change of getting the
1442 * above info out without failing
1444 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1445 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1447 show_stack(current, (unsigned long *) regs->gpr[1]);
1448 if (!user_mode(regs))
1449 show_instructions(regs);
1452 void flush_thread(void)
1454 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1455 flush_ptrace_hw_breakpoint(current);
1456 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1457 set_debug_reg_defaults(¤t->thread);
1458 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1461 #ifdef CONFIG_PPC_BOOK3S_64
1462 void arch_setup_new_exec(void)
1464 if (radix_enabled())
1466 hash__setup_new_exec();
1470 int set_thread_uses_vas(void)
1472 #ifdef CONFIG_PPC_BOOK3S_64
1473 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1476 current->thread.used_vas = 1;
1479 * Even a process that has no foreign real address mapping can use
1480 * an unpaired COPY instruction (to no real effect). Issue CP_ABORT
1481 * to clear any pending COPY and prevent a covert channel.
1483 * __switch_to() will issue CP_ABORT on future context switches.
1485 asm volatile(PPC_CP_ABORT);
1487 #endif /* CONFIG_PPC_BOOK3S_64 */
1493 * Assign a TIDR (thread ID) for task @t and set it in the thread
1494 * structure. For now, we only support setting TIDR for 'current' task.
1496 * Since the TID value is a truncated form of it PID, it is possible
1497 * (but unlikely) for 2 threads to have the same TID. In the unlikely event
1498 * that 2 threads share the same TID and are waiting, one of the following
1499 * cases will happen:
1501 * 1. The correct thread is running, the wrong thread is not
1502 * In this situation, the correct thread is woken and proceeds to pass it's
1505 * 2. Neither threads are running
1506 * In this situation, neither thread will be woken. When scheduled, the waiting
1507 * threads will execute either a wait, which will return immediately, followed
1508 * by a condition check, which will pass for the correct thread and fail
1509 * for the wrong thread, or they will execute the condition check immediately.
1511 * 3. The wrong thread is running, the correct thread is not
1512 * The wrong thread will be woken, but will fail it's condition check and
1513 * re-execute wait. The correct thread, when scheduled, will execute either
1514 * it's condition check (which will pass), or wait, which returns immediately
1515 * when called the first time after the thread is scheduled, followed by it's
1516 * condition check (which will pass).
1518 * 4. Both threads are running
1519 * Both threads will be woken. The wrong thread will fail it's condition check
1520 * and execute another wait, while the correct thread will pass it's condition
1523 * @t: the task to set the thread ID for
1525 int set_thread_tidr(struct task_struct *t)
1527 if (!cpu_has_feature(CPU_FTR_P9_TIDR))
1536 t->thread.tidr = (u16)task_pid_nr(t);
1537 mtspr(SPRN_TIDR, t->thread.tidr);
1541 EXPORT_SYMBOL_GPL(set_thread_tidr);
1543 #endif /* CONFIG_PPC64 */
1546 release_thread(struct task_struct *t)
1551 * this gets called so that we can store coprocessor state into memory and
1552 * copy the current task into the new thread.
1554 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1556 flush_all_to_thread(src);
1558 * Flush TM state out so we can copy it. __switch_to_tm() does this
1559 * flush but it removes the checkpointed state from the current CPU and
1560 * transitions the CPU out of TM mode. Hence we need to call
1561 * tm_recheckpoint_new_task() (on the same task) to restore the
1562 * checkpointed state back and the TM mode.
1564 * Can't pass dst because it isn't ready. Doesn't matter, passing
1565 * dst is only important for __switch_to()
1567 __switch_to_tm(src, src);
1571 clear_task_ebb(dst);
1576 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1578 #ifdef CONFIG_PPC_BOOK3S_64
1579 unsigned long sp_vsid;
1580 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1582 if (radix_enabled())
1585 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1586 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1587 << SLB_VSID_SHIFT_1T;
1589 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1591 sp_vsid |= SLB_VSID_KERNEL | llp;
1592 p->thread.ksp_vsid = sp_vsid;
1601 * Copy architecture-specific thread state
1603 int copy_thread_tls(unsigned long clone_flags, unsigned long usp,
1604 unsigned long kthread_arg, struct task_struct *p,
1607 struct pt_regs *childregs, *kregs;
1608 extern void ret_from_fork(void);
1609 extern void ret_from_kernel_thread(void);
1611 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1612 struct thread_info *ti = task_thread_info(p);
1614 klp_init_thread_info(p);
1616 /* Copy registers */
1617 sp -= sizeof(struct pt_regs);
1618 childregs = (struct pt_regs *) sp;
1619 if (unlikely(p->flags & PF_KTHREAD)) {
1621 memset(childregs, 0, sizeof(struct pt_regs));
1622 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1625 childregs->gpr[14] = ppc_function_entry((void *)usp);
1627 clear_tsk_thread_flag(p, TIF_32BIT);
1628 childregs->softe = IRQS_ENABLED;
1630 childregs->gpr[15] = kthread_arg;
1631 p->thread.regs = NULL; /* no user register state */
1632 ti->flags |= _TIF_RESTOREALL;
1633 f = ret_from_kernel_thread;
1636 struct pt_regs *regs = current_pt_regs();
1637 CHECK_FULL_REGS(regs);
1640 childregs->gpr[1] = usp;
1641 p->thread.regs = childregs;
1642 childregs->gpr[3] = 0; /* Result from fork() */
1643 if (clone_flags & CLONE_SETTLS) {
1644 if (!is_32bit_task())
1645 childregs->gpr[13] = tls;
1647 childregs->gpr[2] = tls;
1652 childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1653 sp -= STACK_FRAME_OVERHEAD;
1656 * The way this works is that at some point in the future
1657 * some task will call _switch to switch to the new task.
1658 * That will pop off the stack frame created below and start
1659 * the new task running at ret_from_fork. The new task will
1660 * do some house keeping and then return from the fork or clone
1661 * system call, using the stack frame created above.
1663 ((unsigned long *)sp)[0] = 0;
1664 sp -= sizeof(struct pt_regs);
1665 kregs = (struct pt_regs *) sp;
1666 sp -= STACK_FRAME_OVERHEAD;
1669 p->thread.ksp_limit = (unsigned long)end_of_stack(p);
1671 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1672 p->thread.ptrace_bps[0] = NULL;
1675 p->thread.fp_save_area = NULL;
1676 #ifdef CONFIG_ALTIVEC
1677 p->thread.vr_save_area = NULL;
1680 setup_ksp_vsid(p, sp);
1683 if (cpu_has_feature(CPU_FTR_DSCR)) {
1684 p->thread.dscr_inherit = current->thread.dscr_inherit;
1685 p->thread.dscr = mfspr(SPRN_DSCR);
1687 if (cpu_has_feature(CPU_FTR_HAS_PPR))
1688 childregs->ppr = DEFAULT_PPR;
1692 kregs->nip = ppc_function_entry(f);
1696 void preload_new_slb_context(unsigned long start, unsigned long sp);
1699 * Set up a thread for executing a new program
1701 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1704 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1706 #ifdef CONFIG_PPC_BOOK3S_64
1707 if (!radix_enabled())
1708 preload_new_slb_context(start, sp);
1713 * If we exec out of a kernel thread then thread.regs will not be
1716 if (!current->thread.regs) {
1717 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1718 current->thread.regs = regs - 1;
1721 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1723 * Clear any transactional state, we're exec()ing. The cause is
1724 * not important as there will never be a recheckpoint so it's not
1727 if (MSR_TM_SUSPENDED(mfmsr()))
1728 tm_reclaim_current(0);
1731 memset(regs->gpr, 0, sizeof(regs->gpr));
1739 * We have just cleared all the nonvolatile GPRs, so make
1740 * FULL_REGS(regs) return true. This is necessary to allow
1741 * ptrace to examine the thread immediately after exec.
1748 regs->msr = MSR_USER;
1750 if (!is_32bit_task()) {
1751 unsigned long entry;
1753 if (is_elf2_task()) {
1754 /* Look ma, no function descriptors! */
1759 * The latest iteration of the ABI requires that when
1760 * calling a function (at its global entry point),
1761 * the caller must ensure r12 holds the entry point
1762 * address (so that the function can quickly
1763 * establish addressability).
1765 regs->gpr[12] = start;
1766 /* Make sure that's restored on entry to userspace. */
1767 set_thread_flag(TIF_RESTOREALL);
1771 /* start is a relocated pointer to the function
1772 * descriptor for the elf _start routine. The first
1773 * entry in the function descriptor is the entry
1774 * address of _start and the second entry is the TOC
1775 * value we need to use.
1777 __get_user(entry, (unsigned long __user *)start);
1778 __get_user(toc, (unsigned long __user *)start+1);
1780 /* Check whether the e_entry function descriptor entries
1781 * need to be relocated before we can use them.
1783 if (load_addr != 0) {
1790 regs->msr = MSR_USER64;
1794 regs->msr = MSR_USER32;
1798 current->thread.used_vsr = 0;
1800 current->thread.load_slb = 0;
1801 current->thread.load_fp = 0;
1802 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state));
1803 current->thread.fp_save_area = NULL;
1804 #ifdef CONFIG_ALTIVEC
1805 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state));
1806 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1807 current->thread.vr_save_area = NULL;
1808 current->thread.vrsave = 0;
1809 current->thread.used_vr = 0;
1810 current->thread.load_vec = 0;
1811 #endif /* CONFIG_ALTIVEC */
1813 memset(current->thread.evr, 0, sizeof(current->thread.evr));
1814 current->thread.acc = 0;
1815 current->thread.spefscr = 0;
1816 current->thread.used_spe = 0;
1817 #endif /* CONFIG_SPE */
1818 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1819 current->thread.tm_tfhar = 0;
1820 current->thread.tm_texasr = 0;
1821 current->thread.tm_tfiar = 0;
1822 current->thread.load_tm = 0;
1823 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1825 thread_pkey_regs_init(¤t->thread);
1827 EXPORT_SYMBOL(start_thread);
1829 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1830 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1832 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1834 struct pt_regs *regs = tsk->thread.regs;
1836 /* This is a bit hairy. If we are an SPE enabled processor
1837 * (have embedded fp) we store the IEEE exception enable flags in
1838 * fpexc_mode. fpexc_mode is also used for setting FP exception
1839 * mode (asyn, precise, disabled) for 'Classic' FP. */
1840 if (val & PR_FP_EXC_SW_ENABLE) {
1842 if (cpu_has_feature(CPU_FTR_SPE)) {
1844 * When the sticky exception bits are set
1845 * directly by userspace, it must call prctl
1846 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1847 * in the existing prctl settings) or
1848 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1849 * the bits being set). <fenv.h> functions
1850 * saving and restoring the whole
1851 * floating-point environment need to do so
1852 * anyway to restore the prctl settings from
1853 * the saved environment.
1855 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1856 tsk->thread.fpexc_mode = val &
1857 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1867 /* on a CONFIG_SPE this does not hurt us. The bits that
1868 * __pack_fe01 use do not overlap with bits used for
1869 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1870 * on CONFIG_SPE implementations are reserved so writing to
1871 * them does not change anything */
1872 if (val > PR_FP_EXC_PRECISE)
1874 tsk->thread.fpexc_mode = __pack_fe01(val);
1875 if (regs != NULL && (regs->msr & MSR_FP) != 0)
1876 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1877 | tsk->thread.fpexc_mode;
1881 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1885 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1887 if (cpu_has_feature(CPU_FTR_SPE)) {
1889 * When the sticky exception bits are set
1890 * directly by userspace, it must call prctl
1891 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1892 * in the existing prctl settings) or
1893 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1894 * the bits being set). <fenv.h> functions
1895 * saving and restoring the whole
1896 * floating-point environment need to do so
1897 * anyway to restore the prctl settings from
1898 * the saved environment.
1900 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1901 val = tsk->thread.fpexc_mode;
1908 val = __unpack_fe01(tsk->thread.fpexc_mode);
1909 return put_user(val, (unsigned int __user *) adr);
1912 int set_endian(struct task_struct *tsk, unsigned int val)
1914 struct pt_regs *regs = tsk->thread.regs;
1916 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1917 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1923 if (val == PR_ENDIAN_BIG)
1924 regs->msr &= ~MSR_LE;
1925 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1926 regs->msr |= MSR_LE;
1933 int get_endian(struct task_struct *tsk, unsigned long adr)
1935 struct pt_regs *regs = tsk->thread.regs;
1938 if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1939 !cpu_has_feature(CPU_FTR_REAL_LE))
1945 if (regs->msr & MSR_LE) {
1946 if (cpu_has_feature(CPU_FTR_REAL_LE))
1947 val = PR_ENDIAN_LITTLE;
1949 val = PR_ENDIAN_PPC_LITTLE;
1951 val = PR_ENDIAN_BIG;
1953 return put_user(val, (unsigned int __user *)adr);
1956 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1958 tsk->thread.align_ctl = val;
1962 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1964 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1967 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1968 unsigned long nbytes)
1970 unsigned long stack_page;
1971 unsigned long cpu = task_cpu(p);
1973 stack_page = (unsigned long)hardirq_ctx[cpu];
1974 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1977 stack_page = (unsigned long)softirq_ctx[cpu];
1978 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1984 static inline int valid_emergency_stack(unsigned long sp, struct task_struct *p,
1985 unsigned long nbytes)
1988 unsigned long stack_page;
1989 unsigned long cpu = task_cpu(p);
1991 stack_page = (unsigned long)paca_ptrs[cpu]->emergency_sp - THREAD_SIZE;
1992 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1995 # ifdef CONFIG_PPC_BOOK3S_64
1996 stack_page = (unsigned long)paca_ptrs[cpu]->nmi_emergency_sp - THREAD_SIZE;
1997 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2000 stack_page = (unsigned long)paca_ptrs[cpu]->mc_emergency_sp - THREAD_SIZE;
2001 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2010 int validate_sp(unsigned long sp, struct task_struct *p,
2011 unsigned long nbytes)
2013 unsigned long stack_page = (unsigned long)task_stack_page(p);
2015 if (sp < THREAD_SIZE)
2018 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2021 if (valid_irq_stack(sp, p, nbytes))
2024 return valid_emergency_stack(sp, p, nbytes);
2027 EXPORT_SYMBOL(validate_sp);
2029 static unsigned long __get_wchan(struct task_struct *p)
2031 unsigned long ip, sp;
2034 if (!p || p == current || p->state == TASK_RUNNING)
2038 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
2042 sp = *(unsigned long *)sp;
2043 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) ||
2044 p->state == TASK_RUNNING)
2047 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
2048 if (!in_sched_functions(ip))
2051 } while (count++ < 16);
2055 unsigned long get_wchan(struct task_struct *p)
2059 if (!try_get_task_stack(p))
2062 ret = __get_wchan(p);
2069 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
2071 void show_stack(struct task_struct *tsk, unsigned long *stack)
2073 unsigned long sp, ip, lr, newsp;
2076 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2077 unsigned long ret_addr;
2084 if (!try_get_task_stack(tsk))
2087 sp = (unsigned long) stack;
2090 sp = current_stack_frame();
2092 sp = tsk->thread.ksp;
2096 printk("Call Trace:\n");
2098 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
2101 stack = (unsigned long *) sp;
2103 ip = stack[STACK_FRAME_LR_SAVE];
2104 if (!firstframe || ip != lr) {
2105 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
2106 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2107 ret_addr = ftrace_graph_ret_addr(current,
2108 &ftrace_idx, ip, stack);
2110 pr_cont(" (%pS)", (void *)ret_addr);
2113 pr_cont(" (unreliable)");
2119 * See if this is an exception frame.
2120 * We look for the "regshere" marker in the current frame.
2122 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
2123 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
2124 struct pt_regs *regs = (struct pt_regs *)
2125 (sp + STACK_FRAME_OVERHEAD);
2127 printk("--- interrupt: %lx at %pS\n LR = %pS\n",
2128 regs->trap, (void *)regs->nip, (void *)lr);
2133 } while (count++ < kstack_depth_to_print);
2135 put_task_stack(tsk);
2139 /* Called with hard IRQs off */
2140 void notrace __ppc64_runlatch_on(void)
2142 struct thread_info *ti = current_thread_info();
2144 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2146 * Least significant bit (RUN) is the only writable bit of
2147 * the CTRL register, so we can avoid mfspr. 2.06 is not the
2148 * earliest ISA where this is the case, but it's convenient.
2150 mtspr(SPRN_CTRLT, CTRL_RUNLATCH);
2155 * Some architectures (e.g., Cell) have writable fields other
2156 * than RUN, so do the read-modify-write.
2158 ctrl = mfspr(SPRN_CTRLF);
2159 ctrl |= CTRL_RUNLATCH;
2160 mtspr(SPRN_CTRLT, ctrl);
2163 ti->local_flags |= _TLF_RUNLATCH;
2166 /* Called with hard IRQs off */
2167 void notrace __ppc64_runlatch_off(void)
2169 struct thread_info *ti = current_thread_info();
2171 ti->local_flags &= ~_TLF_RUNLATCH;
2173 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2174 mtspr(SPRN_CTRLT, 0);
2178 ctrl = mfspr(SPRN_CTRLF);
2179 ctrl &= ~CTRL_RUNLATCH;
2180 mtspr(SPRN_CTRLT, ctrl);
2183 #endif /* CONFIG_PPC64 */
2185 unsigned long arch_align_stack(unsigned long sp)
2187 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
2188 sp -= get_random_int() & ~PAGE_MASK;
2192 static inline unsigned long brk_rnd(void)
2194 unsigned long rnd = 0;
2196 /* 8MB for 32bit, 1GB for 64bit */
2197 if (is_32bit_task())
2198 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
2200 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
2202 return rnd << PAGE_SHIFT;
2205 unsigned long arch_randomize_brk(struct mm_struct *mm)
2207 unsigned long base = mm->brk;
2210 #ifdef CONFIG_PPC_BOOK3S_64
2212 * If we are using 1TB segments and we are allowed to randomise
2213 * the heap, we can put it above 1TB so it is backed by a 1TB
2214 * segment. Otherwise the heap will be in the bottom 1TB
2215 * which always uses 256MB segments and this may result in a
2216 * performance penalty. We don't need to worry about radix. For
2217 * radix, mmu_highuser_ssize remains unchanged from 256MB.
2219 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2220 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2223 ret = PAGE_ALIGN(base + brk_rnd());