2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/sched/debug.h>
20 #include <linux/sched/task.h>
21 #include <linux/sched/task_stack.h>
22 #include <linux/kernel.h>
24 #include <linux/smp.h>
25 #include <linux/stddef.h>
26 #include <linux/unistd.h>
27 #include <linux/ptrace.h>
28 #include <linux/slab.h>
29 #include <linux/user.h>
30 #include <linux/elf.h>
31 #include <linux/prctl.h>
32 #include <linux/init_task.h>
33 #include <linux/export.h>
34 #include <linux/kallsyms.h>
35 #include <linux/mqueue.h>
36 #include <linux/hardirq.h>
37 #include <linux/utsname.h>
38 #include <linux/ftrace.h>
39 #include <linux/kernel_stat.h>
40 #include <linux/personality.h>
41 #include <linux/random.h>
42 #include <linux/hw_breakpoint.h>
43 #include <linux/uaccess.h>
44 #include <linux/elf-randomize.h>
45 #include <linux/pkeys.h>
46 #include <linux/seq_buf.h>
48 #include <asm/pgtable.h>
50 #include <asm/processor.h>
53 #include <asm/machdep.h>
55 #include <asm/runlatch.h>
56 #include <asm/syscalls.h>
57 #include <asm/switch_to.h>
59 #include <asm/debug.h>
61 #include <asm/firmware.h>
62 #include <asm/hw_irq.h>
64 #include <asm/code-patching.h>
66 #include <asm/livepatch.h>
67 #include <asm/cpu_has_feature.h>
68 #include <asm/asm-prototypes.h>
69 #include <asm/stacktrace.h>
70 #include <asm/hw_breakpoint.h>
72 #include <linux/kprobes.h>
73 #include <linux/kdebug.h>
75 /* Transactional Memory debug */
77 #define TM_DEBUG(x...) printk(KERN_INFO x)
79 #define TM_DEBUG(x...) do { } while(0)
82 extern unsigned long _get_SP(void);
84 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
86 * Are we running in "Suspend disabled" mode? If so we have to block any
87 * sigreturn that would get us into suspended state, and we also warn in some
88 * other paths that we should never reach with suspend disabled.
90 bool tm_suspend_disabled __ro_after_init = false;
92 static void check_if_tm_restore_required(struct task_struct *tsk)
95 * If we are saving the current thread's registers, and the
96 * thread is in a transactional state, set the TIF_RESTORE_TM
97 * bit so that we know to restore the registers before
98 * returning to userspace.
100 if (tsk == current && tsk->thread.regs &&
101 MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
102 !test_thread_flag(TIF_RESTORE_TM)) {
103 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
104 set_thread_flag(TIF_RESTORE_TM);
108 static bool tm_active_with_fp(struct task_struct *tsk)
110 return MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
111 (tsk->thread.ckpt_regs.msr & MSR_FP);
114 static bool tm_active_with_altivec(struct task_struct *tsk)
116 return MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
117 (tsk->thread.ckpt_regs.msr & MSR_VEC);
120 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
121 static inline bool tm_active_with_fp(struct task_struct *tsk) { return false; }
122 static inline bool tm_active_with_altivec(struct task_struct *tsk) { return false; }
123 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
125 bool strict_msr_control;
126 EXPORT_SYMBOL(strict_msr_control);
128 static int __init enable_strict_msr_control(char *str)
130 strict_msr_control = true;
131 pr_info("Enabling strict facility control\n");
135 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
137 /* notrace because it's called by restore_math */
138 unsigned long notrace msr_check_and_set(unsigned long bits)
140 unsigned long oldmsr = mfmsr();
141 unsigned long newmsr;
143 newmsr = oldmsr | bits;
146 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
150 if (oldmsr != newmsr)
155 EXPORT_SYMBOL_GPL(msr_check_and_set);
157 /* notrace because it's called by restore_math */
158 void notrace __msr_check_and_clear(unsigned long bits)
160 unsigned long oldmsr = mfmsr();
161 unsigned long newmsr;
163 newmsr = oldmsr & ~bits;
166 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
170 if (oldmsr != newmsr)
173 EXPORT_SYMBOL(__msr_check_and_clear);
175 #ifdef CONFIG_PPC_FPU
176 static void __giveup_fpu(struct task_struct *tsk)
181 msr = tsk->thread.regs->msr;
182 msr &= ~(MSR_FP|MSR_FE0|MSR_FE1);
184 if (cpu_has_feature(CPU_FTR_VSX))
187 tsk->thread.regs->msr = msr;
190 void giveup_fpu(struct task_struct *tsk)
192 check_if_tm_restore_required(tsk);
194 msr_check_and_set(MSR_FP);
196 msr_check_and_clear(MSR_FP);
198 EXPORT_SYMBOL(giveup_fpu);
201 * Make sure the floating-point register state in the
202 * the thread_struct is up to date for task tsk.
204 void flush_fp_to_thread(struct task_struct *tsk)
206 if (tsk->thread.regs) {
208 * We need to disable preemption here because if we didn't,
209 * another process could get scheduled after the regs->msr
210 * test but before we have finished saving the FP registers
211 * to the thread_struct. That process could take over the
212 * FPU, and then when we get scheduled again we would store
213 * bogus values for the remaining FP registers.
216 if (tsk->thread.regs->msr & MSR_FP) {
218 * This should only ever be called for current or
219 * for a stopped child process. Since we save away
220 * the FP register state on context switch,
221 * there is something wrong if a stopped child appears
222 * to still have its FP state in the CPU registers.
224 BUG_ON(tsk != current);
230 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
232 void enable_kernel_fp(void)
234 unsigned long cpumsr;
236 WARN_ON(preemptible());
238 cpumsr = msr_check_and_set(MSR_FP);
240 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
241 check_if_tm_restore_required(current);
243 * If a thread has already been reclaimed then the
244 * checkpointed registers are on the CPU but have definitely
245 * been saved by the reclaim code. Don't need to and *cannot*
246 * giveup as this would save to the 'live' structure not the
247 * checkpointed structure.
249 if (!MSR_TM_ACTIVE(cpumsr) &&
250 MSR_TM_ACTIVE(current->thread.regs->msr))
252 __giveup_fpu(current);
255 EXPORT_SYMBOL(enable_kernel_fp);
257 static int restore_fp(struct task_struct *tsk)
259 if (tsk->thread.load_fp || tm_active_with_fp(tsk)) {
260 load_fp_state(¤t->thread.fp_state);
261 current->thread.load_fp++;
267 static int restore_fp(struct task_struct *tsk) { return 0; }
268 #endif /* CONFIG_PPC_FPU */
270 #ifdef CONFIG_ALTIVEC
271 #define loadvec(thr) ((thr).load_vec)
273 static void __giveup_altivec(struct task_struct *tsk)
278 msr = tsk->thread.regs->msr;
281 if (cpu_has_feature(CPU_FTR_VSX))
284 tsk->thread.regs->msr = msr;
287 void giveup_altivec(struct task_struct *tsk)
289 check_if_tm_restore_required(tsk);
291 msr_check_and_set(MSR_VEC);
292 __giveup_altivec(tsk);
293 msr_check_and_clear(MSR_VEC);
295 EXPORT_SYMBOL(giveup_altivec);
297 void enable_kernel_altivec(void)
299 unsigned long cpumsr;
301 WARN_ON(preemptible());
303 cpumsr = msr_check_and_set(MSR_VEC);
305 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
306 check_if_tm_restore_required(current);
308 * If a thread has already been reclaimed then the
309 * checkpointed registers are on the CPU but have definitely
310 * been saved by the reclaim code. Don't need to and *cannot*
311 * giveup as this would save to the 'live' structure not the
312 * checkpointed structure.
314 if (!MSR_TM_ACTIVE(cpumsr) &&
315 MSR_TM_ACTIVE(current->thread.regs->msr))
317 __giveup_altivec(current);
320 EXPORT_SYMBOL(enable_kernel_altivec);
323 * Make sure the VMX/Altivec register state in the
324 * the thread_struct is up to date for task tsk.
326 void flush_altivec_to_thread(struct task_struct *tsk)
328 if (tsk->thread.regs) {
330 if (tsk->thread.regs->msr & MSR_VEC) {
331 BUG_ON(tsk != current);
337 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
339 static int restore_altivec(struct task_struct *tsk)
341 if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
342 (tsk->thread.load_vec || tm_active_with_altivec(tsk))) {
343 load_vr_state(&tsk->thread.vr_state);
344 tsk->thread.used_vr = 1;
345 tsk->thread.load_vec++;
352 #define loadvec(thr) 0
353 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
354 #endif /* CONFIG_ALTIVEC */
357 static void __giveup_vsx(struct task_struct *tsk)
359 unsigned long msr = tsk->thread.regs->msr;
362 * We should never be ssetting MSR_VSX without also setting
365 WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC)));
367 /* __giveup_fpu will clear MSR_VSX */
371 __giveup_altivec(tsk);
374 static void giveup_vsx(struct task_struct *tsk)
376 check_if_tm_restore_required(tsk);
378 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
380 msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
383 void enable_kernel_vsx(void)
385 unsigned long cpumsr;
387 WARN_ON(preemptible());
389 cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
391 if (current->thread.regs &&
392 (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) {
393 check_if_tm_restore_required(current);
395 * If a thread has already been reclaimed then the
396 * checkpointed registers are on the CPU but have definitely
397 * been saved by the reclaim code. Don't need to and *cannot*
398 * giveup as this would save to the 'live' structure not the
399 * checkpointed structure.
401 if (!MSR_TM_ACTIVE(cpumsr) &&
402 MSR_TM_ACTIVE(current->thread.regs->msr))
404 __giveup_vsx(current);
407 EXPORT_SYMBOL(enable_kernel_vsx);
409 void flush_vsx_to_thread(struct task_struct *tsk)
411 if (tsk->thread.regs) {
413 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) {
414 BUG_ON(tsk != current);
420 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
422 static int restore_vsx(struct task_struct *tsk)
424 if (cpu_has_feature(CPU_FTR_VSX)) {
425 tsk->thread.used_vsr = 1;
432 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
433 #endif /* CONFIG_VSX */
436 void giveup_spe(struct task_struct *tsk)
438 check_if_tm_restore_required(tsk);
440 msr_check_and_set(MSR_SPE);
442 msr_check_and_clear(MSR_SPE);
444 EXPORT_SYMBOL(giveup_spe);
446 void enable_kernel_spe(void)
448 WARN_ON(preemptible());
450 msr_check_and_set(MSR_SPE);
452 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
453 check_if_tm_restore_required(current);
454 __giveup_spe(current);
457 EXPORT_SYMBOL(enable_kernel_spe);
459 void flush_spe_to_thread(struct task_struct *tsk)
461 if (tsk->thread.regs) {
463 if (tsk->thread.regs->msr & MSR_SPE) {
464 BUG_ON(tsk != current);
465 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
471 #endif /* CONFIG_SPE */
473 static unsigned long msr_all_available;
475 static int __init init_msr_all_available(void)
477 #ifdef CONFIG_PPC_FPU
478 msr_all_available |= MSR_FP;
480 #ifdef CONFIG_ALTIVEC
481 if (cpu_has_feature(CPU_FTR_ALTIVEC))
482 msr_all_available |= MSR_VEC;
485 if (cpu_has_feature(CPU_FTR_VSX))
486 msr_all_available |= MSR_VSX;
489 if (cpu_has_feature(CPU_FTR_SPE))
490 msr_all_available |= MSR_SPE;
495 early_initcall(init_msr_all_available);
497 void giveup_all(struct task_struct *tsk)
499 unsigned long usermsr;
501 if (!tsk->thread.regs)
504 usermsr = tsk->thread.regs->msr;
506 if ((usermsr & msr_all_available) == 0)
509 msr_check_and_set(msr_all_available);
510 check_if_tm_restore_required(tsk);
512 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
514 #ifdef CONFIG_PPC_FPU
515 if (usermsr & MSR_FP)
518 #ifdef CONFIG_ALTIVEC
519 if (usermsr & MSR_VEC)
520 __giveup_altivec(tsk);
523 if (usermsr & MSR_SPE)
527 msr_check_and_clear(msr_all_available);
529 EXPORT_SYMBOL(giveup_all);
532 * The exception exit path calls restore_math() with interrupts hard disabled
533 * but the soft irq state not "reconciled". ftrace code that calls
534 * local_irq_save/restore causes warnings.
536 * Rather than complicate the exit path, just don't trace restore_math. This
537 * could be done by having ftrace entry code check for this un-reconciled
538 * condition where MSR[EE]=0 and PACA_IRQ_HARD_DIS is not set, and
539 * temporarily fix it up for the duration of the ftrace call.
541 void notrace restore_math(struct pt_regs *regs)
545 if (!MSR_TM_ACTIVE(regs->msr) &&
546 !current->thread.load_fp && !loadvec(current->thread))
550 msr_check_and_set(msr_all_available);
553 * Only reload if the bit is not set in the user MSR, the bit BEING set
554 * indicates that the registers are hot
556 if ((!(msr & MSR_FP)) && restore_fp(current))
557 msr |= MSR_FP | current->thread.fpexc_mode;
559 if ((!(msr & MSR_VEC)) && restore_altivec(current))
562 if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
563 restore_vsx(current)) {
567 msr_check_and_clear(msr_all_available);
572 static void save_all(struct task_struct *tsk)
574 unsigned long usermsr;
576 if (!tsk->thread.regs)
579 usermsr = tsk->thread.regs->msr;
581 if ((usermsr & msr_all_available) == 0)
584 msr_check_and_set(msr_all_available);
586 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
588 if (usermsr & MSR_FP)
591 if (usermsr & MSR_VEC)
594 if (usermsr & MSR_SPE)
597 msr_check_and_clear(msr_all_available);
598 thread_pkey_regs_save(&tsk->thread);
601 void flush_all_to_thread(struct task_struct *tsk)
603 if (tsk->thread.regs) {
605 BUG_ON(tsk != current);
607 if (tsk->thread.regs->msr & MSR_SPE)
608 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
615 EXPORT_SYMBOL(flush_all_to_thread);
617 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
618 void do_send_trap(struct pt_regs *regs, unsigned long address,
619 unsigned long error_code, int breakpt)
621 current->thread.trap_nr = TRAP_HWBKPT;
622 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
623 11, SIGSEGV) == NOTIFY_STOP)
626 /* Deliver the signal to userspace */
627 force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */
628 (void __user *)address);
630 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
631 void do_break (struct pt_regs *regs, unsigned long address,
632 unsigned long error_code)
634 current->thread.trap_nr = TRAP_HWBKPT;
635 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
636 11, SIGSEGV) == NOTIFY_STOP)
639 if (debugger_break_match(regs))
642 /* Clear the breakpoint */
643 hw_breakpoint_disable();
645 /* Deliver the signal to userspace */
646 force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)address, current);
648 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
650 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
652 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
654 * Set the debug registers back to their default "safe" values.
656 static void set_debug_reg_defaults(struct thread_struct *thread)
658 thread->debug.iac1 = thread->debug.iac2 = 0;
659 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
660 thread->debug.iac3 = thread->debug.iac4 = 0;
662 thread->debug.dac1 = thread->debug.dac2 = 0;
663 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
664 thread->debug.dvc1 = thread->debug.dvc2 = 0;
666 thread->debug.dbcr0 = 0;
669 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
671 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
672 DBCR1_IAC3US | DBCR1_IAC4US;
674 * Force Data Address Compare User/Supervisor bits to be User-only
675 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
677 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
679 thread->debug.dbcr1 = 0;
683 static void prime_debug_regs(struct debug_reg *debug)
686 * We could have inherited MSR_DE from userspace, since
687 * it doesn't get cleared on exception entry. Make sure
688 * MSR_DE is clear before we enable any debug events.
690 mtmsr(mfmsr() & ~MSR_DE);
692 mtspr(SPRN_IAC1, debug->iac1);
693 mtspr(SPRN_IAC2, debug->iac2);
694 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
695 mtspr(SPRN_IAC3, debug->iac3);
696 mtspr(SPRN_IAC4, debug->iac4);
698 mtspr(SPRN_DAC1, debug->dac1);
699 mtspr(SPRN_DAC2, debug->dac2);
700 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
701 mtspr(SPRN_DVC1, debug->dvc1);
702 mtspr(SPRN_DVC2, debug->dvc2);
704 mtspr(SPRN_DBCR0, debug->dbcr0);
705 mtspr(SPRN_DBCR1, debug->dbcr1);
707 mtspr(SPRN_DBCR2, debug->dbcr2);
711 * Unless neither the old or new thread are making use of the
712 * debug registers, set the debug registers from the values
713 * stored in the new thread.
715 void switch_booke_debug_regs(struct debug_reg *new_debug)
717 if ((current->thread.debug.dbcr0 & DBCR0_IDM)
718 || (new_debug->dbcr0 & DBCR0_IDM))
719 prime_debug_regs(new_debug);
721 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
722 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
723 #ifndef CONFIG_HAVE_HW_BREAKPOINT
724 static void set_breakpoint(struct arch_hw_breakpoint *brk)
727 __set_breakpoint(brk);
731 static void set_debug_reg_defaults(struct thread_struct *thread)
733 thread->hw_brk.address = 0;
734 thread->hw_brk.type = 0;
735 if (ppc_breakpoint_available())
736 set_breakpoint(&thread->hw_brk);
738 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
739 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
741 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
742 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
744 mtspr(SPRN_DAC1, dabr);
745 #ifdef CONFIG_PPC_47x
750 #elif defined(CONFIG_PPC_BOOK3S)
751 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
753 mtspr(SPRN_DABR, dabr);
754 if (cpu_has_feature(CPU_FTR_DABRX))
755 mtspr(SPRN_DABRX, dabrx);
758 #elif defined(CONFIG_PPC_8xx)
759 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
761 unsigned long addr = dabr & ~HW_BRK_TYPE_DABR;
762 unsigned long lctrl1 = 0x90000000; /* compare type: equal on E & F */
763 unsigned long lctrl2 = 0x8e000002; /* watchpoint 1 on cmp E | F */
765 if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
767 else if ((dabr & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
769 else if ((dabr & HW_BRK_TYPE_RDWR) == 0)
772 mtspr(SPRN_LCTRL2, 0);
773 mtspr(SPRN_CMPE, addr);
774 mtspr(SPRN_CMPF, addr + 4);
775 mtspr(SPRN_LCTRL1, lctrl1);
776 mtspr(SPRN_LCTRL2, lctrl2);
781 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
787 static inline int set_dabr(struct arch_hw_breakpoint *brk)
789 unsigned long dabr, dabrx;
791 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
792 dabrx = ((brk->type >> 3) & 0x7);
795 return ppc_md.set_dabr(dabr, dabrx);
797 return __set_dabr(dabr, dabrx);
800 void __set_breakpoint(struct arch_hw_breakpoint *brk)
802 memcpy(this_cpu_ptr(¤t_brk), brk, sizeof(*brk));
807 else if (!cpu_has_feature(CPU_FTR_ARCH_207S))
811 // Shouldn't happen due to higher level checks
815 /* Check if we have DAWR or DABR hardware */
816 bool ppc_breakpoint_available(void)
819 return true; /* POWER8 DAWR or POWER9 forced DAWR */
820 if (cpu_has_feature(CPU_FTR_ARCH_207S))
821 return false; /* POWER9 with DAWR disabled */
822 /* DABR: Everything but POWER8 and POWER9 */
825 EXPORT_SYMBOL_GPL(ppc_breakpoint_available);
827 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
828 struct arch_hw_breakpoint *b)
830 if (a->address != b->address)
832 if (a->type != b->type)
834 if (a->len != b->len)
839 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
841 static inline bool tm_enabled(struct task_struct *tsk)
843 return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
846 static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause)
849 * Use the current MSR TM suspended bit to track if we have
850 * checkpointed state outstanding.
851 * On signal delivery, we'd normally reclaim the checkpointed
852 * state to obtain stack pointer (see:get_tm_stackpointer()).
853 * This will then directly return to userspace without going
854 * through __switch_to(). However, if the stack frame is bad,
855 * we need to exit this thread which calls __switch_to() which
856 * will again attempt to reclaim the already saved tm state.
857 * Hence we need to check that we've not already reclaimed
859 * We do this using the current MSR, rather tracking it in
860 * some specific thread_struct bit, as it has the additional
861 * benefit of checking for a potential TM bad thing exception.
863 if (!MSR_TM_SUSPENDED(mfmsr()))
866 giveup_all(container_of(thr, struct task_struct, thread));
868 tm_reclaim(thr, cause);
871 * If we are in a transaction and FP is off then we can't have
872 * used FP inside that transaction. Hence the checkpointed
873 * state is the same as the live state. We need to copy the
874 * live state to the checkpointed state so that when the
875 * transaction is restored, the checkpointed state is correct
876 * and the aborted transaction sees the correct state. We use
877 * ckpt_regs.msr here as that's what tm_reclaim will use to
878 * determine if it's going to write the checkpointed state or
879 * not. So either this will write the checkpointed registers,
880 * or reclaim will. Similarly for VMX.
882 if ((thr->ckpt_regs.msr & MSR_FP) == 0)
883 memcpy(&thr->ckfp_state, &thr->fp_state,
884 sizeof(struct thread_fp_state));
885 if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
886 memcpy(&thr->ckvr_state, &thr->vr_state,
887 sizeof(struct thread_vr_state));
890 void tm_reclaim_current(uint8_t cause)
893 tm_reclaim_thread(¤t->thread, cause);
896 static inline void tm_reclaim_task(struct task_struct *tsk)
898 /* We have to work out if we're switching from/to a task that's in the
899 * middle of a transaction.
901 * In switching we need to maintain a 2nd register state as
902 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
903 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
906 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
908 struct thread_struct *thr = &tsk->thread;
913 if (!MSR_TM_ACTIVE(thr->regs->msr))
914 goto out_and_saveregs;
916 WARN_ON(tm_suspend_disabled);
918 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
919 "ccr=%lx, msr=%lx, trap=%lx)\n",
920 tsk->pid, thr->regs->nip,
921 thr->regs->ccr, thr->regs->msr,
924 tm_reclaim_thread(thr, TM_CAUSE_RESCHED);
926 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
930 /* Always save the regs here, even if a transaction's not active.
931 * This context-switches a thread's TM info SPRs. We do it here to
932 * be consistent with the restore path (in recheckpoint) which
933 * cannot happen later in _switch().
938 extern void __tm_recheckpoint(struct thread_struct *thread);
940 void tm_recheckpoint(struct thread_struct *thread)
944 if (!(thread->regs->msr & MSR_TM))
947 /* We really can't be interrupted here as the TEXASR registers can't
948 * change and later in the trecheckpoint code, we have a userspace R1.
949 * So let's hard disable over this region.
951 local_irq_save(flags);
954 /* The TM SPRs are restored here, so that TEXASR.FS can be set
955 * before the trecheckpoint and no explosion occurs.
957 tm_restore_sprs(thread);
959 __tm_recheckpoint(thread);
961 local_irq_restore(flags);
964 static inline void tm_recheckpoint_new_task(struct task_struct *new)
966 if (!cpu_has_feature(CPU_FTR_TM))
969 /* Recheckpoint the registers of the thread we're about to switch to.
971 * If the task was using FP, we non-lazily reload both the original and
972 * the speculative FP register states. This is because the kernel
973 * doesn't see if/when a TM rollback occurs, so if we take an FP
974 * unavailable later, we are unable to determine which set of FP regs
975 * need to be restored.
977 if (!tm_enabled(new))
980 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
981 tm_restore_sprs(&new->thread);
984 /* Recheckpoint to restore original checkpointed register state. */
985 TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
986 new->pid, new->thread.regs->msr);
988 tm_recheckpoint(&new->thread);
991 * The checkpointed state has been restored but the live state has
992 * not, ensure all the math functionality is turned off to trigger
993 * restore_math() to reload.
995 new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
997 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
998 "(kernel msr 0x%lx)\n",
1002 static inline void __switch_to_tm(struct task_struct *prev,
1003 struct task_struct *new)
1005 if (cpu_has_feature(CPU_FTR_TM)) {
1006 if (tm_enabled(prev) || tm_enabled(new))
1009 if (tm_enabled(prev)) {
1010 prev->thread.load_tm++;
1011 tm_reclaim_task(prev);
1012 if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
1013 prev->thread.regs->msr &= ~MSR_TM;
1016 tm_recheckpoint_new_task(new);
1021 * This is called if we are on the way out to userspace and the
1022 * TIF_RESTORE_TM flag is set. It checks if we need to reload
1023 * FP and/or vector state and does so if necessary.
1024 * If userspace is inside a transaction (whether active or
1025 * suspended) and FP/VMX/VSX instructions have ever been enabled
1026 * inside that transaction, then we have to keep them enabled
1027 * and keep the FP/VMX/VSX state loaded while ever the transaction
1028 * continues. The reason is that if we didn't, and subsequently
1029 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1030 * we don't know whether it's the same transaction, and thus we
1031 * don't know which of the checkpointed state and the transactional
1034 void restore_tm_state(struct pt_regs *regs)
1036 unsigned long msr_diff;
1039 * This is the only moment we should clear TIF_RESTORE_TM as
1040 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1041 * again, anything else could lead to an incorrect ckpt_msr being
1042 * saved and therefore incorrect signal contexts.
1044 clear_thread_flag(TIF_RESTORE_TM);
1045 if (!MSR_TM_ACTIVE(regs->msr))
1048 msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1049 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1051 /* Ensure that restore_math() will restore */
1052 if (msr_diff & MSR_FP)
1053 current->thread.load_fp = 1;
1054 #ifdef CONFIG_ALTIVEC
1055 if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1056 current->thread.load_vec = 1;
1060 regs->msr |= msr_diff;
1064 #define tm_recheckpoint_new_task(new)
1065 #define __switch_to_tm(prev, new)
1066 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1068 static inline void save_sprs(struct thread_struct *t)
1070 #ifdef CONFIG_ALTIVEC
1071 if (cpu_has_feature(CPU_FTR_ALTIVEC))
1072 t->vrsave = mfspr(SPRN_VRSAVE);
1074 #ifdef CONFIG_PPC_BOOK3S_64
1075 if (cpu_has_feature(CPU_FTR_DSCR))
1076 t->dscr = mfspr(SPRN_DSCR);
1078 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1079 t->bescr = mfspr(SPRN_BESCR);
1080 t->ebbhr = mfspr(SPRN_EBBHR);
1081 t->ebbrr = mfspr(SPRN_EBBRR);
1083 t->fscr = mfspr(SPRN_FSCR);
1086 * Note that the TAR is not available for use in the kernel.
1087 * (To provide this, the TAR should be backed up/restored on
1088 * exception entry/exit instead, and be in pt_regs. FIXME,
1089 * this should be in pt_regs anyway (for debug).)
1091 t->tar = mfspr(SPRN_TAR);
1095 thread_pkey_regs_save(t);
1098 static inline void restore_sprs(struct thread_struct *old_thread,
1099 struct thread_struct *new_thread)
1101 #ifdef CONFIG_ALTIVEC
1102 if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1103 old_thread->vrsave != new_thread->vrsave)
1104 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1106 #ifdef CONFIG_PPC_BOOK3S_64
1107 if (cpu_has_feature(CPU_FTR_DSCR)) {
1108 u64 dscr = get_paca()->dscr_default;
1109 if (new_thread->dscr_inherit)
1110 dscr = new_thread->dscr;
1112 if (old_thread->dscr != dscr)
1113 mtspr(SPRN_DSCR, dscr);
1116 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1117 if (old_thread->bescr != new_thread->bescr)
1118 mtspr(SPRN_BESCR, new_thread->bescr);
1119 if (old_thread->ebbhr != new_thread->ebbhr)
1120 mtspr(SPRN_EBBHR, new_thread->ebbhr);
1121 if (old_thread->ebbrr != new_thread->ebbrr)
1122 mtspr(SPRN_EBBRR, new_thread->ebbrr);
1124 if (old_thread->fscr != new_thread->fscr)
1125 mtspr(SPRN_FSCR, new_thread->fscr);
1127 if (old_thread->tar != new_thread->tar)
1128 mtspr(SPRN_TAR, new_thread->tar);
1131 if (cpu_has_feature(CPU_FTR_P9_TIDR) &&
1132 old_thread->tidr != new_thread->tidr)
1133 mtspr(SPRN_TIDR, new_thread->tidr);
1136 thread_pkey_regs_restore(new_thread, old_thread);
1139 struct task_struct *__switch_to(struct task_struct *prev,
1140 struct task_struct *new)
1142 struct thread_struct *new_thread, *old_thread;
1143 struct task_struct *last;
1144 #ifdef CONFIG_PPC_BOOK3S_64
1145 struct ppc64_tlb_batch *batch;
1148 new_thread = &new->thread;
1149 old_thread = ¤t->thread;
1151 WARN_ON(!irqs_disabled());
1153 #ifdef CONFIG_PPC_BOOK3S_64
1154 batch = this_cpu_ptr(&ppc64_tlb_batch);
1155 if (batch->active) {
1156 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1158 __flush_tlb_pending(batch);
1161 #endif /* CONFIG_PPC_BOOK3S_64 */
1163 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1164 switch_booke_debug_regs(&new->thread.debug);
1167 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1170 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1171 if (unlikely(!hw_brk_match(this_cpu_ptr(¤t_brk), &new->thread.hw_brk)))
1172 __set_breakpoint(&new->thread.hw_brk);
1173 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1177 * We need to save SPRs before treclaim/trecheckpoint as these will
1178 * change a number of them.
1180 save_sprs(&prev->thread);
1182 /* Save FPU, Altivec, VSX and SPE state */
1185 __switch_to_tm(prev, new);
1187 if (!radix_enabled()) {
1189 * We can't take a PMU exception inside _switch() since there
1190 * is a window where the kernel stack SLB and the kernel stack
1191 * are out of sync. Hard disable here.
1197 * Call restore_sprs() before calling _switch(). If we move it after
1198 * _switch() then we miss out on calling it for new tasks. The reason
1199 * for this is we manually create a stack frame for new tasks that
1200 * directly returns through ret_from_fork() or
1201 * ret_from_kernel_thread(). See copy_thread() for details.
1203 restore_sprs(old_thread, new_thread);
1205 last = _switch(old_thread, new_thread);
1207 #ifdef CONFIG_PPC_BOOK3S_64
1208 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1209 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1210 batch = this_cpu_ptr(&ppc64_tlb_batch);
1214 if (current->thread.regs) {
1215 restore_math(current->thread.regs);
1218 * The copy-paste buffer can only store into foreign real
1219 * addresses, so unprivileged processes can not see the
1220 * data or use it in any way unless they have foreign real
1221 * mappings. If the new process has the foreign real address
1222 * mappings, we must issue a cp_abort to clear any state and
1223 * prevent snooping, corruption or a covert channel.
1225 if (current->thread.used_vas)
1226 asm volatile(PPC_CP_ABORT);
1228 #endif /* CONFIG_PPC_BOOK3S_64 */
1233 #define NR_INSN_TO_PRINT 16
1235 static void show_instructions(struct pt_regs *regs)
1238 unsigned long pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1240 printk("Instruction dump:");
1242 for (i = 0; i < NR_INSN_TO_PRINT; i++) {
1248 #if !defined(CONFIG_BOOKE)
1249 /* If executing with the IMMU off, adjust pc rather
1250 * than print XXXXXXXX.
1252 if (!(regs->msr & MSR_IR))
1253 pc = (unsigned long)phys_to_virt(pc);
1256 if (!__kernel_text_address(pc) ||
1257 probe_kernel_address((const void *)pc, instr)) {
1258 pr_cont("XXXXXXXX ");
1260 if (regs->nip == pc)
1261 pr_cont("<%08x> ", instr);
1263 pr_cont("%08x ", instr);
1272 void show_user_instructions(struct pt_regs *regs)
1275 int n = NR_INSN_TO_PRINT;
1277 char buf[96]; /* enough for 8 times 9 + 2 chars */
1279 pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1282 * Make sure the NIP points at userspace, not kernel text/data or
1285 if (!__access_ok(pc, NR_INSN_TO_PRINT * sizeof(int), USER_DS)) {
1286 pr_info("%s[%d]: Bad NIP, not dumping instructions.\n",
1287 current->comm, current->pid);
1291 seq_buf_init(&s, buf, sizeof(buf));
1298 for (i = 0; i < 8 && n; i++, n--, pc += sizeof(int)) {
1301 if (probe_kernel_address((const void *)pc, instr)) {
1302 seq_buf_printf(&s, "XXXXXXXX ");
1305 seq_buf_printf(&s, regs->nip == pc ? "<%08x> " : "%08x ", instr);
1308 if (!seq_buf_has_overflowed(&s))
1309 pr_info("%s[%d]: code: %s\n", current->comm,
1310 current->pid, s.buffer);
1319 static struct regbit msr_bits[] = {
1320 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1342 #ifndef CONFIG_BOOKE
1349 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1353 for (; bits->bit; ++bits)
1354 if (val & bits->bit) {
1355 pr_cont("%s%s", s, bits->name);
1360 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1361 static struct regbit msr_tm_bits[] = {
1368 static void print_tm_bits(unsigned long val)
1371 * This only prints something if at least one of the TM bit is set.
1372 * Inside the TM[], the output means:
1373 * E: Enabled (bit 32)
1374 * S: Suspended (bit 33)
1375 * T: Transactional (bit 34)
1377 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1379 print_bits(val, msr_tm_bits, "");
1384 static void print_tm_bits(unsigned long val) {}
1387 static void print_msr_bits(unsigned long val)
1390 print_bits(val, msr_bits, ",");
1396 #define REG "%016lx"
1397 #define REGS_PER_LINE 4
1398 #define LAST_VOLATILE 13
1401 #define REGS_PER_LINE 8
1402 #define LAST_VOLATILE 12
1405 void show_regs(struct pt_regs * regs)
1409 show_regs_print_info(KERN_DEFAULT);
1411 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1412 regs->nip, regs->link, regs->ctr);
1413 printk("REGS: %px TRAP: %04lx %s (%s)\n",
1414 regs, regs->trap, print_tainted(), init_utsname()->release);
1415 printk("MSR: "REG" ", regs->msr);
1416 print_msr_bits(regs->msr);
1417 pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
1419 if ((TRAP(regs) != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1420 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1421 if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1422 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1423 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1425 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1428 pr_cont("IRQMASK: %lx ", regs->softe);
1430 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1431 if (MSR_TM_ACTIVE(regs->msr))
1432 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1435 for (i = 0; i < 32; i++) {
1436 if ((i % REGS_PER_LINE) == 0)
1437 pr_cont("\nGPR%02d: ", i);
1438 pr_cont(REG " ", regs->gpr[i]);
1439 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1443 #ifdef CONFIG_KALLSYMS
1445 * Lookup NIP late so we have the best change of getting the
1446 * above info out without failing
1448 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1449 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1451 show_stack(current, (unsigned long *) regs->gpr[1]);
1452 if (!user_mode(regs))
1453 show_instructions(regs);
1456 void flush_thread(void)
1458 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1459 flush_ptrace_hw_breakpoint(current);
1460 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1461 set_debug_reg_defaults(¤t->thread);
1462 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1465 #ifdef CONFIG_PPC_BOOK3S_64
1466 void arch_setup_new_exec(void)
1468 if (radix_enabled())
1470 hash__setup_new_exec();
1474 int set_thread_uses_vas(void)
1476 #ifdef CONFIG_PPC_BOOK3S_64
1477 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1480 current->thread.used_vas = 1;
1483 * Even a process that has no foreign real address mapping can use
1484 * an unpaired COPY instruction (to no real effect). Issue CP_ABORT
1485 * to clear any pending COPY and prevent a covert channel.
1487 * __switch_to() will issue CP_ABORT on future context switches.
1489 asm volatile(PPC_CP_ABORT);
1491 #endif /* CONFIG_PPC_BOOK3S_64 */
1497 * Assign a TIDR (thread ID) for task @t and set it in the thread
1498 * structure. For now, we only support setting TIDR for 'current' task.
1500 * Since the TID value is a truncated form of it PID, it is possible
1501 * (but unlikely) for 2 threads to have the same TID. In the unlikely event
1502 * that 2 threads share the same TID and are waiting, one of the following
1503 * cases will happen:
1505 * 1. The correct thread is running, the wrong thread is not
1506 * In this situation, the correct thread is woken and proceeds to pass it's
1509 * 2. Neither threads are running
1510 * In this situation, neither thread will be woken. When scheduled, the waiting
1511 * threads will execute either a wait, which will return immediately, followed
1512 * by a condition check, which will pass for the correct thread and fail
1513 * for the wrong thread, or they will execute the condition check immediately.
1515 * 3. The wrong thread is running, the correct thread is not
1516 * The wrong thread will be woken, but will fail it's condition check and
1517 * re-execute wait. The correct thread, when scheduled, will execute either
1518 * it's condition check (which will pass), or wait, which returns immediately
1519 * when called the first time after the thread is scheduled, followed by it's
1520 * condition check (which will pass).
1522 * 4. Both threads are running
1523 * Both threads will be woken. The wrong thread will fail it's condition check
1524 * and execute another wait, while the correct thread will pass it's condition
1527 * @t: the task to set the thread ID for
1529 int set_thread_tidr(struct task_struct *t)
1531 if (!cpu_has_feature(CPU_FTR_P9_TIDR))
1540 t->thread.tidr = (u16)task_pid_nr(t);
1541 mtspr(SPRN_TIDR, t->thread.tidr);
1545 EXPORT_SYMBOL_GPL(set_thread_tidr);
1547 #endif /* CONFIG_PPC64 */
1550 release_thread(struct task_struct *t)
1555 * this gets called so that we can store coprocessor state into memory and
1556 * copy the current task into the new thread.
1558 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1560 flush_all_to_thread(src);
1562 * Flush TM state out so we can copy it. __switch_to_tm() does this
1563 * flush but it removes the checkpointed state from the current CPU and
1564 * transitions the CPU out of TM mode. Hence we need to call
1565 * tm_recheckpoint_new_task() (on the same task) to restore the
1566 * checkpointed state back and the TM mode.
1568 * Can't pass dst because it isn't ready. Doesn't matter, passing
1569 * dst is only important for __switch_to()
1571 __switch_to_tm(src, src);
1575 clear_task_ebb(dst);
1580 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1582 #ifdef CONFIG_PPC_BOOK3S_64
1583 unsigned long sp_vsid;
1584 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1586 if (radix_enabled())
1589 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1590 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1591 << SLB_VSID_SHIFT_1T;
1593 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1595 sp_vsid |= SLB_VSID_KERNEL | llp;
1596 p->thread.ksp_vsid = sp_vsid;
1605 * Copy architecture-specific thread state
1607 int copy_thread(unsigned long clone_flags, unsigned long usp,
1608 unsigned long kthread_arg, struct task_struct *p)
1610 struct pt_regs *childregs, *kregs;
1611 extern void ret_from_fork(void);
1612 extern void ret_from_kernel_thread(void);
1614 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1615 struct thread_info *ti = task_thread_info(p);
1617 klp_init_thread_info(p);
1619 /* Copy registers */
1620 sp -= sizeof(struct pt_regs);
1621 childregs = (struct pt_regs *) sp;
1622 if (unlikely(p->flags & PF_KTHREAD)) {
1624 memset(childregs, 0, sizeof(struct pt_regs));
1625 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1628 childregs->gpr[14] = ppc_function_entry((void *)usp);
1630 clear_tsk_thread_flag(p, TIF_32BIT);
1631 childregs->softe = IRQS_ENABLED;
1633 childregs->gpr[15] = kthread_arg;
1634 p->thread.regs = NULL; /* no user register state */
1635 ti->flags |= _TIF_RESTOREALL;
1636 f = ret_from_kernel_thread;
1639 struct pt_regs *regs = current_pt_regs();
1640 CHECK_FULL_REGS(regs);
1643 childregs->gpr[1] = usp;
1644 p->thread.regs = childregs;
1645 childregs->gpr[3] = 0; /* Result from fork() */
1646 if (clone_flags & CLONE_SETTLS) {
1648 if (!is_32bit_task())
1649 childregs->gpr[13] = childregs->gpr[6];
1652 childregs->gpr[2] = childregs->gpr[6];
1657 childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1658 sp -= STACK_FRAME_OVERHEAD;
1661 * The way this works is that at some point in the future
1662 * some task will call _switch to switch to the new task.
1663 * That will pop off the stack frame created below and start
1664 * the new task running at ret_from_fork. The new task will
1665 * do some house keeping and then return from the fork or clone
1666 * system call, using the stack frame created above.
1668 ((unsigned long *)sp)[0] = 0;
1669 sp -= sizeof(struct pt_regs);
1670 kregs = (struct pt_regs *) sp;
1671 sp -= STACK_FRAME_OVERHEAD;
1674 p->thread.ksp_limit = (unsigned long)end_of_stack(p);
1676 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1677 p->thread.ptrace_bps[0] = NULL;
1680 p->thread.fp_save_area = NULL;
1681 #ifdef CONFIG_ALTIVEC
1682 p->thread.vr_save_area = NULL;
1685 setup_ksp_vsid(p, sp);
1688 if (cpu_has_feature(CPU_FTR_DSCR)) {
1689 p->thread.dscr_inherit = current->thread.dscr_inherit;
1690 p->thread.dscr = mfspr(SPRN_DSCR);
1692 if (cpu_has_feature(CPU_FTR_HAS_PPR))
1693 childregs->ppr = DEFAULT_PPR;
1697 kregs->nip = ppc_function_entry(f);
1701 void preload_new_slb_context(unsigned long start, unsigned long sp);
1704 * Set up a thread for executing a new program
1706 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1709 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1711 #ifdef CONFIG_PPC_BOOK3S_64
1712 if (!radix_enabled())
1713 preload_new_slb_context(start, sp);
1718 * If we exec out of a kernel thread then thread.regs will not be
1721 if (!current->thread.regs) {
1722 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1723 current->thread.regs = regs - 1;
1726 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1728 * Clear any transactional state, we're exec()ing. The cause is
1729 * not important as there will never be a recheckpoint so it's not
1732 if (MSR_TM_SUSPENDED(mfmsr()))
1733 tm_reclaim_current(0);
1736 memset(regs->gpr, 0, sizeof(regs->gpr));
1744 * We have just cleared all the nonvolatile GPRs, so make
1745 * FULL_REGS(regs) return true. This is necessary to allow
1746 * ptrace to examine the thread immediately after exec.
1753 regs->msr = MSR_USER;
1755 if (!is_32bit_task()) {
1756 unsigned long entry;
1758 if (is_elf2_task()) {
1759 /* Look ma, no function descriptors! */
1764 * The latest iteration of the ABI requires that when
1765 * calling a function (at its global entry point),
1766 * the caller must ensure r12 holds the entry point
1767 * address (so that the function can quickly
1768 * establish addressability).
1770 regs->gpr[12] = start;
1771 /* Make sure that's restored on entry to userspace. */
1772 set_thread_flag(TIF_RESTOREALL);
1776 /* start is a relocated pointer to the function
1777 * descriptor for the elf _start routine. The first
1778 * entry in the function descriptor is the entry
1779 * address of _start and the second entry is the TOC
1780 * value we need to use.
1782 __get_user(entry, (unsigned long __user *)start);
1783 __get_user(toc, (unsigned long __user *)start+1);
1785 /* Check whether the e_entry function descriptor entries
1786 * need to be relocated before we can use them.
1788 if (load_addr != 0) {
1795 regs->msr = MSR_USER64;
1799 regs->msr = MSR_USER32;
1803 current->thread.used_vsr = 0;
1805 current->thread.load_slb = 0;
1806 current->thread.load_fp = 0;
1807 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state));
1808 current->thread.fp_save_area = NULL;
1809 #ifdef CONFIG_ALTIVEC
1810 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state));
1811 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1812 current->thread.vr_save_area = NULL;
1813 current->thread.vrsave = 0;
1814 current->thread.used_vr = 0;
1815 current->thread.load_vec = 0;
1816 #endif /* CONFIG_ALTIVEC */
1818 memset(current->thread.evr, 0, sizeof(current->thread.evr));
1819 current->thread.acc = 0;
1820 current->thread.spefscr = 0;
1821 current->thread.used_spe = 0;
1822 #endif /* CONFIG_SPE */
1823 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1824 current->thread.tm_tfhar = 0;
1825 current->thread.tm_texasr = 0;
1826 current->thread.tm_tfiar = 0;
1827 current->thread.load_tm = 0;
1828 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1830 thread_pkey_regs_init(¤t->thread);
1832 EXPORT_SYMBOL(start_thread);
1834 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1835 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1837 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1839 struct pt_regs *regs = tsk->thread.regs;
1841 /* This is a bit hairy. If we are an SPE enabled processor
1842 * (have embedded fp) we store the IEEE exception enable flags in
1843 * fpexc_mode. fpexc_mode is also used for setting FP exception
1844 * mode (asyn, precise, disabled) for 'Classic' FP. */
1845 if (val & PR_FP_EXC_SW_ENABLE) {
1847 if (cpu_has_feature(CPU_FTR_SPE)) {
1849 * When the sticky exception bits are set
1850 * directly by userspace, it must call prctl
1851 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1852 * in the existing prctl settings) or
1853 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1854 * the bits being set). <fenv.h> functions
1855 * saving and restoring the whole
1856 * floating-point environment need to do so
1857 * anyway to restore the prctl settings from
1858 * the saved environment.
1860 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1861 tsk->thread.fpexc_mode = val &
1862 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1872 /* on a CONFIG_SPE this does not hurt us. The bits that
1873 * __pack_fe01 use do not overlap with bits used for
1874 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1875 * on CONFIG_SPE implementations are reserved so writing to
1876 * them does not change anything */
1877 if (val > PR_FP_EXC_PRECISE)
1879 tsk->thread.fpexc_mode = __pack_fe01(val);
1880 if (regs != NULL && (regs->msr & MSR_FP) != 0)
1881 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1882 | tsk->thread.fpexc_mode;
1886 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1890 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1892 if (cpu_has_feature(CPU_FTR_SPE)) {
1894 * When the sticky exception bits are set
1895 * directly by userspace, it must call prctl
1896 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1897 * in the existing prctl settings) or
1898 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1899 * the bits being set). <fenv.h> functions
1900 * saving and restoring the whole
1901 * floating-point environment need to do so
1902 * anyway to restore the prctl settings from
1903 * the saved environment.
1905 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1906 val = tsk->thread.fpexc_mode;
1913 val = __unpack_fe01(tsk->thread.fpexc_mode);
1914 return put_user(val, (unsigned int __user *) adr);
1917 int set_endian(struct task_struct *tsk, unsigned int val)
1919 struct pt_regs *regs = tsk->thread.regs;
1921 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1922 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1928 if (val == PR_ENDIAN_BIG)
1929 regs->msr &= ~MSR_LE;
1930 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1931 regs->msr |= MSR_LE;
1938 int get_endian(struct task_struct *tsk, unsigned long adr)
1940 struct pt_regs *regs = tsk->thread.regs;
1943 if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1944 !cpu_has_feature(CPU_FTR_REAL_LE))
1950 if (regs->msr & MSR_LE) {
1951 if (cpu_has_feature(CPU_FTR_REAL_LE))
1952 val = PR_ENDIAN_LITTLE;
1954 val = PR_ENDIAN_PPC_LITTLE;
1956 val = PR_ENDIAN_BIG;
1958 return put_user(val, (unsigned int __user *)adr);
1961 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1963 tsk->thread.align_ctl = val;
1967 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1969 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1972 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1973 unsigned long nbytes)
1975 unsigned long stack_page;
1976 unsigned long cpu = task_cpu(p);
1978 stack_page = (unsigned long)hardirq_ctx[cpu];
1979 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1982 stack_page = (unsigned long)softirq_ctx[cpu];
1983 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
1989 int validate_sp(unsigned long sp, struct task_struct *p,
1990 unsigned long nbytes)
1992 unsigned long stack_page = (unsigned long)task_stack_page(p);
1994 if (sp < THREAD_SIZE)
1997 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2000 return valid_irq_stack(sp, p, nbytes);
2003 EXPORT_SYMBOL(validate_sp);
2005 static unsigned long __get_wchan(struct task_struct *p)
2007 unsigned long ip, sp;
2010 if (!p || p == current || p->state == TASK_RUNNING)
2014 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
2018 sp = *(unsigned long *)sp;
2019 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) ||
2020 p->state == TASK_RUNNING)
2023 ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
2024 if (!in_sched_functions(ip))
2027 } while (count++ < 16);
2031 unsigned long get_wchan(struct task_struct *p)
2035 if (!try_get_task_stack(p))
2038 ret = __get_wchan(p);
2045 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
2047 void show_stack(struct task_struct *tsk, unsigned long *stack)
2049 unsigned long sp, ip, lr, newsp;
2052 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2053 struct ftrace_ret_stack *ret_stack;
2054 extern void return_to_handler(void);
2055 unsigned long rth = (unsigned long)return_to_handler;
2062 if (!try_get_task_stack(tsk))
2065 sp = (unsigned long) stack;
2068 sp = current_stack_pointer();
2070 sp = tsk->thread.ksp;
2074 printk("Call Trace:\n");
2076 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
2079 stack = (unsigned long *) sp;
2081 ip = stack[STACK_FRAME_LR_SAVE];
2082 if (!firstframe || ip != lr) {
2083 printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
2084 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
2085 if ((ip == rth) && curr_frame >= 0) {
2086 ret_stack = ftrace_graph_get_ret_stack(current,
2090 (void *)ret_stack->ret);
2096 pr_cont(" (unreliable)");
2102 * See if this is an exception frame.
2103 * We look for the "regshere" marker in the current frame.
2105 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
2106 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
2107 struct pt_regs *regs = (struct pt_regs *)
2108 (sp + STACK_FRAME_OVERHEAD);
2110 printk("--- interrupt: %lx at %pS\n LR = %pS\n",
2111 regs->trap, (void *)regs->nip, (void *)lr);
2116 } while (count++ < kstack_depth_to_print);
2118 put_task_stack(tsk);
2122 /* Called with hard IRQs off */
2123 void notrace __ppc64_runlatch_on(void)
2125 struct thread_info *ti = current_thread_info();
2127 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2129 * Least significant bit (RUN) is the only writable bit of
2130 * the CTRL register, so we can avoid mfspr. 2.06 is not the
2131 * earliest ISA where this is the case, but it's convenient.
2133 mtspr(SPRN_CTRLT, CTRL_RUNLATCH);
2138 * Some architectures (e.g., Cell) have writable fields other
2139 * than RUN, so do the read-modify-write.
2141 ctrl = mfspr(SPRN_CTRLF);
2142 ctrl |= CTRL_RUNLATCH;
2143 mtspr(SPRN_CTRLT, ctrl);
2146 ti->local_flags |= _TLF_RUNLATCH;
2149 /* Called with hard IRQs off */
2150 void notrace __ppc64_runlatch_off(void)
2152 struct thread_info *ti = current_thread_info();
2154 ti->local_flags &= ~_TLF_RUNLATCH;
2156 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2157 mtspr(SPRN_CTRLT, 0);
2161 ctrl = mfspr(SPRN_CTRLF);
2162 ctrl &= ~CTRL_RUNLATCH;
2163 mtspr(SPRN_CTRLT, ctrl);
2166 #endif /* CONFIG_PPC64 */
2168 unsigned long arch_align_stack(unsigned long sp)
2170 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
2171 sp -= get_random_int() & ~PAGE_MASK;
2175 static inline unsigned long brk_rnd(void)
2177 unsigned long rnd = 0;
2179 /* 8MB for 32bit, 1GB for 64bit */
2180 if (is_32bit_task())
2181 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
2183 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
2185 return rnd << PAGE_SHIFT;
2188 unsigned long arch_randomize_brk(struct mm_struct *mm)
2190 unsigned long base = mm->brk;
2193 #ifdef CONFIG_PPC_BOOK3S_64
2195 * If we are using 1TB segments and we are allowed to randomise
2196 * the heap, we can put it above 1TB so it is backed by a 1TB
2197 * segment. Otherwise the heap will be in the bottom 1TB
2198 * which always uses 256MB segments and this may result in a
2199 * performance penalty. We don't need to worry about radix. For
2200 * radix, mmu_highuser_ssize remains unchanged from 256MB.
2202 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2203 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2206 ret = PAGE_ALIGN(base + brk_rnd());