arch/powerpc/kernel/ppc970-pmu.c

   1 /*
   2  * Performance counter support for PPC970-family processors.
   3  *
   4  * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/string.h>
  12 #include <linux/perf_counter.h>
  13 #include <asm/reg.h>
  14
  15 /*
  16  * Bits in event code for PPC970
  17  */
  18 #define PM_PMC_SH       12      /* PMC number (1-based) for direct events */
  19 #define PM_PMC_MSK      0xf
  20 #define PM_UNIT_SH      8       /* TTMMUX number and setting - unit select */
  21 #define PM_UNIT_MSK     0xf
  22 #define PM_SPCSEL_SH    6
  23 #define PM_SPCSEL_MSK   3
  24 #define PM_BYTE_SH      4       /* Byte number of event bus to use */
  25 #define PM_BYTE_MSK     3
  26 #define PM_PMCSEL_MSK   0xf
  27
  28 /* Values in PM_UNIT field */
  29 #define PM_NONE         0
  30 #define PM_FPU          1
  31 #define PM_VPU          2
  32 #define PM_ISU          3
  33 #define PM_IFU          4
  34 #define PM_IDU          5
  35 #define PM_STS          6
  36 #define PM_LSU0         7
  37 #define PM_LSU1U        8
  38 #define PM_LSU1L        9
  39 #define PM_LASTUNIT     9
  40
  41 /*
  42  * Bits in MMCR0 for PPC970
  43  */
  44 #define MMCR0_PMC1SEL_SH        8
  45 #define MMCR0_PMC2SEL_SH        1
  46 #define MMCR_PMCSEL_MSK         0x1f
  47
  48 /*
  49  * Bits in MMCR1 for PPC970
  50  */
  51 #define MMCR1_TTM0SEL_SH        62
  52 #define MMCR1_TTM1SEL_SH        59
  53 #define MMCR1_TTM3SEL_SH        53
  54 #define MMCR1_TTMSEL_MSK        3
  55 #define MMCR1_TD_CP_DBG0SEL_SH  50
  56 #define MMCR1_TD_CP_DBG1SEL_SH  48
  57 #define MMCR1_TD_CP_DBG2SEL_SH  46
  58 #define MMCR1_TD_CP_DBG3SEL_SH  44
  59 #define MMCR1_PMC1_ADDER_SEL_SH 39
  60 #define MMCR1_PMC2_ADDER_SEL_SH 38
  61 #define MMCR1_PMC6_ADDER_SEL_SH 37
  62 #define MMCR1_PMC5_ADDER_SEL_SH 36
  63 #define MMCR1_PMC8_ADDER_SEL_SH 35
  64 #define MMCR1_PMC7_ADDER_SEL_SH 34
  65 #define MMCR1_PMC3_ADDER_SEL_SH 33
  66 #define MMCR1_PMC4_ADDER_SEL_SH 32
  67 #define MMCR1_PMC3SEL_SH        27
  68 #define MMCR1_PMC4SEL_SH        22
  69 #define MMCR1_PMC5SEL_SH        17
  70 #define MMCR1_PMC6SEL_SH        12
  71 #define MMCR1_PMC7SEL_SH        7
  72 #define MMCR1_PMC8SEL_SH        2
  73
  74 static short mmcr1_adder_bits[8] = {
  75         MMCR1_PMC1_ADDER_SEL_SH,
  76         MMCR1_PMC2_ADDER_SEL_SH,
  77         MMCR1_PMC3_ADDER_SEL_SH,
  78         MMCR1_PMC4_ADDER_SEL_SH,
  79         MMCR1_PMC5_ADDER_SEL_SH,
  80         MMCR1_PMC6_ADDER_SEL_SH,
  81         MMCR1_PMC7_ADDER_SEL_SH,
  82         MMCR1_PMC8_ADDER_SEL_SH
  83 };
  84
  85 /*
  86  * Bits in MMCRA
  87  */
  88
  89 /*
  90  * Layout of constraint bits:
  91  * 6666555555555544444444443333333333222222222211111111110000000000
  92  * 3210987654321098765432109876543210987654321098765432109876543210
  93  *               <><><>[  >[  >[  ><  ><  ><  ><  ><><><><><><><><>
  94  *               SPT0T1 UC  PS1 PS2 B0  B1  B2  B3 P1P2P3P4P5P6P7P8
  95  *
  96  * SP - SPCSEL constraint
  97  *     48-49: SPCSEL value 0x3_0000_0000_0000
  98  *
  99  * T0 - TTM0 constraint
 100  *     46-47: TTM0SEL value (0=FPU, 2=IFU, 3=VPU) 0xC000_0000_0000
 101  *
 102  * T1 - TTM1 constraint
 103  *     44-45: TTM1SEL value (0=IDU, 3=STS) 0x3000_0000_0000
 104  *
 105  * UC - unit constraint: can't have all three of FPU|IFU|VPU, ISU, IDU|STS
 106  *     43: UC3 error 0x0800_0000_0000
 107  *     42: FPU|IFU|VPU events needed 0x0400_0000_0000
 108  *     41: ISU events needed 0x0200_0000_0000
 109  *     40: IDU|STS events needed 0x0100_0000_0000
 110  *
 111  * PS1
 112  *     39: PS1 error 0x0080_0000_0000
 113  *     36-38: count of events needing PMC1/2/5/6 0x0070_0000_0000
 114  *
 115  * PS2
 116  *     35: PS2 error 0x0008_0000_0000
 117  *     32-34: count of events needing PMC3/4/7/8 0x0007_0000_0000
 118  *
 119  * B0
 120  *     28-31: Byte 0 event source 0xf000_0000
 121  *            Encoding as for the event code
 122  *
 123  * B1, B2, B3
 124  *     24-27, 20-23, 16-19: Byte 1, 2, 3 event sources
 125  *
 126  * P1
 127  *     15: P1 error 0x8000
 128  *     14-15: Count of events needing PMC1
 129  *
 130  * P2..P8
 131  *     0-13: Count of events needing PMC2..PMC8
 132  */
 133
 134 static unsigned char direct_marked_event[8] = {
 135         (1<<2) | (1<<3),        /* PMC1: PM_MRK_GRP_DISP, PM_MRK_ST_CMPL */
 136         (1<<3) | (1<<5),        /* PMC2: PM_THRESH_TIMEO, PM_MRK_BRU_FIN */
 137         (1<<3) | (1<<5),        /* PMC3: PM_MRK_ST_CMPL_INT, PM_MRK_VMX_FIN */
 138         (1<<4) | (1<<5),        /* PMC4: PM_MRK_GRP_CMPL, PM_MRK_CRU_FIN */
 139         (1<<4) | (1<<5),        /* PMC5: PM_GRP_MRK, PM_MRK_GRP_TIMEO */
 140         (1<<3) | (1<<4) | (1<<5),
 141                 /* PMC6: PM_MRK_ST_STS, PM_MRK_FXU_FIN, PM_MRK_GRP_ISSUED */
 142         (1<<4) | (1<<5),        /* PMC7: PM_MRK_FPU_FIN, PM_MRK_INST_FIN */
 143         (1<<4)                  /* PMC8: PM_MRK_LSU_FIN */
 144 };
 145
 146 /*
 147  * Returns 1 if event counts things relating to marked instructions
 148  * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
 149  */
 150 static int p970_marked_instr_event(u64 event)
 151 {
 152         int pmc, psel, unit, byte, bit;
 153         unsigned int mask;
 154
 155         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 156         psel = event & PM_PMCSEL_MSK;
 157         if (pmc) {
 158                 if (direct_marked_event[pmc - 1] & (1 << psel))
 159                         return 1;
 160                 if (psel == 0)          /* add events */
 161                         bit = (pmc <= 4)? pmc - 1: 8 - pmc;
 162                 else if (psel == 7 || psel == 13)       /* decode events */
 163                         bit = 4;
 164                 else
 165                         return 0;
 166         } else
 167                 bit = psel;
 168
 169         byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
 170         unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
 171         mask = 0;
 172         switch (unit) {
 173         case PM_VPU:
 174                 mask = 0x4c;            /* byte 0 bits 2,3,6 */
 175         case PM_LSU0:
 176                 /* byte 2 bits 0,2,3,4,6; all of byte 1 */
 177                 mask = 0x085dff00;
 178         case PM_LSU1L:
 179                 mask = 0x50 << 24;      /* byte 3 bits 4,6 */
 180                 break;
 181         }
 182         return (mask >> (byte * 8 + bit)) & 1;
 183 }
 184
 185 /* Masks and values for using events from the various units */
 186 static unsigned long unit_cons[PM_LASTUNIT+1][2] = {
 187         [PM_FPU] =   { 0xc80000000000ull, 0x040000000000ull },
 188         [PM_VPU] =   { 0xc80000000000ull, 0xc40000000000ull },
 189         [PM_ISU] =   { 0x080000000000ull, 0x020000000000ull },
 190         [PM_IFU] =   { 0xc80000000000ull, 0x840000000000ull },
 191         [PM_IDU] =   { 0x380000000000ull, 0x010000000000ull },
 192         [PM_STS] =   { 0x380000000000ull, 0x310000000000ull },
 193 };
 194
 195 static int p970_get_constraint(u64 event, unsigned long *maskp,
 196                                unsigned long *valp)
 197 {
 198         int pmc, byte, unit, sh, spcsel;
 199         unsigned long mask = 0, value = 0;
 200         int grp = -1;
 201
 202         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
 203         if (pmc) {
 204                 if (pmc > 8)
 205                         return -1;
 206                 sh = (pmc - 1) * 2;
 207                 mask |= 2 << sh;
 208                 value |= 1 << sh;
 209                 grp = ((pmc - 1) >> 1) & 1;
 210         }
 211         unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
 212         if (unit) {
 213                 if (unit > PM_LASTUNIT)
 214                         return -1;
 215                 mask |= unit_cons[unit][0];
 216                 value |= unit_cons[unit][1];
 217                 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
 218                 /*
 219                  * Bus events on bytes 0 and 2 can be counted
 220                  * on PMC1/2/5/6; bytes 1 and 3 on PMC3/4/7/8.
 221                  */
 222                 if (!pmc)
 223                         grp = byte & 1;
 224                 /* Set byte lane select field */
 225                 mask  |= 0xfULL << (28 - 4 * byte);
 226                 value |= (unsigned long)unit << (28 - 4 * byte);
 227         }
 228         if (grp == 0) {
 229                 /* increment PMC1/2/5/6 field */
 230                 mask  |= 0x8000000000ull;
 231                 value |= 0x1000000000ull;
 232         } else if (grp == 1) {
 233                 /* increment PMC3/4/7/8 field */
 234                 mask  |= 0x800000000ull;
 235                 value |= 0x100000000ull;
 236         }
 237         spcsel = (event >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
 238         if (spcsel) {
 239                 mask  |= 3ull << 48;
 240                 value |= (unsigned long)spcsel << 48;
 241         }
 242         *maskp = mask;
 243         *valp = value;
 244         return 0;
 245 }
 246
 247 static int p970_get_alternatives(u64 event, unsigned int flags, u64 alt[])
 248 {
 249         alt[0] = event;
 250
 251         /* 2 alternatives for LSU empty */
 252         if (event == 0x2002 || event == 0x3002) {
 253                 alt[1] = event ^ 0x1000;
 254                 return 2;
 255         }
 256
 257         return 1;
 258 }
 259
 260 static int p970_compute_mmcr(u64 event[], int n_ev,
 261                              unsigned int hwc[], unsigned long mmcr[])
 262 {
 263         unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0;
 264         unsigned int pmc, unit, byte, psel;
 265         unsigned int ttm, grp;
 266         unsigned int pmc_inuse = 0;
 267         unsigned int pmc_grp_use[2];
 268         unsigned char busbyte[4];
 269         unsigned char unituse[16];
 270         unsigned char unitmap[] = { 0, 0<<3, 3<<3, 1<<3, 2<<3, 0|4, 3|4 };
 271         unsigned char ttmuse[2];
 272         unsigned char pmcsel[8];
 273         int i;
 274         int spcsel;
 275
 276         if (n_ev > 8)
 277                 return -1;
 278
 279         /* First pass to count resource use */
 280         pmc_grp_use[0] = pmc_grp_use[1] = 0;
 281         memset(busbyte, 0, sizeof(busbyte));
 282         memset(unituse, 0, sizeof(unituse));
 283         for (i = 0; i < n_ev; ++i) {
 284                 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
 285                 if (pmc) {
 286                         if (pmc_inuse & (1 << (pmc - 1)))
 287                                 return -1;
 288                         pmc_inuse |= 1 << (pmc - 1);
 289                         /* count 1/2/5/6 vs 3/4/7/8 use */
 290                         ++pmc_grp_use[((pmc - 1) >> 1) & 1];
 291                 }
 292                 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
 293                 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
 294                 if (unit) {
 295                         if (unit > PM_LASTUNIT)
 296                                 return -1;
 297                         if (!pmc)
 298                                 ++pmc_grp_use[byte & 1];
 299                         if (busbyte[byte] && busbyte[byte] != unit)
 300                                 return -1;
 301                         busbyte[byte] = unit;
 302                         unituse[unit] = 1;
 303                 }
 304         }
 305         if (pmc_grp_use[0] > 4 || pmc_grp_use[1] > 4)
 306                 return -1;
 307
 308         /*
 309          * Assign resources and set multiplexer selects.
 310          *
 311          * PM_ISU can go either on TTM0 or TTM1, but that's the only
 312          * choice we have to deal with.
 313          */
 314         if (unituse[PM_ISU] &
 315             (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_VPU]))
 316                 unitmap[PM_ISU] = 2 | 4;        /* move ISU to TTM1 */
 317         /* Set TTM[01]SEL fields. */
 318         ttmuse[0] = ttmuse[1] = 0;
 319         for (i = PM_FPU; i <= PM_STS; ++i) {
 320                 if (!unituse[i])
 321                         continue;
 322                 ttm = unitmap[i];
 323                 ++ttmuse[(ttm >> 2) & 1];
 324                 mmcr1 |= (unsigned long)(ttm & ~4) << MMCR1_TTM1SEL_SH;
 325         }
 326         /* Check only one unit per TTMx */
 327         if (ttmuse[0] > 1 || ttmuse[1] > 1)
 328                 return -1;
 329
 330         /* Set byte lane select fields and TTM3SEL. */
 331         for (byte = 0; byte < 4; ++byte) {
 332                 unit = busbyte[byte];
 333                 if (!unit)
 334                         continue;
 335                 if (unit <= PM_STS)
 336                         ttm = (unitmap[unit] >> 2) & 1;
 337                 else if (unit == PM_LSU0)
 338                         ttm = 2;
 339                 else {
 340                         ttm = 3;
 341                         if (unit == PM_LSU1L && byte >= 2)
 342                                 mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
 343                 }
 344                 mmcr1 |= (unsigned long)ttm
 345                         << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
 346         }
 347
 348         /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
 349         memset(pmcsel, 0x8, sizeof(pmcsel));    /* 8 means don't count */
 350         for (i = 0; i < n_ev; ++i) {
 351                 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
 352                 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
 353                 byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
 354                 psel = event[i] & PM_PMCSEL_MSK;
 355                 if (!pmc) {
 356                         /* Bus event or any-PMC direct event */
 357                         if (unit)
 358                                 psel |= 0x10 | ((byte & 2) << 2);
 359                         else
 360                                 psel |= 8;
 361                         for (pmc = 0; pmc < 8; ++pmc) {
 362                                 if (pmc_inuse & (1 << pmc))
 363                                         continue;
 364                                 grp = (pmc >> 1) & 1;
 365                                 if (unit) {
 366                                         if (grp == (byte & 1))
 367                                                 break;
 368                                 } else if (pmc_grp_use[grp] < 4) {
 369                                         ++pmc_grp_use[grp];
 370                                         break;
 371                                 }
 372                         }
 373                         pmc_inuse |= 1 << pmc;
 374                 } else {
 375                         /* Direct event */
 376                         --pmc;
 377                         if (psel == 0 && (byte & 2))
 378                                 /* add events on higher-numbered bus */
 379                                 mmcr1 |= 1ull << mmcr1_adder_bits[pmc];
 380                 }
 381                 pmcsel[pmc] = psel;
 382                 hwc[i] = pmc;
 383                 spcsel = (event[i] >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
 384                 mmcr1 |= spcsel;
 385                 if (p970_marked_instr_event(event[i]))
 386                         mmcra |= MMCRA_SAMPLE_ENABLE;
 387         }
 388         for (pmc = 0; pmc < 2; ++pmc)
 389                 mmcr0 |= pmcsel[pmc] << (MMCR0_PMC1SEL_SH - 7 * pmc);
 390         for (; pmc < 8; ++pmc)
 391                 mmcr1 |= (unsigned long)pmcsel[pmc]
 392                         << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2));
 393         if (pmc_inuse & 1)
 394                 mmcr0 |= MMCR0_PMC1CE;
 395         if (pmc_inuse & 0xfe)
 396                 mmcr0 |= MMCR0_PMCjCE;
 397
 398         mmcra |= 0x2000;        /* mark only one IOP per PPC instruction */
 399
 400         /* Return MMCRx values */
 401         mmcr[0] = mmcr0;
 402         mmcr[1] = mmcr1;
 403         mmcr[2] = mmcra;
 404         return 0;
 405 }
 406
 407 static void p970_disable_pmc(unsigned int pmc, unsigned long mmcr[])
 408 {
 409         int shift, i;
 410
 411         if (pmc <= 1) {
 412                 shift = MMCR0_PMC1SEL_SH - 7 * pmc;
 413                 i = 0;
 414         } else {
 415                 shift = MMCR1_PMC3SEL_SH - 5 * (pmc - 2);
 416                 i = 1;
 417         }
 418         /*
 419          * Setting the PMCxSEL field to 0x08 disables PMC x.
 420          */
 421         mmcr[i] = (mmcr[i] & ~(0x1fUL << shift)) | (0x08UL << shift);
 422 }
 423
 424 static int ppc970_generic_events[] = {
 425         [PERF_COUNT_HW_CPU_CYCLES]              = 7,
 426         [PERF_COUNT_HW_INSTRUCTIONS]            = 1,
 427         [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x8810, /* PM_LD_REF_L1 */
 428         [PERF_COUNT_HW_CACHE_MISSES]            = 0x3810, /* PM_LD_MISS_L1 */
 429         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x431,  /* PM_BR_ISSUED */
 430         [PERF_COUNT_HW_BRANCH_MISSES]           = 0x327,  /* PM_GRP_BR_MPRED */
 431 };
 432
 433 #define C(x)    PERF_COUNT_HW_CACHE_##x
 434
 435 /*
 436  * Table of generalized cache-related events.
 437  * 0 means not supported, -1 means nonsensical, other values
 438  * are event codes.
 439  */
 440 static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 441         [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 442                 [C(OP_READ)] = {        0x8810,         0x3810  },
 443                 [C(OP_WRITE)] = {       0x7810,         0x813   },
 444                 [C(OP_PREFETCH)] = {    0x731,          0       },
 445         },
 446         [C(L1I)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 447                 [C(OP_READ)] = {        0,              0       },
 448                 [C(OP_WRITE)] = {       -1,             -1      },
 449                 [C(OP_PREFETCH)] = {    0,              0       },
 450         },
 451         [C(LL)] = {             /*      RESULT_ACCESS   RESULT_MISS */
 452                 [C(OP_READ)] = {        0,              0       },
 453                 [C(OP_WRITE)] = {       0,              0       },
 454                 [C(OP_PREFETCH)] = {    0x733,          0       },
 455         },
 456         [C(DTLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
 457                 [C(OP_READ)] = {        0,              0x704   },
 458                 [C(OP_WRITE)] = {       -1,             -1      },
 459                 [C(OP_PREFETCH)] = {    -1,             -1      },
 460         },
 461         [C(ITLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
 462                 [C(OP_READ)] = {        0,              0x700   },
 463                 [C(OP_WRITE)] = {       -1,             -1      },
 464                 [C(OP_PREFETCH)] = {    -1,             -1      },
 465         },
 466         [C(BPU)] = {            /*      RESULT_ACCESS   RESULT_MISS */
 467                 [C(OP_READ)] = {        0x431,          0x327   },
 468                 [C(OP_WRITE)] = {       -1,             -1      },
 469                 [C(OP_PREFETCH)] = {    -1,             -1      },
 470         },
 471 };
 472
 473 struct power_pmu ppc970_pmu = {
 474         .n_counter              = 8,
 475         .max_alternatives       = 2,
 476         .add_fields             = 0x001100005555ull,
 477         .test_adder             = 0x013300000000ull,
 478         .compute_mmcr           = p970_compute_mmcr,
 479         .get_constraint         = p970_get_constraint,
 480         .get_alternatives       = p970_get_alternatives,
 481         .disable_pmc            = p970_disable_pmc,
 482         .n_generic              = ARRAY_SIZE(ppc970_generic_events),
 483         .generic_events         = ppc970_generic_events,
 484         .cache_events           = &ppc970_cache_events,
 485 };