2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/list.h>
29 #include <linux/syscalls.h>
30 #include <linux/irq.h>
31 #include <linux/vmalloc.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
35 #include <asm/processor.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/byteorder.h>
40 #include <asm/machdep.h>
41 #include <asm/ppc-pci.h>
44 /* hose_spinlock protects accesses to the the phb_bitmap. */
45 static DEFINE_SPINLOCK(hose_spinlock);
48 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
49 #define MAX_PHBS 0x10000
52 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
53 * Accesses to this bitmap should be protected by hose_spinlock.
55 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
57 /* ISA Memory physical address */
58 resource_size_t isa_mem_base;
61 static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
63 void set_pci_dma_ops(struct dma_map_ops *dma_ops)
65 pci_dma_ops = dma_ops;
68 struct dma_map_ops *get_pci_dma_ops(void)
72 EXPORT_SYMBOL(get_pci_dma_ops);
75 * This function should run under locking protection, specifically
78 static int get_phb_number(struct device_node *dn)
85 * Try fixed PHB numbering first, by checking archs and reading
86 * the respective device-tree properties. Firstly, try powernv by
87 * reading "ibm,opal-phbid", only present in OPAL environment.
89 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
91 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
96 phb_id = (int)(prop & (MAX_PHBS - 1));
98 /* We need to be sure to not use the same PHB number twice. */
99 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
103 * If not pseries nor powernv, or if fixed PHB numbering tried to add
104 * the same PHB number twice, then fallback to dynamic PHB numbering.
106 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
107 BUG_ON(phb_id >= MAX_PHBS);
108 set_bit(phb_id, phb_bitmap);
113 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
115 struct pci_controller *phb;
117 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
120 spin_lock(&hose_spinlock);
121 phb->global_number = get_phb_number(dev);
122 list_add_tail(&phb->list_node, &hose_list);
123 spin_unlock(&hose_spinlock);
125 phb->is_dynamic = slab_is_available();
128 int nid = of_node_to_nid(dev);
130 if (nid < 0 || !node_online(nid))
133 PHB_SET_NODE(phb, nid);
138 EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
140 void pcibios_free_controller(struct pci_controller *phb)
142 spin_lock(&hose_spinlock);
144 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
145 if (phb->global_number < MAX_PHBS)
146 clear_bit(phb->global_number, phb_bitmap);
148 list_del(&phb->list_node);
149 spin_unlock(&hose_spinlock);
154 EXPORT_SYMBOL_GPL(pcibios_free_controller);
157 * The function is used to return the minimal alignment
158 * for memory or I/O windows of the associated P2P bridge.
159 * By default, 4KiB alignment for I/O windows and 1MiB for
162 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
165 struct pci_controller *phb = pci_bus_to_host(bus);
167 if (phb->controller_ops.window_alignment)
168 return phb->controller_ops.window_alignment(bus, type);
171 * PCI core will figure out the default
172 * alignment: 4KiB for I/O and 1MiB for
178 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
180 struct pci_controller *hose = pci_bus_to_host(bus);
182 if (hose->controller_ops.setup_bridge)
183 hose->controller_ops.setup_bridge(bus, type);
186 void pcibios_reset_secondary_bus(struct pci_dev *dev)
188 struct pci_controller *phb = pci_bus_to_host(dev->bus);
190 if (phb->controller_ops.reset_secondary_bus) {
191 phb->controller_ops.reset_secondary_bus(dev);
195 pci_reset_secondary_bus(dev);
198 #ifdef CONFIG_PCI_IOV
199 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
201 if (ppc_md.pcibios_iov_resource_alignment)
202 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
204 return pci_iov_resource_size(pdev, resno);
206 #endif /* CONFIG_PCI_IOV */
208 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
211 return hose->pci_io_size;
213 return resource_size(&hose->io_resource);
217 int pcibios_vaddr_is_ioport(void __iomem *address)
220 struct pci_controller *hose;
221 resource_size_t size;
223 spin_lock(&hose_spinlock);
224 list_for_each_entry(hose, &hose_list, list_node) {
225 size = pcibios_io_size(hose);
226 if (address >= hose->io_base_virt &&
227 address < (hose->io_base_virt + size)) {
232 spin_unlock(&hose_spinlock);
236 unsigned long pci_address_to_pio(phys_addr_t address)
238 struct pci_controller *hose;
239 resource_size_t size;
240 unsigned long ret = ~0;
242 spin_lock(&hose_spinlock);
243 list_for_each_entry(hose, &hose_list, list_node) {
244 size = pcibios_io_size(hose);
245 if (address >= hose->io_base_phys &&
246 address < (hose->io_base_phys + size)) {
248 (unsigned long)hose->io_base_virt - _IO_BASE;
249 ret = base + (address - hose->io_base_phys);
253 spin_unlock(&hose_spinlock);
257 EXPORT_SYMBOL_GPL(pci_address_to_pio);
260 * Return the domain number for this bus.
262 int pci_domain_nr(struct pci_bus *bus)
264 struct pci_controller *hose = pci_bus_to_host(bus);
266 return hose->global_number;
268 EXPORT_SYMBOL(pci_domain_nr);
270 /* This routine is meant to be used early during boot, when the
271 * PCI bus numbers have not yet been assigned, and you need to
272 * issue PCI config cycles to an OF device.
273 * It could also be used to "fix" RTAS config cycles if you want
274 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
277 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
280 struct pci_controller *hose, *tmp;
281 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
282 if (hose->dn == node)
290 * Reads the interrupt pin to determine if interrupt is use by card.
291 * If the interrupt is used, then gets the interrupt line from the
292 * openfirmware and sets it in the pci_dev and pci_config line.
294 static int pci_read_irq_line(struct pci_dev *pci_dev)
296 struct of_phandle_args oirq;
299 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
302 memset(&oirq, 0xff, sizeof(oirq));
304 /* Try to get a mapping from the device-tree */
305 if (of_irq_parse_pci(pci_dev, &oirq)) {
308 /* If that fails, lets fallback to what is in the config
309 * space and map that through the default controller. We
310 * also set the type to level low since that's what PCI
311 * interrupts are. If your platform does differently, then
312 * either provide a proper interrupt tree or don't use this
315 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
319 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
320 line == 0xff || line == 0) {
323 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
326 virq = irq_create_mapping(NULL, line);
328 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
330 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
331 oirq.args_count, oirq.args[0], oirq.args[1],
332 of_node_full_name(oirq.np));
334 virq = irq_create_of_mapping(&oirq);
337 pr_debug(" Failed to map !\n");
341 pr_debug(" Mapped to linux irq %d\n", virq);
349 * Platform support for /proc/bus/pci/X/Y mmap()s,
350 * modelled on the sparc64 implementation by Dave Miller.
355 * Adjust vm_pgoff of VMA such that it is the physical page offset
356 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
358 * Basically, the user finds the base address for his device which he wishes
359 * to mmap. They read the 32-bit value from the config space base register,
360 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
361 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
363 * Returns negative error code on failure, zero on success.
365 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
366 resource_size_t *offset,
367 enum pci_mmap_state mmap_state)
369 struct pci_controller *hose = pci_bus_to_host(dev->bus);
370 unsigned long io_offset = 0;
374 return NULL; /* should never happen */
376 /* If memory, add on the PCI bridge address offset */
377 if (mmap_state == pci_mmap_mem) {
378 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
379 *offset += hose->pci_mem_offset;
381 res_bit = IORESOURCE_MEM;
383 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
384 *offset += io_offset;
385 res_bit = IORESOURCE_IO;
389 * Check that the offset requested corresponds to one of the
390 * resources of the device.
392 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
393 struct resource *rp = &dev->resource[i];
394 int flags = rp->flags;
396 /* treat ROM as memory (should be already) */
397 if (i == PCI_ROM_RESOURCE)
398 flags |= IORESOURCE_MEM;
400 /* Active and same type? */
401 if ((flags & res_bit) == 0)
404 /* In the range of this resource? */
405 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
408 /* found it! construct the final physical address */
409 if (mmap_state == pci_mmap_io)
410 *offset += hose->io_base_phys - io_offset;
418 * This one is used by /dev/mem and fbdev who have no clue about the
419 * PCI device, it tries to find the PCI device first and calls the
422 pgprot_t pci_phys_mem_access_prot(struct file *file,
427 struct pci_dev *pdev = NULL;
428 struct resource *found = NULL;
429 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
432 if (page_is_ram(pfn))
435 prot = pgprot_noncached(prot);
436 for_each_pci_dev(pdev) {
437 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
438 struct resource *rp = &pdev->resource[i];
439 int flags = rp->flags;
441 /* Active and same type? */
442 if ((flags & IORESOURCE_MEM) == 0)
444 /* In the range of this resource? */
445 if (offset < (rp->start & PAGE_MASK) ||
455 if (found->flags & IORESOURCE_PREFETCH)
456 prot = pgprot_noncached_wc(prot);
460 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
461 (unsigned long long)offset, pgprot_val(prot));
468 * Perform the actual remap of the pages for a PCI device mapping, as
469 * appropriate for this architecture. The region in the process to map
470 * is described by vm_start and vm_end members of VMA, the base physical
471 * address is found in vm_pgoff.
472 * The pci device structure is provided so that architectures may make mapping
473 * decisions on a per-device or per-bus basis.
475 * Returns a negative error code on failure, zero on success.
477 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
478 enum pci_mmap_state mmap_state, int write_combine)
480 resource_size_t offset =
481 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
485 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
489 vma->vm_pgoff = offset >> PAGE_SHIFT;
491 vma->vm_page_prot = pgprot_noncached_wc(vma->vm_page_prot);
493 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
495 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
496 vma->vm_end - vma->vm_start, vma->vm_page_prot);
501 /* This provides legacy IO read access on a bus */
502 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
504 unsigned long offset;
505 struct pci_controller *hose = pci_bus_to_host(bus);
506 struct resource *rp = &hose->io_resource;
509 /* Check if port can be supported by that bus. We only check
510 * the ranges of the PHB though, not the bus itself as the rules
511 * for forwarding legacy cycles down bridges are not our problem
512 * here. So if the host bridge supports it, we do it.
514 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
517 if (!(rp->flags & IORESOURCE_IO))
519 if (offset < rp->start || (offset + size) > rp->end)
521 addr = hose->io_base_virt + port;
525 *((u8 *)val) = in_8(addr);
530 *((u16 *)val) = in_le16(addr);
535 *((u32 *)val) = in_le32(addr);
541 /* This provides legacy IO write access on a bus */
542 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
544 unsigned long offset;
545 struct pci_controller *hose = pci_bus_to_host(bus);
546 struct resource *rp = &hose->io_resource;
549 /* Check if port can be supported by that bus. We only check
550 * the ranges of the PHB though, not the bus itself as the rules
551 * for forwarding legacy cycles down bridges are not our problem
552 * here. So if the host bridge supports it, we do it.
554 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
557 if (!(rp->flags & IORESOURCE_IO))
559 if (offset < rp->start || (offset + size) > rp->end)
561 addr = hose->io_base_virt + port;
563 /* WARNING: The generic code is idiotic. It gets passed a pointer
564 * to what can be a 1, 2 or 4 byte quantity and always reads that
565 * as a u32, which means that we have to correct the location of
566 * the data read within those 32 bits for size 1 and 2
570 out_8(addr, val >> 24);
575 out_le16(addr, val >> 16);
586 /* This provides legacy IO or memory mmap access on a bus */
587 int pci_mmap_legacy_page_range(struct pci_bus *bus,
588 struct vm_area_struct *vma,
589 enum pci_mmap_state mmap_state)
591 struct pci_controller *hose = pci_bus_to_host(bus);
592 resource_size_t offset =
593 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
594 resource_size_t size = vma->vm_end - vma->vm_start;
597 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
598 pci_domain_nr(bus), bus->number,
599 mmap_state == pci_mmap_mem ? "MEM" : "IO",
600 (unsigned long long)offset,
601 (unsigned long long)(offset + size - 1));
603 if (mmap_state == pci_mmap_mem) {
606 * Because X is lame and can fail starting if it gets an error trying
607 * to mmap legacy_mem (instead of just moving on without legacy memory
608 * access) we fake it here by giving it anonymous memory, effectively
609 * behaving just like /dev/zero
611 if ((offset + size) > hose->isa_mem_size) {
613 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
614 current->comm, current->pid, pci_domain_nr(bus), bus->number);
615 if (vma->vm_flags & VM_SHARED)
616 return shmem_zero_setup(vma);
619 offset += hose->isa_mem_phys;
621 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
622 unsigned long roffset = offset + io_offset;
623 rp = &hose->io_resource;
624 if (!(rp->flags & IORESOURCE_IO))
626 if (roffset < rp->start || (roffset + size) > rp->end)
628 offset += hose->io_base_phys;
630 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
632 vma->vm_pgoff = offset >> PAGE_SHIFT;
633 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
634 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
635 vma->vm_end - vma->vm_start,
639 void pci_resource_to_user(const struct pci_dev *dev, int bar,
640 const struct resource *rsrc,
641 resource_size_t *start, resource_size_t *end)
643 struct pci_bus_region region;
645 if (rsrc->flags & IORESOURCE_IO) {
646 pcibios_resource_to_bus(dev->bus, ®ion,
647 (struct resource *) rsrc);
648 *start = region.start;
653 /* We pass a CPU physical address to userland for MMIO instead of a
654 * BAR value because X is lame and expects to be able to use that
655 * to pass to /dev/mem!
657 * That means we may have 64-bit values where some apps only expect
658 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
660 *start = rsrc->start;
665 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
666 * @hose: newly allocated pci_controller to be setup
667 * @dev: device node of the host bridge
668 * @primary: set if primary bus (32 bits only, soon to be deprecated)
670 * This function will parse the "ranges" property of a PCI host bridge device
671 * node and setup the resource mapping of a pci controller based on its
674 * Life would be boring if it wasn't for a few issues that we have to deal
677 * - We can only cope with one IO space range and up to 3 Memory space
678 * ranges. However, some machines (thanks Apple !) tend to split their
679 * space into lots of small contiguous ranges. So we have to coalesce.
681 * - Some busses have IO space not starting at 0, which causes trouble with
682 * the way we do our IO resource renumbering. The code somewhat deals with
683 * it for 64 bits but I would expect problems on 32 bits.
685 * - Some 32 bits platforms such as 4xx can have physical space larger than
686 * 32 bits so we need to use 64 bits values for the parsing
688 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
689 struct device_node *dev, int primary)
692 struct resource *res;
693 struct of_pci_range range;
694 struct of_pci_range_parser parser;
696 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
697 dev->full_name, primary ? "(primary)" : "");
699 /* Check for ranges property */
700 if (of_pci_range_parser_init(&parser, dev))
704 for_each_of_pci_range(&parser, &range) {
705 /* If we failed translation or got a zero-sized region
706 * (some FW try to feed us with non sensical zero sized regions
707 * such as power3 which look like some kind of attempt at exposing
708 * the VGA memory hole)
710 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
713 /* Act based on address space type */
715 switch (range.flags & IORESOURCE_TYPE_BITS) {
718 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
719 range.cpu_addr, range.cpu_addr + range.size - 1,
722 /* We support only one IO range */
723 if (hose->pci_io_size) {
725 " \\--> Skipped (too many) !\n");
729 /* On 32 bits, limit I/O space to 16MB */
730 if (range.size > 0x01000000)
731 range.size = 0x01000000;
733 /* 32 bits needs to map IOs here */
734 hose->io_base_virt = ioremap(range.cpu_addr,
737 /* Expect trouble if pci_addr is not 0 */
740 (unsigned long)hose->io_base_virt;
741 #endif /* CONFIG_PPC32 */
742 /* pci_io_size and io_base_phys always represent IO
743 * space starting at 0 so we factor in pci_addr
745 hose->pci_io_size = range.pci_addr + range.size;
746 hose->io_base_phys = range.cpu_addr - range.pci_addr;
749 res = &hose->io_resource;
750 range.cpu_addr = range.pci_addr;
754 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
755 range.cpu_addr, range.cpu_addr + range.size - 1,
757 (range.pci_space & 0x40000000) ?
760 /* We support only 3 memory ranges */
763 " \\--> Skipped (too many) !\n");
766 /* Handles ISA memory hole space here */
767 if (range.pci_addr == 0) {
768 if (primary || isa_mem_base == 0)
769 isa_mem_base = range.cpu_addr;
770 hose->isa_mem_phys = range.cpu_addr;
771 hose->isa_mem_size = range.size;
775 hose->mem_offset[memno] = range.cpu_addr -
777 res = &hose->mem_resources[memno++];
781 res->name = dev->full_name;
782 res->flags = range.flags;
783 res->start = range.cpu_addr;
784 res->end = range.cpu_addr + range.size - 1;
785 res->parent = res->child = res->sibling = NULL;
790 /* Decide whether to display the domain number in /proc */
791 int pci_proc_domain(struct pci_bus *bus)
793 struct pci_controller *hose = pci_bus_to_host(bus);
795 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
797 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
798 return hose->global_number != 0;
802 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
804 if (ppc_md.pcibios_root_bridge_prepare)
805 return ppc_md.pcibios_root_bridge_prepare(bridge);
810 /* This header fixup will do the resource fixup for all devices as they are
811 * probed, but not for bridge ranges
813 static void pcibios_fixup_resources(struct pci_dev *dev)
815 struct pci_controller *hose = pci_bus_to_host(dev->bus);
819 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
827 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
828 struct resource *res = dev->resource + i;
829 struct pci_bus_region reg;
833 /* If we're going to re-assign everything, we mark all resources
834 * as unset (and 0-base them). In addition, we mark BARs starting
835 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
836 * since in that case, we don't want to re-assign anything
838 pcibios_resource_to_bus(dev->bus, ®, res);
839 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
840 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
841 /* Only print message if not re-assigning */
842 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
843 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
844 pci_name(dev), i, res);
845 res->end -= res->start;
847 res->flags |= IORESOURCE_UNSET;
851 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
854 /* Call machine specific resource fixup */
855 if (ppc_md.pcibios_fixup_resources)
856 ppc_md.pcibios_fixup_resources(dev);
858 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
860 /* This function tries to figure out if a bridge resource has been initialized
861 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
862 * things go more smoothly when it gets it right. It should covers cases such
863 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
865 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
866 struct resource *res)
868 struct pci_controller *hose = pci_bus_to_host(bus);
869 struct pci_dev *dev = bus->self;
870 resource_size_t offset;
871 struct pci_bus_region region;
875 /* We don't do anything if PCI_PROBE_ONLY is set */
876 if (pci_has_flag(PCI_PROBE_ONLY))
879 /* Job is a bit different between memory and IO */
880 if (res->flags & IORESOURCE_MEM) {
881 pcibios_resource_to_bus(dev->bus, ®ion, res);
883 /* If the BAR is non-0 then it's probably been initialized */
884 if (region.start != 0)
887 /* The BAR is 0, let's check if memory decoding is enabled on
888 * the bridge. If not, we consider it unassigned
890 pci_read_config_word(dev, PCI_COMMAND, &command);
891 if ((command & PCI_COMMAND_MEMORY) == 0)
894 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
895 * resources covers that starting address (0 then it's good enough for
896 * us for memory space)
898 for (i = 0; i < 3; i++) {
899 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
900 hose->mem_resources[i].start == hose->mem_offset[i])
904 /* Well, it starts at 0 and we know it will collide so we may as
905 * well consider it as unassigned. That covers the Apple case.
909 /* If the BAR is non-0, then we consider it assigned */
910 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
911 if (((res->start - offset) & 0xfffffffful) != 0)
914 /* Here, we are a bit different than memory as typically IO space
915 * starting at low addresses -is- valid. What we do instead if that
916 * we consider as unassigned anything that doesn't have IO enabled
917 * in the PCI command register, and that's it.
919 pci_read_config_word(dev, PCI_COMMAND, &command);
920 if (command & PCI_COMMAND_IO)
923 /* It's starting at 0 and IO is disabled in the bridge, consider
930 /* Fixup resources of a PCI<->PCI bridge */
931 static void pcibios_fixup_bridge(struct pci_bus *bus)
933 struct resource *res;
936 struct pci_dev *dev = bus->self;
938 pci_bus_for_each_resource(bus, res, i) {
939 if (!res || !res->flags)
941 if (i >= 3 && bus->self->transparent)
944 /* If we're going to reassign everything, we can
945 * shrink the P2P resource to have size as being
946 * of 0 in order to save space.
948 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
949 res->flags |= IORESOURCE_UNSET;
955 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
957 /* Try to detect uninitialized P2P bridge resources,
958 * and clear them out so they get re-assigned later
960 if (pcibios_uninitialized_bridge_resource(bus, res)) {
962 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
967 void pcibios_setup_bus_self(struct pci_bus *bus)
969 struct pci_controller *phb;
971 /* Fix up the bus resources for P2P bridges */
972 if (bus->self != NULL)
973 pcibios_fixup_bridge(bus);
975 /* Platform specific bus fixups. This is currently only used
976 * by fsl_pci and I'm hoping to get rid of it at some point
978 if (ppc_md.pcibios_fixup_bus)
979 ppc_md.pcibios_fixup_bus(bus);
981 /* Setup bus DMA mappings */
982 phb = pci_bus_to_host(bus);
983 if (phb->controller_ops.dma_bus_setup)
984 phb->controller_ops.dma_bus_setup(bus);
987 static void pcibios_setup_device(struct pci_dev *dev)
989 struct pci_controller *phb;
990 /* Fixup NUMA node as it may not be setup yet by the generic
991 * code and is needed by the DMA init
993 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
995 /* Hook up default DMA ops */
996 set_dma_ops(&dev->dev, pci_dma_ops);
997 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
999 /* Additional platform DMA/iommu setup */
1000 phb = pci_bus_to_host(dev->bus);
1001 if (phb->controller_ops.dma_dev_setup)
1002 phb->controller_ops.dma_dev_setup(dev);
1004 /* Read default IRQs and fixup if necessary */
1005 pci_read_irq_line(dev);
1006 if (ppc_md.pci_irq_fixup)
1007 ppc_md.pci_irq_fixup(dev);
1010 int pcibios_add_device(struct pci_dev *dev)
1013 * We can only call pcibios_setup_device() after bus setup is complete,
1014 * since some of the platform specific DMA setup code depends on it.
1016 if (dev->bus->is_added)
1017 pcibios_setup_device(dev);
1019 #ifdef CONFIG_PCI_IOV
1020 if (ppc_md.pcibios_fixup_sriov)
1021 ppc_md.pcibios_fixup_sriov(dev);
1022 #endif /* CONFIG_PCI_IOV */
1027 void pcibios_setup_bus_devices(struct pci_bus *bus)
1029 struct pci_dev *dev;
1031 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1032 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1034 list_for_each_entry(dev, &bus->devices, bus_list) {
1035 /* Cardbus can call us to add new devices to a bus, so ignore
1036 * those who are already fully discovered
1041 pcibios_setup_device(dev);
1045 void pcibios_set_master(struct pci_dev *dev)
1047 /* No special bus mastering setup handling */
1050 void pcibios_fixup_bus(struct pci_bus *bus)
1052 /* When called from the generic PCI probe, read PCI<->PCI bridge
1053 * bases. This is -not- called when generating the PCI tree from
1054 * the OF device-tree.
1056 pci_read_bridge_bases(bus);
1058 /* Now fixup the bus bus */
1059 pcibios_setup_bus_self(bus);
1061 /* Now fixup devices on that bus */
1062 pcibios_setup_bus_devices(bus);
1064 EXPORT_SYMBOL(pcibios_fixup_bus);
1066 void pci_fixup_cardbus(struct pci_bus *bus)
1068 /* Now fixup devices on that bus */
1069 pcibios_setup_bus_devices(bus);
1073 static int skip_isa_ioresource_align(struct pci_dev *dev)
1075 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1076 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1082 * We need to avoid collisions with `mirrored' VGA ports
1083 * and other strange ISA hardware, so we always want the
1084 * addresses to be allocated in the 0x000-0x0ff region
1087 * Why? Because some silly external IO cards only decode
1088 * the low 10 bits of the IO address. The 0x00-0xff region
1089 * is reserved for motherboard devices that decode all 16
1090 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1091 * but we want to try to avoid allocating at 0x2900-0x2bff
1092 * which might have be mirrored at 0x0100-0x03ff..
1094 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1095 resource_size_t size, resource_size_t align)
1097 struct pci_dev *dev = data;
1098 resource_size_t start = res->start;
1100 if (res->flags & IORESOURCE_IO) {
1101 if (skip_isa_ioresource_align(dev))
1104 start = (start + 0x3ff) & ~0x3ff;
1109 EXPORT_SYMBOL(pcibios_align_resource);
1112 * Reparent resource children of pr that conflict with res
1113 * under res, and make res replace those children.
1115 static int reparent_resources(struct resource *parent,
1116 struct resource *res)
1118 struct resource *p, **pp;
1119 struct resource **firstpp = NULL;
1121 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1122 if (p->end < res->start)
1124 if (res->end < p->start)
1126 if (p->start < res->start || p->end > res->end)
1127 return -1; /* not completely contained */
1128 if (firstpp == NULL)
1131 if (firstpp == NULL)
1132 return -1; /* didn't find any conflicting entries? */
1133 res->parent = parent;
1134 res->child = *firstpp;
1138 for (p = res->child; p != NULL; p = p->sibling) {
1140 pr_debug("PCI: Reparented %s %pR under %s\n",
1141 p->name, p, res->name);
1147 * Handle resources of PCI devices. If the world were perfect, we could
1148 * just allocate all the resource regions and do nothing more. It isn't.
1149 * On the other hand, we cannot just re-allocate all devices, as it would
1150 * require us to know lots of host bridge internals. So we attempt to
1151 * keep as much of the original configuration as possible, but tweak it
1152 * when it's found to be wrong.
1154 * Known BIOS problems we have to work around:
1155 * - I/O or memory regions not configured
1156 * - regions configured, but not enabled in the command register
1157 * - bogus I/O addresses above 64K used
1158 * - expansion ROMs left enabled (this may sound harmless, but given
1159 * the fact the PCI specs explicitly allow address decoders to be
1160 * shared between expansion ROMs and other resource regions, it's
1161 * at least dangerous)
1164 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1165 * This gives us fixed barriers on where we can allocate.
1166 * (2) Allocate resources for all enabled devices. If there is
1167 * a collision, just mark the resource as unallocated. Also
1168 * disable expansion ROMs during this step.
1169 * (3) Try to allocate resources for disabled devices. If the
1170 * resources were assigned correctly, everything goes well,
1171 * if they weren't, they won't disturb allocation of other
1173 * (4) Assign new addresses to resources which were either
1174 * not configured at all or misconfigured. If explicitly
1175 * requested by the user, configure expansion ROM address
1179 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1183 struct resource *res, *pr;
1185 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1186 pci_domain_nr(bus), bus->number);
1188 pci_bus_for_each_resource(bus, res, i) {
1189 if (!res || !res->flags || res->start > res->end || res->parent)
1192 /* If the resource was left unset at this point, we clear it */
1193 if (res->flags & IORESOURCE_UNSET)
1194 goto clear_resource;
1196 if (bus->parent == NULL)
1197 pr = (res->flags & IORESOURCE_IO) ?
1198 &ioport_resource : &iomem_resource;
1200 pr = pci_find_parent_resource(bus->self, res);
1202 /* this happens when the generic PCI
1203 * code (wrongly) decides that this
1204 * bridge is transparent -- paulus
1210 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1211 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1212 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1214 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1215 struct pci_dev *dev = bus->self;
1217 if (request_resource(pr, res) == 0)
1220 * Must be a conflict with an existing entry.
1221 * Move that entry (or entries) under the
1222 * bridge resource and try again.
1224 if (reparent_resources(pr, res) == 0)
1227 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1228 pci_claim_bridge_resource(dev,
1229 i + PCI_BRIDGE_RESOURCES) == 0)
1232 pr_warning("PCI: Cannot allocate resource region "
1233 "%d of PCI bridge %d, will remap\n", i, bus->number);
1235 /* The resource might be figured out when doing
1236 * reassignment based on the resources required
1237 * by the downstream PCI devices. Here we set
1238 * the size of the resource to be 0 in order to
1246 list_for_each_entry(b, &bus->children, node)
1247 pcibios_allocate_bus_resources(b);
1250 static inline void alloc_resource(struct pci_dev *dev, int idx)
1252 struct resource *pr, *r = &dev->resource[idx];
1254 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1255 pci_name(dev), idx, r);
1257 pr = pci_find_parent_resource(dev, r);
1258 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1259 request_resource(pr, r) < 0) {
1260 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1261 " of device %s, will remap\n", idx, pci_name(dev));
1263 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1264 /* We'll assign a new address later */
1265 r->flags |= IORESOURCE_UNSET;
1271 static void __init pcibios_allocate_resources(int pass)
1273 struct pci_dev *dev = NULL;
1278 for_each_pci_dev(dev) {
1279 pci_read_config_word(dev, PCI_COMMAND, &command);
1280 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1281 r = &dev->resource[idx];
1282 if (r->parent) /* Already allocated */
1284 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1285 continue; /* Not assigned at all */
1286 /* We only allocate ROMs on pass 1 just in case they
1287 * have been screwed up by firmware
1289 if (idx == PCI_ROM_RESOURCE )
1291 if (r->flags & IORESOURCE_IO)
1292 disabled = !(command & PCI_COMMAND_IO);
1294 disabled = !(command & PCI_COMMAND_MEMORY);
1295 if (pass == disabled)
1296 alloc_resource(dev, idx);
1300 r = &dev->resource[PCI_ROM_RESOURCE];
1302 /* Turn the ROM off, leave the resource region,
1303 * but keep it unregistered.
1306 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1307 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1308 pr_debug("PCI: Switching off ROM of %s\n",
1310 r->flags &= ~IORESOURCE_ROM_ENABLE;
1311 pci_write_config_dword(dev, dev->rom_base_reg,
1312 reg & ~PCI_ROM_ADDRESS_ENABLE);
1318 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1320 struct pci_controller *hose = pci_bus_to_host(bus);
1321 resource_size_t offset;
1322 struct resource *res, *pres;
1325 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1328 if (!(hose->io_resource.flags & IORESOURCE_IO))
1330 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1331 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1332 BUG_ON(res == NULL);
1333 res->name = "Legacy IO";
1334 res->flags = IORESOURCE_IO;
1335 res->start = offset;
1336 res->end = (offset + 0xfff) & 0xfffffffful;
1337 pr_debug("Candidate legacy IO: %pR\n", res);
1338 if (request_resource(&hose->io_resource, res)) {
1340 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1341 pci_domain_nr(bus), bus->number, res);
1346 /* Check for memory */
1347 for (i = 0; i < 3; i++) {
1348 pres = &hose->mem_resources[i];
1349 offset = hose->mem_offset[i];
1350 if (!(pres->flags & IORESOURCE_MEM))
1352 pr_debug("hose mem res: %pR\n", pres);
1353 if ((pres->start - offset) <= 0xa0000 &&
1354 (pres->end - offset) >= 0xbffff)
1359 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1360 BUG_ON(res == NULL);
1361 res->name = "Legacy VGA memory";
1362 res->flags = IORESOURCE_MEM;
1363 res->start = 0xa0000 + offset;
1364 res->end = 0xbffff + offset;
1365 pr_debug("Candidate VGA memory: %pR\n", res);
1366 if (request_resource(pres, res)) {
1368 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1369 pci_domain_nr(bus), bus->number, res);
1374 void __init pcibios_resource_survey(void)
1378 /* Allocate and assign resources */
1379 list_for_each_entry(b, &pci_root_buses, node)
1380 pcibios_allocate_bus_resources(b);
1381 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1382 pcibios_allocate_resources(0);
1383 pcibios_allocate_resources(1);
1386 /* Before we start assigning unassigned resource, we try to reserve
1387 * the low IO area and the VGA memory area if they intersect the
1388 * bus available resources to avoid allocating things on top of them
1390 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1391 list_for_each_entry(b, &pci_root_buses, node)
1392 pcibios_reserve_legacy_regions(b);
1395 /* Now, if the platform didn't decide to blindly trust the firmware,
1396 * we proceed to assigning things that were left unassigned
1398 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1399 pr_debug("PCI: Assigning unassigned resources...\n");
1400 pci_assign_unassigned_resources();
1403 /* Call machine dependent fixup */
1404 if (ppc_md.pcibios_fixup)
1405 ppc_md.pcibios_fixup();
1408 /* This is used by the PCI hotplug driver to allocate resource
1409 * of newly plugged busses. We can try to consolidate with the
1410 * rest of the code later, for now, keep it as-is as our main
1411 * resource allocation function doesn't deal with sub-trees yet.
1413 void pcibios_claim_one_bus(struct pci_bus *bus)
1415 struct pci_dev *dev;
1416 struct pci_bus *child_bus;
1418 list_for_each_entry(dev, &bus->devices, bus_list) {
1421 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1422 struct resource *r = &dev->resource[i];
1424 if (r->parent || !r->start || !r->flags)
1427 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1428 pci_name(dev), i, r);
1430 if (pci_claim_resource(dev, i) == 0)
1433 pci_claim_bridge_resource(dev, i);
1437 list_for_each_entry(child_bus, &bus->children, node)
1438 pcibios_claim_one_bus(child_bus);
1440 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1443 /* pcibios_finish_adding_to_bus
1445 * This is to be called by the hotplug code after devices have been
1446 * added to a bus, this include calling it for a PHB that is just
1449 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1451 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1452 pci_domain_nr(bus), bus->number);
1454 /* Allocate bus and devices resources */
1455 pcibios_allocate_bus_resources(bus);
1456 pcibios_claim_one_bus(bus);
1457 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1459 pci_assign_unassigned_bridge_resources(bus->self);
1461 pci_assign_unassigned_bus_resources(bus);
1465 eeh_add_device_tree_late(bus);
1467 /* Add new devices to global lists. Register in proc, sysfs. */
1468 pci_bus_add_devices(bus);
1470 /* sysfs files should only be added after devices are added */
1471 eeh_add_sysfs_files(bus);
1473 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1475 int pcibios_enable_device(struct pci_dev *dev, int mask)
1477 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1479 if (phb->controller_ops.enable_device_hook)
1480 if (!phb->controller_ops.enable_device_hook(dev))
1483 return pci_enable_resources(dev, mask);
1486 void pcibios_disable_device(struct pci_dev *dev)
1488 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1490 if (phb->controller_ops.disable_device)
1491 phb->controller_ops.disable_device(dev);
1494 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1496 return (unsigned long) hose->io_base_virt - _IO_BASE;
1499 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1500 struct list_head *resources)
1502 struct resource *res;
1503 resource_size_t offset;
1506 /* Hookup PHB IO resource */
1507 res = &hose->io_resource;
1510 pr_debug("PCI: I/O resource not set for host"
1511 " bridge %s (domain %d)\n",
1512 hose->dn->full_name, hose->global_number);
1514 offset = pcibios_io_space_offset(hose);
1516 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1517 res, (unsigned long long)offset);
1518 pci_add_resource_offset(resources, res, offset);
1521 /* Hookup PHB Memory resources */
1522 for (i = 0; i < 3; ++i) {
1523 res = &hose->mem_resources[i];
1526 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1527 "host bridge %s (domain %d)\n",
1528 hose->dn->full_name, hose->global_number);
1531 offset = hose->mem_offset[i];
1534 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1535 res, (unsigned long long)offset);
1537 pci_add_resource_offset(resources, res, offset);
1542 * Null PCI config access functions, for the case when we can't
1545 #define NULL_PCI_OP(rw, size, type) \
1547 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1549 return PCIBIOS_DEVICE_NOT_FOUND; \
1553 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1556 return PCIBIOS_DEVICE_NOT_FOUND;
1560 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1563 return PCIBIOS_DEVICE_NOT_FOUND;
1566 static struct pci_ops null_pci_ops =
1568 .read = null_read_config,
1569 .write = null_write_config,
1573 * These functions are used early on before PCI scanning is done
1574 * and all of the pci_dev and pci_bus structures have been created.
1576 static struct pci_bus *
1577 fake_pci_bus(struct pci_controller *hose, int busnr)
1579 static struct pci_bus bus;
1582 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1586 bus.ops = hose? hose->ops: &null_pci_ops;
1590 #define EARLY_PCI_OP(rw, size, type) \
1591 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1592 int devfn, int offset, type value) \
1594 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1595 devfn, offset, value); \
1598 EARLY_PCI_OP(read, byte, u8 *)
1599 EARLY_PCI_OP(read, word, u16 *)
1600 EARLY_PCI_OP(read, dword, u32 *)
1601 EARLY_PCI_OP(write, byte, u8)
1602 EARLY_PCI_OP(write, word, u16)
1603 EARLY_PCI_OP(write, dword, u32)
1605 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1608 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1611 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1613 struct pci_controller *hose = bus->sysdata;
1615 return of_node_get(hose->dn);
1619 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1620 * @hose: Pointer to the PCI host controller instance structure
1622 void pcibios_scan_phb(struct pci_controller *hose)
1624 LIST_HEAD(resources);
1625 struct pci_bus *bus;
1626 struct device_node *node = hose->dn;
1629 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1631 /* Get some IO space for the new PHB */
1632 pcibios_setup_phb_io_space(hose);
1634 /* Wire up PHB bus resources */
1635 pcibios_setup_phb_resources(hose, &resources);
1637 hose->busn.start = hose->first_busno;
1638 hose->busn.end = hose->last_busno;
1639 hose->busn.flags = IORESOURCE_BUS;
1640 pci_add_resource(&resources, &hose->busn);
1642 /* Create an empty bus for the toplevel */
1643 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1644 hose->ops, hose, &resources);
1646 pr_err("Failed to create bus for PCI domain %04x\n",
1647 hose->global_number);
1648 pci_free_resource_list(&resources);
1653 /* Get probe mode and perform scan */
1654 mode = PCI_PROBE_NORMAL;
1655 if (node && hose->controller_ops.probe_mode)
1656 mode = hose->controller_ops.probe_mode(bus);
1657 pr_debug(" probe mode: %d\n", mode);
1658 if (mode == PCI_PROBE_DEVTREE)
1659 of_scan_bus(node, bus);
1661 if (mode == PCI_PROBE_NORMAL) {
1662 pci_bus_update_busn_res_end(bus, 255);
1663 hose->last_busno = pci_scan_child_bus(bus);
1664 pci_bus_update_busn_res_end(bus, hose->last_busno);
1667 /* Platform gets a chance to do some global fixups before
1668 * we proceed to resource allocation
1670 if (ppc_md.pcibios_fixup_phb)
1671 ppc_md.pcibios_fixup_phb(hose);
1673 /* Configure PCI Express settings */
1674 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1675 struct pci_bus *child;
1676 list_for_each_entry(child, &bus->children, node)
1677 pcie_bus_configure_settings(child);
1680 EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1682 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1684 int i, class = dev->class >> 8;
1685 /* When configured as agent, programing interface = 1 */
1686 int prog_if = dev->class & 0xf;
1688 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1689 class == PCI_CLASS_BRIDGE_OTHER) &&
1690 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1692 (dev->bus->parent == NULL)) {
1693 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1694 dev->resource[i].start = 0;
1695 dev->resource[i].end = 0;
1696 dev->resource[i].flags = 0;
1700 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1701 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1703 static void fixup_vga(struct pci_dev *pdev)
1707 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1708 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device())
1709 vga_set_default_device(pdev);
1712 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1713 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga);