2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/shmem_fs.h>
29 #include <linux/list.h>
30 #include <linux/syscalls.h>
31 #include <linux/irq.h>
32 #include <linux/vmalloc.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
36 #include <asm/processor.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/byteorder.h>
41 #include <asm/machdep.h>
42 #include <asm/ppc-pci.h>
45 #include "../../../drivers/pci/pci.h"
47 /* hose_spinlock protects accesses to the the phb_bitmap. */
48 static DEFINE_SPINLOCK(hose_spinlock);
51 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
52 #define MAX_PHBS 0x10000
55 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
56 * Accesses to this bitmap should be protected by hose_spinlock.
58 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
60 /* ISA Memory physical address */
61 resource_size_t isa_mem_base;
62 EXPORT_SYMBOL(isa_mem_base);
65 static const struct dma_map_ops *pci_dma_ops;
67 void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
69 pci_dma_ops = dma_ops;
73 * This function should run under locking protection, specifically
76 static int get_phb_number(struct device_node *dn)
83 * Try fixed PHB numbering first, by checking archs and reading
84 * the respective device-tree properties. Firstly, try powernv by
85 * reading "ibm,opal-phbid", only present in OPAL environment.
87 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
89 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
94 phb_id = (int)(prop & (MAX_PHBS - 1));
96 /* We need to be sure to not use the same PHB number twice. */
97 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
101 * If not pseries nor powernv, or if fixed PHB numbering tried to add
102 * the same PHB number twice, then fallback to dynamic PHB numbering.
104 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
105 BUG_ON(phb_id >= MAX_PHBS);
106 set_bit(phb_id, phb_bitmap);
111 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
113 struct pci_controller *phb;
115 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
118 spin_lock(&hose_spinlock);
119 phb->global_number = get_phb_number(dev);
120 list_add_tail(&phb->list_node, &hose_list);
121 spin_unlock(&hose_spinlock);
123 phb->is_dynamic = slab_is_available();
126 int nid = of_node_to_nid(dev);
128 if (nid < 0 || !node_online(nid))
131 PHB_SET_NODE(phb, nid);
136 EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
138 void pcibios_free_controller(struct pci_controller *phb)
140 spin_lock(&hose_spinlock);
142 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
143 if (phb->global_number < MAX_PHBS)
144 clear_bit(phb->global_number, phb_bitmap);
146 list_del(&phb->list_node);
147 spin_unlock(&hose_spinlock);
152 EXPORT_SYMBOL_GPL(pcibios_free_controller);
155 * This function is used to call pcibios_free_controller()
156 * in a deferred manner: a callback from the PCI subsystem.
158 * _*DO NOT*_ call pcibios_free_controller() explicitly if
159 * this is used (or it may access an invalid *phb pointer).
161 * The callback occurs when all references to the root bus
162 * are dropped (e.g., child buses/devices and their users).
164 * It's called as .release_fn() of 'struct pci_host_bridge'
165 * which is associated with the 'struct pci_controller.bus'
166 * (root bus) - it expects .release_data to hold a pointer
167 * to 'struct pci_controller'.
169 * In order to use it, register .release_fn()/release_data
172 * pci_set_host_bridge_release(bridge,
173 * pcibios_free_controller_deferred
176 * e.g. in the pcibios_root_bridge_prepare() callback from
177 * pci_create_root_bus().
179 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
181 struct pci_controller *phb = (struct pci_controller *)
182 bridge->release_data;
184 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
186 pcibios_free_controller(phb);
188 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
191 * The function is used to return the minimal alignment
192 * for memory or I/O windows of the associated P2P bridge.
193 * By default, 4KiB alignment for I/O windows and 1MiB for
196 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
199 struct pci_controller *phb = pci_bus_to_host(bus);
201 if (phb->controller_ops.window_alignment)
202 return phb->controller_ops.window_alignment(bus, type);
205 * PCI core will figure out the default
206 * alignment: 4KiB for I/O and 1MiB for
212 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
214 struct pci_controller *hose = pci_bus_to_host(bus);
216 if (hose->controller_ops.setup_bridge)
217 hose->controller_ops.setup_bridge(bus, type);
220 void pcibios_reset_secondary_bus(struct pci_dev *dev)
222 struct pci_controller *phb = pci_bus_to_host(dev->bus);
224 if (phb->controller_ops.reset_secondary_bus) {
225 phb->controller_ops.reset_secondary_bus(dev);
229 pci_reset_secondary_bus(dev);
232 resource_size_t pcibios_default_alignment(void)
234 if (ppc_md.pcibios_default_alignment)
235 return ppc_md.pcibios_default_alignment();
240 #ifdef CONFIG_PCI_IOV
241 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
243 if (ppc_md.pcibios_iov_resource_alignment)
244 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
246 return pci_iov_resource_size(pdev, resno);
249 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
251 if (ppc_md.pcibios_sriov_enable)
252 return ppc_md.pcibios_sriov_enable(pdev, num_vfs);
257 int pcibios_sriov_disable(struct pci_dev *pdev)
259 if (ppc_md.pcibios_sriov_disable)
260 return ppc_md.pcibios_sriov_disable(pdev);
265 #endif /* CONFIG_PCI_IOV */
267 void pcibios_bus_add_device(struct pci_dev *pdev)
269 if (ppc_md.pcibios_bus_add_device)
270 ppc_md.pcibios_bus_add_device(pdev);
273 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
276 return hose->pci_io_size;
278 return resource_size(&hose->io_resource);
282 int pcibios_vaddr_is_ioport(void __iomem *address)
285 struct pci_controller *hose;
286 resource_size_t size;
288 spin_lock(&hose_spinlock);
289 list_for_each_entry(hose, &hose_list, list_node) {
290 size = pcibios_io_size(hose);
291 if (address >= hose->io_base_virt &&
292 address < (hose->io_base_virt + size)) {
297 spin_unlock(&hose_spinlock);
301 unsigned long pci_address_to_pio(phys_addr_t address)
303 struct pci_controller *hose;
304 resource_size_t size;
305 unsigned long ret = ~0;
307 spin_lock(&hose_spinlock);
308 list_for_each_entry(hose, &hose_list, list_node) {
309 size = pcibios_io_size(hose);
310 if (address >= hose->io_base_phys &&
311 address < (hose->io_base_phys + size)) {
313 (unsigned long)hose->io_base_virt - _IO_BASE;
314 ret = base + (address - hose->io_base_phys);
318 spin_unlock(&hose_spinlock);
322 EXPORT_SYMBOL_GPL(pci_address_to_pio);
325 * Return the domain number for this bus.
327 int pci_domain_nr(struct pci_bus *bus)
329 struct pci_controller *hose = pci_bus_to_host(bus);
331 return hose->global_number;
333 EXPORT_SYMBOL(pci_domain_nr);
335 /* This routine is meant to be used early during boot, when the
336 * PCI bus numbers have not yet been assigned, and you need to
337 * issue PCI config cycles to an OF device.
338 * It could also be used to "fix" RTAS config cycles if you want
339 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
342 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
345 struct pci_controller *hose, *tmp;
346 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
347 if (hose->dn == node)
355 * Reads the interrupt pin to determine if interrupt is use by card.
356 * If the interrupt is used, then gets the interrupt line from the
357 * openfirmware and sets it in the pci_dev and pci_config line.
359 static int pci_read_irq_line(struct pci_dev *pci_dev)
363 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
365 /* Try to get a mapping from the device-tree */
366 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0);
370 /* If that fails, lets fallback to what is in the config
371 * space and map that through the default controller. We
372 * also set the type to level low since that's what PCI
373 * interrupts are. If your platform does differently, then
374 * either provide a proper interrupt tree or don't use this
377 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
381 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
382 line == 0xff || line == 0) {
385 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
388 virq = irq_create_mapping(NULL, line);
390 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
394 pr_debug(" Failed to map !\n");
398 pr_debug(" Mapped to linux irq %d\n", virq);
406 * Platform support for /proc/bus/pci/X/Y mmap()s.
409 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
411 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
412 resource_size_t ioaddr = pci_resource_start(pdev, bar);
417 /* Convert to an offset within this PCI controller */
418 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
420 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
425 * This one is used by /dev/mem and fbdev who have no clue about the
426 * PCI device, it tries to find the PCI device first and calls the
429 pgprot_t pci_phys_mem_access_prot(struct file *file,
434 struct pci_dev *pdev = NULL;
435 struct resource *found = NULL;
436 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
439 if (page_is_ram(pfn))
442 prot = pgprot_noncached(prot);
443 for_each_pci_dev(pdev) {
444 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
445 struct resource *rp = &pdev->resource[i];
446 int flags = rp->flags;
448 /* Active and same type? */
449 if ((flags & IORESOURCE_MEM) == 0)
451 /* In the range of this resource? */
452 if (offset < (rp->start & PAGE_MASK) ||
462 if (found->flags & IORESOURCE_PREFETCH)
463 prot = pgprot_noncached_wc(prot);
467 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
468 (unsigned long long)offset, pgprot_val(prot));
473 /* This provides legacy IO read access on a bus */
474 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
476 unsigned long offset;
477 struct pci_controller *hose = pci_bus_to_host(bus);
478 struct resource *rp = &hose->io_resource;
481 /* Check if port can be supported by that bus. We only check
482 * the ranges of the PHB though, not the bus itself as the rules
483 * for forwarding legacy cycles down bridges are not our problem
484 * here. So if the host bridge supports it, we do it.
486 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
489 if (!(rp->flags & IORESOURCE_IO))
491 if (offset < rp->start || (offset + size) > rp->end)
493 addr = hose->io_base_virt + port;
497 *((u8 *)val) = in_8(addr);
502 *((u16 *)val) = in_le16(addr);
507 *((u32 *)val) = in_le32(addr);
513 /* This provides legacy IO write access on a bus */
514 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
516 unsigned long offset;
517 struct pci_controller *hose = pci_bus_to_host(bus);
518 struct resource *rp = &hose->io_resource;
521 /* Check if port can be supported by that bus. We only check
522 * the ranges of the PHB though, not the bus itself as the rules
523 * for forwarding legacy cycles down bridges are not our problem
524 * here. So if the host bridge supports it, we do it.
526 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
529 if (!(rp->flags & IORESOURCE_IO))
531 if (offset < rp->start || (offset + size) > rp->end)
533 addr = hose->io_base_virt + port;
535 /* WARNING: The generic code is idiotic. It gets passed a pointer
536 * to what can be a 1, 2 or 4 byte quantity and always reads that
537 * as a u32, which means that we have to correct the location of
538 * the data read within those 32 bits for size 1 and 2
542 out_8(addr, val >> 24);
547 out_le16(addr, val >> 16);
558 /* This provides legacy IO or memory mmap access on a bus */
559 int pci_mmap_legacy_page_range(struct pci_bus *bus,
560 struct vm_area_struct *vma,
561 enum pci_mmap_state mmap_state)
563 struct pci_controller *hose = pci_bus_to_host(bus);
564 resource_size_t offset =
565 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
566 resource_size_t size = vma->vm_end - vma->vm_start;
569 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
570 pci_domain_nr(bus), bus->number,
571 mmap_state == pci_mmap_mem ? "MEM" : "IO",
572 (unsigned long long)offset,
573 (unsigned long long)(offset + size - 1));
575 if (mmap_state == pci_mmap_mem) {
578 * Because X is lame and can fail starting if it gets an error trying
579 * to mmap legacy_mem (instead of just moving on without legacy memory
580 * access) we fake it here by giving it anonymous memory, effectively
581 * behaving just like /dev/zero
583 if ((offset + size) > hose->isa_mem_size) {
585 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
586 current->comm, current->pid, pci_domain_nr(bus), bus->number);
587 if (vma->vm_flags & VM_SHARED)
588 return shmem_zero_setup(vma);
591 offset += hose->isa_mem_phys;
593 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
594 unsigned long roffset = offset + io_offset;
595 rp = &hose->io_resource;
596 if (!(rp->flags & IORESOURCE_IO))
598 if (roffset < rp->start || (roffset + size) > rp->end)
600 offset += hose->io_base_phys;
602 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
604 vma->vm_pgoff = offset >> PAGE_SHIFT;
605 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
606 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
607 vma->vm_end - vma->vm_start,
611 void pci_resource_to_user(const struct pci_dev *dev, int bar,
612 const struct resource *rsrc,
613 resource_size_t *start, resource_size_t *end)
615 struct pci_bus_region region;
617 if (rsrc->flags & IORESOURCE_IO) {
618 pcibios_resource_to_bus(dev->bus, ®ion,
619 (struct resource *) rsrc);
620 *start = region.start;
625 /* We pass a CPU physical address to userland for MMIO instead of a
626 * BAR value because X is lame and expects to be able to use that
627 * to pass to /dev/mem!
629 * That means we may have 64-bit values where some apps only expect
630 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
632 *start = rsrc->start;
637 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
638 * @hose: newly allocated pci_controller to be setup
639 * @dev: device node of the host bridge
640 * @primary: set if primary bus (32 bits only, soon to be deprecated)
642 * This function will parse the "ranges" property of a PCI host bridge device
643 * node and setup the resource mapping of a pci controller based on its
646 * Life would be boring if it wasn't for a few issues that we have to deal
649 * - We can only cope with one IO space range and up to 3 Memory space
650 * ranges. However, some machines (thanks Apple !) tend to split their
651 * space into lots of small contiguous ranges. So we have to coalesce.
653 * - Some busses have IO space not starting at 0, which causes trouble with
654 * the way we do our IO resource renumbering. The code somewhat deals with
655 * it for 64 bits but I would expect problems on 32 bits.
657 * - Some 32 bits platforms such as 4xx can have physical space larger than
658 * 32 bits so we need to use 64 bits values for the parsing
660 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
661 struct device_node *dev, int primary)
664 struct resource *res;
665 struct of_pci_range range;
666 struct of_pci_range_parser parser;
668 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
669 dev, primary ? "(primary)" : "");
671 /* Check for ranges property */
672 if (of_pci_range_parser_init(&parser, dev))
676 for_each_of_pci_range(&parser, &range) {
677 /* If we failed translation or got a zero-sized region
678 * (some FW try to feed us with non sensical zero sized regions
679 * such as power3 which look like some kind of attempt at exposing
680 * the VGA memory hole)
682 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
685 /* Act based on address space type */
687 switch (range.flags & IORESOURCE_TYPE_BITS) {
690 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
691 range.cpu_addr, range.cpu_addr + range.size - 1,
694 /* We support only one IO range */
695 if (hose->pci_io_size) {
697 " \\--> Skipped (too many) !\n");
701 /* On 32 bits, limit I/O space to 16MB */
702 if (range.size > 0x01000000)
703 range.size = 0x01000000;
705 /* 32 bits needs to map IOs here */
706 hose->io_base_virt = ioremap(range.cpu_addr,
709 /* Expect trouble if pci_addr is not 0 */
712 (unsigned long)hose->io_base_virt;
713 #endif /* CONFIG_PPC32 */
714 /* pci_io_size and io_base_phys always represent IO
715 * space starting at 0 so we factor in pci_addr
717 hose->pci_io_size = range.pci_addr + range.size;
718 hose->io_base_phys = range.cpu_addr - range.pci_addr;
721 res = &hose->io_resource;
722 range.cpu_addr = range.pci_addr;
726 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
727 range.cpu_addr, range.cpu_addr + range.size - 1,
729 (range.pci_space & 0x40000000) ?
732 /* We support only 3 memory ranges */
735 " \\--> Skipped (too many) !\n");
738 /* Handles ISA memory hole space here */
739 if (range.pci_addr == 0) {
740 if (primary || isa_mem_base == 0)
741 isa_mem_base = range.cpu_addr;
742 hose->isa_mem_phys = range.cpu_addr;
743 hose->isa_mem_size = range.size;
747 hose->mem_offset[memno] = range.cpu_addr -
749 res = &hose->mem_resources[memno++];
753 res->name = dev->full_name;
754 res->flags = range.flags;
755 res->start = range.cpu_addr;
756 res->end = range.cpu_addr + range.size - 1;
757 res->parent = res->child = res->sibling = NULL;
762 /* Decide whether to display the domain number in /proc */
763 int pci_proc_domain(struct pci_bus *bus)
765 struct pci_controller *hose = pci_bus_to_host(bus);
767 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
769 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
770 return hose->global_number != 0;
774 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
776 if (ppc_md.pcibios_root_bridge_prepare)
777 return ppc_md.pcibios_root_bridge_prepare(bridge);
782 /* This header fixup will do the resource fixup for all devices as they are
783 * probed, but not for bridge ranges
785 static void pcibios_fixup_resources(struct pci_dev *dev)
787 struct pci_controller *hose = pci_bus_to_host(dev->bus);
791 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
799 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
800 struct resource *res = dev->resource + i;
801 struct pci_bus_region reg;
805 /* If we're going to re-assign everything, we mark all resources
806 * as unset (and 0-base them). In addition, we mark BARs starting
807 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
808 * since in that case, we don't want to re-assign anything
810 pcibios_resource_to_bus(dev->bus, ®, res);
811 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
812 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
813 /* Only print message if not re-assigning */
814 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
815 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
816 pci_name(dev), i, res);
817 res->end -= res->start;
819 res->flags |= IORESOURCE_UNSET;
823 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
826 /* Call machine specific resource fixup */
827 if (ppc_md.pcibios_fixup_resources)
828 ppc_md.pcibios_fixup_resources(dev);
830 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
832 /* This function tries to figure out if a bridge resource has been initialized
833 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
834 * things go more smoothly when it gets it right. It should covers cases such
835 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
837 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
838 struct resource *res)
840 struct pci_controller *hose = pci_bus_to_host(bus);
841 struct pci_dev *dev = bus->self;
842 resource_size_t offset;
843 struct pci_bus_region region;
847 /* We don't do anything if PCI_PROBE_ONLY is set */
848 if (pci_has_flag(PCI_PROBE_ONLY))
851 /* Job is a bit different between memory and IO */
852 if (res->flags & IORESOURCE_MEM) {
853 pcibios_resource_to_bus(dev->bus, ®ion, res);
855 /* If the BAR is non-0 then it's probably been initialized */
856 if (region.start != 0)
859 /* The BAR is 0, let's check if memory decoding is enabled on
860 * the bridge. If not, we consider it unassigned
862 pci_read_config_word(dev, PCI_COMMAND, &command);
863 if ((command & PCI_COMMAND_MEMORY) == 0)
866 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
867 * resources covers that starting address (0 then it's good enough for
868 * us for memory space)
870 for (i = 0; i < 3; i++) {
871 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
872 hose->mem_resources[i].start == hose->mem_offset[i])
876 /* Well, it starts at 0 and we know it will collide so we may as
877 * well consider it as unassigned. That covers the Apple case.
881 /* If the BAR is non-0, then we consider it assigned */
882 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
883 if (((res->start - offset) & 0xfffffffful) != 0)
886 /* Here, we are a bit different than memory as typically IO space
887 * starting at low addresses -is- valid. What we do instead if that
888 * we consider as unassigned anything that doesn't have IO enabled
889 * in the PCI command register, and that's it.
891 pci_read_config_word(dev, PCI_COMMAND, &command);
892 if (command & PCI_COMMAND_IO)
895 /* It's starting at 0 and IO is disabled in the bridge, consider
902 /* Fixup resources of a PCI<->PCI bridge */
903 static void pcibios_fixup_bridge(struct pci_bus *bus)
905 struct resource *res;
908 struct pci_dev *dev = bus->self;
910 pci_bus_for_each_resource(bus, res, i) {
911 if (!res || !res->flags)
913 if (i >= 3 && bus->self->transparent)
916 /* If we're going to reassign everything, we can
917 * shrink the P2P resource to have size as being
918 * of 0 in order to save space.
920 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
921 res->flags |= IORESOURCE_UNSET;
927 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
929 /* Try to detect uninitialized P2P bridge resources,
930 * and clear them out so they get re-assigned later
932 if (pcibios_uninitialized_bridge_resource(bus, res)) {
934 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
939 void pcibios_setup_bus_self(struct pci_bus *bus)
941 struct pci_controller *phb;
943 /* Fix up the bus resources for P2P bridges */
944 if (bus->self != NULL)
945 pcibios_fixup_bridge(bus);
947 /* Platform specific bus fixups. This is currently only used
948 * by fsl_pci and I'm hoping to get rid of it at some point
950 if (ppc_md.pcibios_fixup_bus)
951 ppc_md.pcibios_fixup_bus(bus);
953 /* Setup bus DMA mappings */
954 phb = pci_bus_to_host(bus);
955 if (phb->controller_ops.dma_bus_setup)
956 phb->controller_ops.dma_bus_setup(bus);
959 static void pcibios_setup_device(struct pci_dev *dev)
961 struct pci_controller *phb;
962 /* Fixup NUMA node as it may not be setup yet by the generic
963 * code and is needed by the DMA init
965 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
967 /* Hook up default DMA ops */
968 set_dma_ops(&dev->dev, pci_dma_ops);
969 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET;
971 /* Additional platform DMA/iommu setup */
972 phb = pci_bus_to_host(dev->bus);
973 if (phb->controller_ops.dma_dev_setup)
974 phb->controller_ops.dma_dev_setup(dev);
976 /* Read default IRQs and fixup if necessary */
977 pci_read_irq_line(dev);
978 if (ppc_md.pci_irq_fixup)
979 ppc_md.pci_irq_fixup(dev);
982 int pcibios_add_device(struct pci_dev *dev)
985 * We can only call pcibios_setup_device() after bus setup is complete,
986 * since some of the platform specific DMA setup code depends on it.
988 if (dev->bus->is_added)
989 pcibios_setup_device(dev);
991 #ifdef CONFIG_PCI_IOV
992 if (ppc_md.pcibios_fixup_sriov)
993 ppc_md.pcibios_fixup_sriov(dev);
994 #endif /* CONFIG_PCI_IOV */
999 void pcibios_setup_bus_devices(struct pci_bus *bus)
1001 struct pci_dev *dev;
1003 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1004 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1006 list_for_each_entry(dev, &bus->devices, bus_list) {
1007 /* Cardbus can call us to add new devices to a bus, so ignore
1008 * those who are already fully discovered
1010 if (pci_dev_is_added(dev))
1013 pcibios_setup_device(dev);
1017 void pcibios_set_master(struct pci_dev *dev)
1019 /* No special bus mastering setup handling */
1022 void pcibios_fixup_bus(struct pci_bus *bus)
1024 /* When called from the generic PCI probe, read PCI<->PCI bridge
1025 * bases. This is -not- called when generating the PCI tree from
1026 * the OF device-tree.
1028 pci_read_bridge_bases(bus);
1030 /* Now fixup the bus bus */
1031 pcibios_setup_bus_self(bus);
1033 /* Now fixup devices on that bus */
1034 pcibios_setup_bus_devices(bus);
1036 EXPORT_SYMBOL(pcibios_fixup_bus);
1038 void pci_fixup_cardbus(struct pci_bus *bus)
1040 /* Now fixup devices on that bus */
1041 pcibios_setup_bus_devices(bus);
1045 static int skip_isa_ioresource_align(struct pci_dev *dev)
1047 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1048 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1054 * We need to avoid collisions with `mirrored' VGA ports
1055 * and other strange ISA hardware, so we always want the
1056 * addresses to be allocated in the 0x000-0x0ff region
1059 * Why? Because some silly external IO cards only decode
1060 * the low 10 bits of the IO address. The 0x00-0xff region
1061 * is reserved for motherboard devices that decode all 16
1062 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1063 * but we want to try to avoid allocating at 0x2900-0x2bff
1064 * which might have be mirrored at 0x0100-0x03ff..
1066 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1067 resource_size_t size, resource_size_t align)
1069 struct pci_dev *dev = data;
1070 resource_size_t start = res->start;
1072 if (res->flags & IORESOURCE_IO) {
1073 if (skip_isa_ioresource_align(dev))
1076 start = (start + 0x3ff) & ~0x3ff;
1081 EXPORT_SYMBOL(pcibios_align_resource);
1084 * Reparent resource children of pr that conflict with res
1085 * under res, and make res replace those children.
1087 static int reparent_resources(struct resource *parent,
1088 struct resource *res)
1090 struct resource *p, **pp;
1091 struct resource **firstpp = NULL;
1093 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1094 if (p->end < res->start)
1096 if (res->end < p->start)
1098 if (p->start < res->start || p->end > res->end)
1099 return -1; /* not completely contained */
1100 if (firstpp == NULL)
1103 if (firstpp == NULL)
1104 return -1; /* didn't find any conflicting entries? */
1105 res->parent = parent;
1106 res->child = *firstpp;
1110 for (p = res->child; p != NULL; p = p->sibling) {
1112 pr_debug("PCI: Reparented %s %pR under %s\n",
1113 p->name, p, res->name);
1119 * Handle resources of PCI devices. If the world were perfect, we could
1120 * just allocate all the resource regions and do nothing more. It isn't.
1121 * On the other hand, we cannot just re-allocate all devices, as it would
1122 * require us to know lots of host bridge internals. So we attempt to
1123 * keep as much of the original configuration as possible, but tweak it
1124 * when it's found to be wrong.
1126 * Known BIOS problems we have to work around:
1127 * - I/O or memory regions not configured
1128 * - regions configured, but not enabled in the command register
1129 * - bogus I/O addresses above 64K used
1130 * - expansion ROMs left enabled (this may sound harmless, but given
1131 * the fact the PCI specs explicitly allow address decoders to be
1132 * shared between expansion ROMs and other resource regions, it's
1133 * at least dangerous)
1136 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1137 * This gives us fixed barriers on where we can allocate.
1138 * (2) Allocate resources for all enabled devices. If there is
1139 * a collision, just mark the resource as unallocated. Also
1140 * disable expansion ROMs during this step.
1141 * (3) Try to allocate resources for disabled devices. If the
1142 * resources were assigned correctly, everything goes well,
1143 * if they weren't, they won't disturb allocation of other
1145 * (4) Assign new addresses to resources which were either
1146 * not configured at all or misconfigured. If explicitly
1147 * requested by the user, configure expansion ROM address
1151 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1155 struct resource *res, *pr;
1157 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1158 pci_domain_nr(bus), bus->number);
1160 pci_bus_for_each_resource(bus, res, i) {
1161 if (!res || !res->flags || res->start > res->end || res->parent)
1164 /* If the resource was left unset at this point, we clear it */
1165 if (res->flags & IORESOURCE_UNSET)
1166 goto clear_resource;
1168 if (bus->parent == NULL)
1169 pr = (res->flags & IORESOURCE_IO) ?
1170 &ioport_resource : &iomem_resource;
1172 pr = pci_find_parent_resource(bus->self, res);
1174 /* this happens when the generic PCI
1175 * code (wrongly) decides that this
1176 * bridge is transparent -- paulus
1182 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1183 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1184 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1186 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1187 struct pci_dev *dev = bus->self;
1189 if (request_resource(pr, res) == 0)
1192 * Must be a conflict with an existing entry.
1193 * Move that entry (or entries) under the
1194 * bridge resource and try again.
1196 if (reparent_resources(pr, res) == 0)
1199 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1200 pci_claim_bridge_resource(dev,
1201 i + PCI_BRIDGE_RESOURCES) == 0)
1204 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n",
1207 /* The resource might be figured out when doing
1208 * reassignment based on the resources required
1209 * by the downstream PCI devices. Here we set
1210 * the size of the resource to be 0 in order to
1218 list_for_each_entry(b, &bus->children, node)
1219 pcibios_allocate_bus_resources(b);
1222 static inline void alloc_resource(struct pci_dev *dev, int idx)
1224 struct resource *pr, *r = &dev->resource[idx];
1226 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1227 pci_name(dev), idx, r);
1229 pr = pci_find_parent_resource(dev, r);
1230 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1231 request_resource(pr, r) < 0) {
1232 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1233 " of device %s, will remap\n", idx, pci_name(dev));
1235 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1236 /* We'll assign a new address later */
1237 r->flags |= IORESOURCE_UNSET;
1243 static void __init pcibios_allocate_resources(int pass)
1245 struct pci_dev *dev = NULL;
1250 for_each_pci_dev(dev) {
1251 pci_read_config_word(dev, PCI_COMMAND, &command);
1252 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1253 r = &dev->resource[idx];
1254 if (r->parent) /* Already allocated */
1256 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1257 continue; /* Not assigned at all */
1258 /* We only allocate ROMs on pass 1 just in case they
1259 * have been screwed up by firmware
1261 if (idx == PCI_ROM_RESOURCE )
1263 if (r->flags & IORESOURCE_IO)
1264 disabled = !(command & PCI_COMMAND_IO);
1266 disabled = !(command & PCI_COMMAND_MEMORY);
1267 if (pass == disabled)
1268 alloc_resource(dev, idx);
1272 r = &dev->resource[PCI_ROM_RESOURCE];
1274 /* Turn the ROM off, leave the resource region,
1275 * but keep it unregistered.
1278 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1279 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1280 pr_debug("PCI: Switching off ROM of %s\n",
1282 r->flags &= ~IORESOURCE_ROM_ENABLE;
1283 pci_write_config_dword(dev, dev->rom_base_reg,
1284 reg & ~PCI_ROM_ADDRESS_ENABLE);
1290 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1292 struct pci_controller *hose = pci_bus_to_host(bus);
1293 resource_size_t offset;
1294 struct resource *res, *pres;
1297 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1300 if (!(hose->io_resource.flags & IORESOURCE_IO))
1302 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1303 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1304 BUG_ON(res == NULL);
1305 res->name = "Legacy IO";
1306 res->flags = IORESOURCE_IO;
1307 res->start = offset;
1308 res->end = (offset + 0xfff) & 0xfffffffful;
1309 pr_debug("Candidate legacy IO: %pR\n", res);
1310 if (request_resource(&hose->io_resource, res)) {
1312 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1313 pci_domain_nr(bus), bus->number, res);
1318 /* Check for memory */
1319 for (i = 0; i < 3; i++) {
1320 pres = &hose->mem_resources[i];
1321 offset = hose->mem_offset[i];
1322 if (!(pres->flags & IORESOURCE_MEM))
1324 pr_debug("hose mem res: %pR\n", pres);
1325 if ((pres->start - offset) <= 0xa0000 &&
1326 (pres->end - offset) >= 0xbffff)
1331 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1332 BUG_ON(res == NULL);
1333 res->name = "Legacy VGA memory";
1334 res->flags = IORESOURCE_MEM;
1335 res->start = 0xa0000 + offset;
1336 res->end = 0xbffff + offset;
1337 pr_debug("Candidate VGA memory: %pR\n", res);
1338 if (request_resource(pres, res)) {
1340 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1341 pci_domain_nr(bus), bus->number, res);
1346 void __init pcibios_resource_survey(void)
1350 /* Allocate and assign resources */
1351 list_for_each_entry(b, &pci_root_buses, node)
1352 pcibios_allocate_bus_resources(b);
1353 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1354 pcibios_allocate_resources(0);
1355 pcibios_allocate_resources(1);
1358 /* Before we start assigning unassigned resource, we try to reserve
1359 * the low IO area and the VGA memory area if they intersect the
1360 * bus available resources to avoid allocating things on top of them
1362 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1363 list_for_each_entry(b, &pci_root_buses, node)
1364 pcibios_reserve_legacy_regions(b);
1367 /* Now, if the platform didn't decide to blindly trust the firmware,
1368 * we proceed to assigning things that were left unassigned
1370 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1371 pr_debug("PCI: Assigning unassigned resources...\n");
1372 pci_assign_unassigned_resources();
1375 /* Call machine dependent fixup */
1376 if (ppc_md.pcibios_fixup)
1377 ppc_md.pcibios_fixup();
1380 /* This is used by the PCI hotplug driver to allocate resource
1381 * of newly plugged busses. We can try to consolidate with the
1382 * rest of the code later, for now, keep it as-is as our main
1383 * resource allocation function doesn't deal with sub-trees yet.
1385 void pcibios_claim_one_bus(struct pci_bus *bus)
1387 struct pci_dev *dev;
1388 struct pci_bus *child_bus;
1390 list_for_each_entry(dev, &bus->devices, bus_list) {
1393 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1394 struct resource *r = &dev->resource[i];
1396 if (r->parent || !r->start || !r->flags)
1399 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1400 pci_name(dev), i, r);
1402 if (pci_claim_resource(dev, i) == 0)
1405 pci_claim_bridge_resource(dev, i);
1409 list_for_each_entry(child_bus, &bus->children, node)
1410 pcibios_claim_one_bus(child_bus);
1412 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1415 /* pcibios_finish_adding_to_bus
1417 * This is to be called by the hotplug code after devices have been
1418 * added to a bus, this include calling it for a PHB that is just
1421 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1423 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1424 pci_domain_nr(bus), bus->number);
1426 /* Allocate bus and devices resources */
1427 pcibios_allocate_bus_resources(bus);
1428 pcibios_claim_one_bus(bus);
1429 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1431 pci_assign_unassigned_bridge_resources(bus->self);
1433 pci_assign_unassigned_bus_resources(bus);
1437 eeh_add_device_tree_late(bus);
1439 /* Add new devices to global lists. Register in proc, sysfs. */
1440 pci_bus_add_devices(bus);
1442 /* sysfs files should only be added after devices are added */
1443 eeh_add_sysfs_files(bus);
1445 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1447 int pcibios_enable_device(struct pci_dev *dev, int mask)
1449 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1451 if (phb->controller_ops.enable_device_hook)
1452 if (!phb->controller_ops.enable_device_hook(dev))
1455 return pci_enable_resources(dev, mask);
1458 void pcibios_disable_device(struct pci_dev *dev)
1460 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1462 if (phb->controller_ops.disable_device)
1463 phb->controller_ops.disable_device(dev);
1466 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1468 return (unsigned long) hose->io_base_virt - _IO_BASE;
1471 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1472 struct list_head *resources)
1474 struct resource *res;
1475 resource_size_t offset;
1478 /* Hookup PHB IO resource */
1479 res = &hose->io_resource;
1482 pr_debug("PCI: I/O resource not set for host"
1483 " bridge %pOF (domain %d)\n",
1484 hose->dn, hose->global_number);
1486 offset = pcibios_io_space_offset(hose);
1488 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1489 res, (unsigned long long)offset);
1490 pci_add_resource_offset(resources, res, offset);
1493 /* Hookup PHB Memory resources */
1494 for (i = 0; i < 3; ++i) {
1495 res = &hose->mem_resources[i];
1499 offset = hose->mem_offset[i];
1500 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1501 res, (unsigned long long)offset);
1503 pci_add_resource_offset(resources, res, offset);
1508 * Null PCI config access functions, for the case when we can't
1511 #define NULL_PCI_OP(rw, size, type) \
1513 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1515 return PCIBIOS_DEVICE_NOT_FOUND; \
1519 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1522 return PCIBIOS_DEVICE_NOT_FOUND;
1526 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1529 return PCIBIOS_DEVICE_NOT_FOUND;
1532 static struct pci_ops null_pci_ops =
1534 .read = null_read_config,
1535 .write = null_write_config,
1539 * These functions are used early on before PCI scanning is done
1540 * and all of the pci_dev and pci_bus structures have been created.
1542 static struct pci_bus *
1543 fake_pci_bus(struct pci_controller *hose, int busnr)
1545 static struct pci_bus bus;
1548 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1552 bus.ops = hose? hose->ops: &null_pci_ops;
1556 #define EARLY_PCI_OP(rw, size, type) \
1557 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1558 int devfn, int offset, type value) \
1560 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1561 devfn, offset, value); \
1564 EARLY_PCI_OP(read, byte, u8 *)
1565 EARLY_PCI_OP(read, word, u16 *)
1566 EARLY_PCI_OP(read, dword, u32 *)
1567 EARLY_PCI_OP(write, byte, u8)
1568 EARLY_PCI_OP(write, word, u16)
1569 EARLY_PCI_OP(write, dword, u32)
1571 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1574 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1577 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1579 struct pci_controller *hose = bus->sysdata;
1581 return of_node_get(hose->dn);
1585 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1586 * @hose: Pointer to the PCI host controller instance structure
1588 void pcibios_scan_phb(struct pci_controller *hose)
1590 LIST_HEAD(resources);
1591 struct pci_bus *bus;
1592 struct device_node *node = hose->dn;
1595 pr_debug("PCI: Scanning PHB %pOF\n", node);
1597 /* Get some IO space for the new PHB */
1598 pcibios_setup_phb_io_space(hose);
1600 /* Wire up PHB bus resources */
1601 pcibios_setup_phb_resources(hose, &resources);
1603 hose->busn.start = hose->first_busno;
1604 hose->busn.end = hose->last_busno;
1605 hose->busn.flags = IORESOURCE_BUS;
1606 pci_add_resource(&resources, &hose->busn);
1608 /* Create an empty bus for the toplevel */
1609 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1610 hose->ops, hose, &resources);
1612 pr_err("Failed to create bus for PCI domain %04x\n",
1613 hose->global_number);
1614 pci_free_resource_list(&resources);
1619 /* Get probe mode and perform scan */
1620 mode = PCI_PROBE_NORMAL;
1621 if (node && hose->controller_ops.probe_mode)
1622 mode = hose->controller_ops.probe_mode(bus);
1623 pr_debug(" probe mode: %d\n", mode);
1624 if (mode == PCI_PROBE_DEVTREE)
1625 of_scan_bus(node, bus);
1627 if (mode == PCI_PROBE_NORMAL) {
1628 pci_bus_update_busn_res_end(bus, 255);
1629 hose->last_busno = pci_scan_child_bus(bus);
1630 pci_bus_update_busn_res_end(bus, hose->last_busno);
1633 /* Platform gets a chance to do some global fixups before
1634 * we proceed to resource allocation
1636 if (ppc_md.pcibios_fixup_phb)
1637 ppc_md.pcibios_fixup_phb(hose);
1639 /* Configure PCI Express settings */
1640 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1641 struct pci_bus *child;
1642 list_for_each_entry(child, &bus->children, node)
1643 pcie_bus_configure_settings(child);
1646 EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1648 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1650 int i, class = dev->class >> 8;
1651 /* When configured as agent, programing interface = 1 */
1652 int prog_if = dev->class & 0xf;
1654 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1655 class == PCI_CLASS_BRIDGE_OTHER) &&
1656 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1658 (dev->bus->parent == NULL)) {
1659 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1660 dev->resource[i].start = 0;
1661 dev->resource[i].end = 0;
1662 dev->resource[i].flags = 0;
1666 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1667 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);