2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/shmem_fs.h>
29 #include <linux/list.h>
30 #include <linux/syscalls.h>
31 #include <linux/irq.h>
32 #include <linux/vmalloc.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
36 #include <asm/processor.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/byteorder.h>
41 #include <asm/machdep.h>
42 #include <asm/ppc-pci.h>
45 #include "../../../drivers/pci/pci.h"
47 /* hose_spinlock protects accesses to the the phb_bitmap. */
48 static DEFINE_SPINLOCK(hose_spinlock);
51 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
52 #define MAX_PHBS 0x10000
55 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
56 * Accesses to this bitmap should be protected by hose_spinlock.
58 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
60 /* ISA Memory physical address */
61 resource_size_t isa_mem_base;
62 EXPORT_SYMBOL(isa_mem_base);
65 static const struct dma_map_ops *pci_dma_ops = &dma_nommu_ops;
67 void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
69 pci_dma_ops = dma_ops;
72 const struct dma_map_ops *get_pci_dma_ops(void)
76 EXPORT_SYMBOL(get_pci_dma_ops);
79 * This function should run under locking protection, specifically
82 static int get_phb_number(struct device_node *dn)
89 * Try fixed PHB numbering first, by checking archs and reading
90 * the respective device-tree properties. Firstly, try powernv by
91 * reading "ibm,opal-phbid", only present in OPAL environment.
93 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
95 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
100 phb_id = (int)(prop & (MAX_PHBS - 1));
102 /* We need to be sure to not use the same PHB number twice. */
103 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
107 * If not pseries nor powernv, or if fixed PHB numbering tried to add
108 * the same PHB number twice, then fallback to dynamic PHB numbering.
110 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
111 BUG_ON(phb_id >= MAX_PHBS);
112 set_bit(phb_id, phb_bitmap);
117 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
119 struct pci_controller *phb;
121 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
124 spin_lock(&hose_spinlock);
125 phb->global_number = get_phb_number(dev);
126 list_add_tail(&phb->list_node, &hose_list);
127 spin_unlock(&hose_spinlock);
129 phb->is_dynamic = slab_is_available();
132 int nid = of_node_to_nid(dev);
134 if (nid < 0 || !node_online(nid))
137 PHB_SET_NODE(phb, nid);
142 EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
144 void pcibios_free_controller(struct pci_controller *phb)
146 spin_lock(&hose_spinlock);
148 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
149 if (phb->global_number < MAX_PHBS)
150 clear_bit(phb->global_number, phb_bitmap);
152 list_del(&phb->list_node);
153 spin_unlock(&hose_spinlock);
158 EXPORT_SYMBOL_GPL(pcibios_free_controller);
161 * This function is used to call pcibios_free_controller()
162 * in a deferred manner: a callback from the PCI subsystem.
164 * _*DO NOT*_ call pcibios_free_controller() explicitly if
165 * this is used (or it may access an invalid *phb pointer).
167 * The callback occurs when all references to the root bus
168 * are dropped (e.g., child buses/devices and their users).
170 * It's called as .release_fn() of 'struct pci_host_bridge'
171 * which is associated with the 'struct pci_controller.bus'
172 * (root bus) - it expects .release_data to hold a pointer
173 * to 'struct pci_controller'.
175 * In order to use it, register .release_fn()/release_data
178 * pci_set_host_bridge_release(bridge,
179 * pcibios_free_controller_deferred
182 * e.g. in the pcibios_root_bridge_prepare() callback from
183 * pci_create_root_bus().
185 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
187 struct pci_controller *phb = (struct pci_controller *)
188 bridge->release_data;
190 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
192 pcibios_free_controller(phb);
194 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
197 * The function is used to return the minimal alignment
198 * for memory or I/O windows of the associated P2P bridge.
199 * By default, 4KiB alignment for I/O windows and 1MiB for
202 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
205 struct pci_controller *phb = pci_bus_to_host(bus);
207 if (phb->controller_ops.window_alignment)
208 return phb->controller_ops.window_alignment(bus, type);
211 * PCI core will figure out the default
212 * alignment: 4KiB for I/O and 1MiB for
218 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
220 struct pci_controller *hose = pci_bus_to_host(bus);
222 if (hose->controller_ops.setup_bridge)
223 hose->controller_ops.setup_bridge(bus, type);
226 void pcibios_reset_secondary_bus(struct pci_dev *dev)
228 struct pci_controller *phb = pci_bus_to_host(dev->bus);
230 if (phb->controller_ops.reset_secondary_bus) {
231 phb->controller_ops.reset_secondary_bus(dev);
235 pci_reset_secondary_bus(dev);
238 resource_size_t pcibios_default_alignment(void)
240 if (ppc_md.pcibios_default_alignment)
241 return ppc_md.pcibios_default_alignment();
246 #ifdef CONFIG_PCI_IOV
247 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
249 if (ppc_md.pcibios_iov_resource_alignment)
250 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
252 return pci_iov_resource_size(pdev, resno);
255 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
257 if (ppc_md.pcibios_sriov_enable)
258 return ppc_md.pcibios_sriov_enable(pdev, num_vfs);
263 int pcibios_sriov_disable(struct pci_dev *pdev)
265 if (ppc_md.pcibios_sriov_disable)
266 return ppc_md.pcibios_sriov_disable(pdev);
271 #endif /* CONFIG_PCI_IOV */
273 void pcibios_bus_add_device(struct pci_dev *pdev)
275 if (ppc_md.pcibios_bus_add_device)
276 ppc_md.pcibios_bus_add_device(pdev);
279 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
282 return hose->pci_io_size;
284 return resource_size(&hose->io_resource);
288 int pcibios_vaddr_is_ioport(void __iomem *address)
291 struct pci_controller *hose;
292 resource_size_t size;
294 spin_lock(&hose_spinlock);
295 list_for_each_entry(hose, &hose_list, list_node) {
296 size = pcibios_io_size(hose);
297 if (address >= hose->io_base_virt &&
298 address < (hose->io_base_virt + size)) {
303 spin_unlock(&hose_spinlock);
307 unsigned long pci_address_to_pio(phys_addr_t address)
309 struct pci_controller *hose;
310 resource_size_t size;
311 unsigned long ret = ~0;
313 spin_lock(&hose_spinlock);
314 list_for_each_entry(hose, &hose_list, list_node) {
315 size = pcibios_io_size(hose);
316 if (address >= hose->io_base_phys &&
317 address < (hose->io_base_phys + size)) {
319 (unsigned long)hose->io_base_virt - _IO_BASE;
320 ret = base + (address - hose->io_base_phys);
324 spin_unlock(&hose_spinlock);
328 EXPORT_SYMBOL_GPL(pci_address_to_pio);
331 * Return the domain number for this bus.
333 int pci_domain_nr(struct pci_bus *bus)
335 struct pci_controller *hose = pci_bus_to_host(bus);
337 return hose->global_number;
339 EXPORT_SYMBOL(pci_domain_nr);
341 /* This routine is meant to be used early during boot, when the
342 * PCI bus numbers have not yet been assigned, and you need to
343 * issue PCI config cycles to an OF device.
344 * It could also be used to "fix" RTAS config cycles if you want
345 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
348 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
351 struct pci_controller *hose, *tmp;
352 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
353 if (hose->dn == node)
361 * Reads the interrupt pin to determine if interrupt is use by card.
362 * If the interrupt is used, then gets the interrupt line from the
363 * openfirmware and sets it in the pci_dev and pci_config line.
365 static int pci_read_irq_line(struct pci_dev *pci_dev)
369 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
371 /* Try to get a mapping from the device-tree */
372 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0);
376 /* If that fails, lets fallback to what is in the config
377 * space and map that through the default controller. We
378 * also set the type to level low since that's what PCI
379 * interrupts are. If your platform does differently, then
380 * either provide a proper interrupt tree or don't use this
383 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
387 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
388 line == 0xff || line == 0) {
391 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
394 virq = irq_create_mapping(NULL, line);
396 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
400 pr_debug(" Failed to map !\n");
404 pr_debug(" Mapped to linux irq %d\n", virq);
412 * Platform support for /proc/bus/pci/X/Y mmap()s.
415 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
417 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
418 resource_size_t ioaddr = pci_resource_start(pdev, bar);
423 /* Convert to an offset within this PCI controller */
424 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
426 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
431 * This one is used by /dev/mem and fbdev who have no clue about the
432 * PCI device, it tries to find the PCI device first and calls the
435 pgprot_t pci_phys_mem_access_prot(struct file *file,
440 struct pci_dev *pdev = NULL;
441 struct resource *found = NULL;
442 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
445 if (page_is_ram(pfn))
448 prot = pgprot_noncached(prot);
449 for_each_pci_dev(pdev) {
450 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
451 struct resource *rp = &pdev->resource[i];
452 int flags = rp->flags;
454 /* Active and same type? */
455 if ((flags & IORESOURCE_MEM) == 0)
457 /* In the range of this resource? */
458 if (offset < (rp->start & PAGE_MASK) ||
468 if (found->flags & IORESOURCE_PREFETCH)
469 prot = pgprot_noncached_wc(prot);
473 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
474 (unsigned long long)offset, pgprot_val(prot));
479 /* This provides legacy IO read access on a bus */
480 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
482 unsigned long offset;
483 struct pci_controller *hose = pci_bus_to_host(bus);
484 struct resource *rp = &hose->io_resource;
487 /* Check if port can be supported by that bus. We only check
488 * the ranges of the PHB though, not the bus itself as the rules
489 * for forwarding legacy cycles down bridges are not our problem
490 * here. So if the host bridge supports it, we do it.
492 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
495 if (!(rp->flags & IORESOURCE_IO))
497 if (offset < rp->start || (offset + size) > rp->end)
499 addr = hose->io_base_virt + port;
503 *((u8 *)val) = in_8(addr);
508 *((u16 *)val) = in_le16(addr);
513 *((u32 *)val) = in_le32(addr);
519 /* This provides legacy IO write access on a bus */
520 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
522 unsigned long offset;
523 struct pci_controller *hose = pci_bus_to_host(bus);
524 struct resource *rp = &hose->io_resource;
527 /* Check if port can be supported by that bus. We only check
528 * the ranges of the PHB though, not the bus itself as the rules
529 * for forwarding legacy cycles down bridges are not our problem
530 * here. So if the host bridge supports it, we do it.
532 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
535 if (!(rp->flags & IORESOURCE_IO))
537 if (offset < rp->start || (offset + size) > rp->end)
539 addr = hose->io_base_virt + port;
541 /* WARNING: The generic code is idiotic. It gets passed a pointer
542 * to what can be a 1, 2 or 4 byte quantity and always reads that
543 * as a u32, which means that we have to correct the location of
544 * the data read within those 32 bits for size 1 and 2
548 out_8(addr, val >> 24);
553 out_le16(addr, val >> 16);
564 /* This provides legacy IO or memory mmap access on a bus */
565 int pci_mmap_legacy_page_range(struct pci_bus *bus,
566 struct vm_area_struct *vma,
567 enum pci_mmap_state mmap_state)
569 struct pci_controller *hose = pci_bus_to_host(bus);
570 resource_size_t offset =
571 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
572 resource_size_t size = vma->vm_end - vma->vm_start;
575 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
576 pci_domain_nr(bus), bus->number,
577 mmap_state == pci_mmap_mem ? "MEM" : "IO",
578 (unsigned long long)offset,
579 (unsigned long long)(offset + size - 1));
581 if (mmap_state == pci_mmap_mem) {
584 * Because X is lame and can fail starting if it gets an error trying
585 * to mmap legacy_mem (instead of just moving on without legacy memory
586 * access) we fake it here by giving it anonymous memory, effectively
587 * behaving just like /dev/zero
589 if ((offset + size) > hose->isa_mem_size) {
591 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
592 current->comm, current->pid, pci_domain_nr(bus), bus->number);
593 if (vma->vm_flags & VM_SHARED)
594 return shmem_zero_setup(vma);
597 offset += hose->isa_mem_phys;
599 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
600 unsigned long roffset = offset + io_offset;
601 rp = &hose->io_resource;
602 if (!(rp->flags & IORESOURCE_IO))
604 if (roffset < rp->start || (roffset + size) > rp->end)
606 offset += hose->io_base_phys;
608 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
610 vma->vm_pgoff = offset >> PAGE_SHIFT;
611 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
612 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
613 vma->vm_end - vma->vm_start,
617 void pci_resource_to_user(const struct pci_dev *dev, int bar,
618 const struct resource *rsrc,
619 resource_size_t *start, resource_size_t *end)
621 struct pci_bus_region region;
623 if (rsrc->flags & IORESOURCE_IO) {
624 pcibios_resource_to_bus(dev->bus, ®ion,
625 (struct resource *) rsrc);
626 *start = region.start;
631 /* We pass a CPU physical address to userland for MMIO instead of a
632 * BAR value because X is lame and expects to be able to use that
633 * to pass to /dev/mem!
635 * That means we may have 64-bit values where some apps only expect
636 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
638 *start = rsrc->start;
643 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
644 * @hose: newly allocated pci_controller to be setup
645 * @dev: device node of the host bridge
646 * @primary: set if primary bus (32 bits only, soon to be deprecated)
648 * This function will parse the "ranges" property of a PCI host bridge device
649 * node and setup the resource mapping of a pci controller based on its
652 * Life would be boring if it wasn't for a few issues that we have to deal
655 * - We can only cope with one IO space range and up to 3 Memory space
656 * ranges. However, some machines (thanks Apple !) tend to split their
657 * space into lots of small contiguous ranges. So we have to coalesce.
659 * - Some busses have IO space not starting at 0, which causes trouble with
660 * the way we do our IO resource renumbering. The code somewhat deals with
661 * it for 64 bits but I would expect problems on 32 bits.
663 * - Some 32 bits platforms such as 4xx can have physical space larger than
664 * 32 bits so we need to use 64 bits values for the parsing
666 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
667 struct device_node *dev, int primary)
670 struct resource *res;
671 struct of_pci_range range;
672 struct of_pci_range_parser parser;
674 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
675 dev, primary ? "(primary)" : "");
677 /* Check for ranges property */
678 if (of_pci_range_parser_init(&parser, dev))
682 for_each_of_pci_range(&parser, &range) {
683 /* If we failed translation or got a zero-sized region
684 * (some FW try to feed us with non sensical zero sized regions
685 * such as power3 which look like some kind of attempt at exposing
686 * the VGA memory hole)
688 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
691 /* Act based on address space type */
693 switch (range.flags & IORESOURCE_TYPE_BITS) {
696 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
697 range.cpu_addr, range.cpu_addr + range.size - 1,
700 /* We support only one IO range */
701 if (hose->pci_io_size) {
703 " \\--> Skipped (too many) !\n");
707 /* On 32 bits, limit I/O space to 16MB */
708 if (range.size > 0x01000000)
709 range.size = 0x01000000;
711 /* 32 bits needs to map IOs here */
712 hose->io_base_virt = ioremap(range.cpu_addr,
715 /* Expect trouble if pci_addr is not 0 */
718 (unsigned long)hose->io_base_virt;
719 #endif /* CONFIG_PPC32 */
720 /* pci_io_size and io_base_phys always represent IO
721 * space starting at 0 so we factor in pci_addr
723 hose->pci_io_size = range.pci_addr + range.size;
724 hose->io_base_phys = range.cpu_addr - range.pci_addr;
727 res = &hose->io_resource;
728 range.cpu_addr = range.pci_addr;
732 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
733 range.cpu_addr, range.cpu_addr + range.size - 1,
735 (range.pci_space & 0x40000000) ?
738 /* We support only 3 memory ranges */
741 " \\--> Skipped (too many) !\n");
744 /* Handles ISA memory hole space here */
745 if (range.pci_addr == 0) {
746 if (primary || isa_mem_base == 0)
747 isa_mem_base = range.cpu_addr;
748 hose->isa_mem_phys = range.cpu_addr;
749 hose->isa_mem_size = range.size;
753 hose->mem_offset[memno] = range.cpu_addr -
755 res = &hose->mem_resources[memno++];
759 res->name = dev->full_name;
760 res->flags = range.flags;
761 res->start = range.cpu_addr;
762 res->end = range.cpu_addr + range.size - 1;
763 res->parent = res->child = res->sibling = NULL;
768 /* Decide whether to display the domain number in /proc */
769 int pci_proc_domain(struct pci_bus *bus)
771 struct pci_controller *hose = pci_bus_to_host(bus);
773 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
775 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
776 return hose->global_number != 0;
780 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
782 if (ppc_md.pcibios_root_bridge_prepare)
783 return ppc_md.pcibios_root_bridge_prepare(bridge);
788 /* This header fixup will do the resource fixup for all devices as they are
789 * probed, but not for bridge ranges
791 static void pcibios_fixup_resources(struct pci_dev *dev)
793 struct pci_controller *hose = pci_bus_to_host(dev->bus);
797 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
805 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
806 struct resource *res = dev->resource + i;
807 struct pci_bus_region reg;
811 /* If we're going to re-assign everything, we mark all resources
812 * as unset (and 0-base them). In addition, we mark BARs starting
813 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
814 * since in that case, we don't want to re-assign anything
816 pcibios_resource_to_bus(dev->bus, ®, res);
817 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
818 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
819 /* Only print message if not re-assigning */
820 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
821 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
822 pci_name(dev), i, res);
823 res->end -= res->start;
825 res->flags |= IORESOURCE_UNSET;
829 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
832 /* Call machine specific resource fixup */
833 if (ppc_md.pcibios_fixup_resources)
834 ppc_md.pcibios_fixup_resources(dev);
836 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
838 /* This function tries to figure out if a bridge resource has been initialized
839 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
840 * things go more smoothly when it gets it right. It should covers cases such
841 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
843 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
844 struct resource *res)
846 struct pci_controller *hose = pci_bus_to_host(bus);
847 struct pci_dev *dev = bus->self;
848 resource_size_t offset;
849 struct pci_bus_region region;
853 /* We don't do anything if PCI_PROBE_ONLY is set */
854 if (pci_has_flag(PCI_PROBE_ONLY))
857 /* Job is a bit different between memory and IO */
858 if (res->flags & IORESOURCE_MEM) {
859 pcibios_resource_to_bus(dev->bus, ®ion, res);
861 /* If the BAR is non-0 then it's probably been initialized */
862 if (region.start != 0)
865 /* The BAR is 0, let's check if memory decoding is enabled on
866 * the bridge. If not, we consider it unassigned
868 pci_read_config_word(dev, PCI_COMMAND, &command);
869 if ((command & PCI_COMMAND_MEMORY) == 0)
872 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
873 * resources covers that starting address (0 then it's good enough for
874 * us for memory space)
876 for (i = 0; i < 3; i++) {
877 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
878 hose->mem_resources[i].start == hose->mem_offset[i])
882 /* Well, it starts at 0 and we know it will collide so we may as
883 * well consider it as unassigned. That covers the Apple case.
887 /* If the BAR is non-0, then we consider it assigned */
888 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
889 if (((res->start - offset) & 0xfffffffful) != 0)
892 /* Here, we are a bit different than memory as typically IO space
893 * starting at low addresses -is- valid. What we do instead if that
894 * we consider as unassigned anything that doesn't have IO enabled
895 * in the PCI command register, and that's it.
897 pci_read_config_word(dev, PCI_COMMAND, &command);
898 if (command & PCI_COMMAND_IO)
901 /* It's starting at 0 and IO is disabled in the bridge, consider
908 /* Fixup resources of a PCI<->PCI bridge */
909 static void pcibios_fixup_bridge(struct pci_bus *bus)
911 struct resource *res;
914 struct pci_dev *dev = bus->self;
916 pci_bus_for_each_resource(bus, res, i) {
917 if (!res || !res->flags)
919 if (i >= 3 && bus->self->transparent)
922 /* If we're going to reassign everything, we can
923 * shrink the P2P resource to have size as being
924 * of 0 in order to save space.
926 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
927 res->flags |= IORESOURCE_UNSET;
933 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
935 /* Try to detect uninitialized P2P bridge resources,
936 * and clear them out so they get re-assigned later
938 if (pcibios_uninitialized_bridge_resource(bus, res)) {
940 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
945 void pcibios_setup_bus_self(struct pci_bus *bus)
947 struct pci_controller *phb;
949 /* Fix up the bus resources for P2P bridges */
950 if (bus->self != NULL)
951 pcibios_fixup_bridge(bus);
953 /* Platform specific bus fixups. This is currently only used
954 * by fsl_pci and I'm hoping to get rid of it at some point
956 if (ppc_md.pcibios_fixup_bus)
957 ppc_md.pcibios_fixup_bus(bus);
959 /* Setup bus DMA mappings */
960 phb = pci_bus_to_host(bus);
961 if (phb->controller_ops.dma_bus_setup)
962 phb->controller_ops.dma_bus_setup(bus);
965 static void pcibios_setup_device(struct pci_dev *dev)
967 struct pci_controller *phb;
968 /* Fixup NUMA node as it may not be setup yet by the generic
969 * code and is needed by the DMA init
971 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
973 /* Hook up default DMA ops */
974 set_dma_ops(&dev->dev, pci_dma_ops);
975 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
977 /* Additional platform DMA/iommu setup */
978 phb = pci_bus_to_host(dev->bus);
979 if (phb->controller_ops.dma_dev_setup)
980 phb->controller_ops.dma_dev_setup(dev);
982 /* Read default IRQs and fixup if necessary */
983 pci_read_irq_line(dev);
984 if (ppc_md.pci_irq_fixup)
985 ppc_md.pci_irq_fixup(dev);
988 int pcibios_add_device(struct pci_dev *dev)
991 * We can only call pcibios_setup_device() after bus setup is complete,
992 * since some of the platform specific DMA setup code depends on it.
994 if (dev->bus->is_added)
995 pcibios_setup_device(dev);
997 #ifdef CONFIG_PCI_IOV
998 if (ppc_md.pcibios_fixup_sriov)
999 ppc_md.pcibios_fixup_sriov(dev);
1000 #endif /* CONFIG_PCI_IOV */
1005 void pcibios_setup_bus_devices(struct pci_bus *bus)
1007 struct pci_dev *dev;
1009 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1010 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1012 list_for_each_entry(dev, &bus->devices, bus_list) {
1013 /* Cardbus can call us to add new devices to a bus, so ignore
1014 * those who are already fully discovered
1016 if (pci_dev_is_added(dev))
1019 pcibios_setup_device(dev);
1023 void pcibios_set_master(struct pci_dev *dev)
1025 /* No special bus mastering setup handling */
1028 void pcibios_fixup_bus(struct pci_bus *bus)
1030 /* When called from the generic PCI probe, read PCI<->PCI bridge
1031 * bases. This is -not- called when generating the PCI tree from
1032 * the OF device-tree.
1034 pci_read_bridge_bases(bus);
1036 /* Now fixup the bus bus */
1037 pcibios_setup_bus_self(bus);
1039 /* Now fixup devices on that bus */
1040 pcibios_setup_bus_devices(bus);
1042 EXPORT_SYMBOL(pcibios_fixup_bus);
1044 void pci_fixup_cardbus(struct pci_bus *bus)
1046 /* Now fixup devices on that bus */
1047 pcibios_setup_bus_devices(bus);
1051 static int skip_isa_ioresource_align(struct pci_dev *dev)
1053 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1054 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1060 * We need to avoid collisions with `mirrored' VGA ports
1061 * and other strange ISA hardware, so we always want the
1062 * addresses to be allocated in the 0x000-0x0ff region
1065 * Why? Because some silly external IO cards only decode
1066 * the low 10 bits of the IO address. The 0x00-0xff region
1067 * is reserved for motherboard devices that decode all 16
1068 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1069 * but we want to try to avoid allocating at 0x2900-0x2bff
1070 * which might have be mirrored at 0x0100-0x03ff..
1072 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1073 resource_size_t size, resource_size_t align)
1075 struct pci_dev *dev = data;
1076 resource_size_t start = res->start;
1078 if (res->flags & IORESOURCE_IO) {
1079 if (skip_isa_ioresource_align(dev))
1082 start = (start + 0x3ff) & ~0x3ff;
1087 EXPORT_SYMBOL(pcibios_align_resource);
1090 * Reparent resource children of pr that conflict with res
1091 * under res, and make res replace those children.
1093 static int reparent_resources(struct resource *parent,
1094 struct resource *res)
1096 struct resource *p, **pp;
1097 struct resource **firstpp = NULL;
1099 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1100 if (p->end < res->start)
1102 if (res->end < p->start)
1104 if (p->start < res->start || p->end > res->end)
1105 return -1; /* not completely contained */
1106 if (firstpp == NULL)
1109 if (firstpp == NULL)
1110 return -1; /* didn't find any conflicting entries? */
1111 res->parent = parent;
1112 res->child = *firstpp;
1116 for (p = res->child; p != NULL; p = p->sibling) {
1118 pr_debug("PCI: Reparented %s %pR under %s\n",
1119 p->name, p, res->name);
1125 * Handle resources of PCI devices. If the world were perfect, we could
1126 * just allocate all the resource regions and do nothing more. It isn't.
1127 * On the other hand, we cannot just re-allocate all devices, as it would
1128 * require us to know lots of host bridge internals. So we attempt to
1129 * keep as much of the original configuration as possible, but tweak it
1130 * when it's found to be wrong.
1132 * Known BIOS problems we have to work around:
1133 * - I/O or memory regions not configured
1134 * - regions configured, but not enabled in the command register
1135 * - bogus I/O addresses above 64K used
1136 * - expansion ROMs left enabled (this may sound harmless, but given
1137 * the fact the PCI specs explicitly allow address decoders to be
1138 * shared between expansion ROMs and other resource regions, it's
1139 * at least dangerous)
1142 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1143 * This gives us fixed barriers on where we can allocate.
1144 * (2) Allocate resources for all enabled devices. If there is
1145 * a collision, just mark the resource as unallocated. Also
1146 * disable expansion ROMs during this step.
1147 * (3) Try to allocate resources for disabled devices. If the
1148 * resources were assigned correctly, everything goes well,
1149 * if they weren't, they won't disturb allocation of other
1151 * (4) Assign new addresses to resources which were either
1152 * not configured at all or misconfigured. If explicitly
1153 * requested by the user, configure expansion ROM address
1157 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1161 struct resource *res, *pr;
1163 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1164 pci_domain_nr(bus), bus->number);
1166 pci_bus_for_each_resource(bus, res, i) {
1167 if (!res || !res->flags || res->start > res->end || res->parent)
1170 /* If the resource was left unset at this point, we clear it */
1171 if (res->flags & IORESOURCE_UNSET)
1172 goto clear_resource;
1174 if (bus->parent == NULL)
1175 pr = (res->flags & IORESOURCE_IO) ?
1176 &ioport_resource : &iomem_resource;
1178 pr = pci_find_parent_resource(bus->self, res);
1180 /* this happens when the generic PCI
1181 * code (wrongly) decides that this
1182 * bridge is transparent -- paulus
1188 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1189 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1190 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1192 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1193 struct pci_dev *dev = bus->self;
1195 if (request_resource(pr, res) == 0)
1198 * Must be a conflict with an existing entry.
1199 * Move that entry (or entries) under the
1200 * bridge resource and try again.
1202 if (reparent_resources(pr, res) == 0)
1205 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1206 pci_claim_bridge_resource(dev,
1207 i + PCI_BRIDGE_RESOURCES) == 0)
1210 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n",
1213 /* The resource might be figured out when doing
1214 * reassignment based on the resources required
1215 * by the downstream PCI devices. Here we set
1216 * the size of the resource to be 0 in order to
1224 list_for_each_entry(b, &bus->children, node)
1225 pcibios_allocate_bus_resources(b);
1228 static inline void alloc_resource(struct pci_dev *dev, int idx)
1230 struct resource *pr, *r = &dev->resource[idx];
1232 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1233 pci_name(dev), idx, r);
1235 pr = pci_find_parent_resource(dev, r);
1236 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1237 request_resource(pr, r) < 0) {
1238 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1239 " of device %s, will remap\n", idx, pci_name(dev));
1241 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1242 /* We'll assign a new address later */
1243 r->flags |= IORESOURCE_UNSET;
1249 static void __init pcibios_allocate_resources(int pass)
1251 struct pci_dev *dev = NULL;
1256 for_each_pci_dev(dev) {
1257 pci_read_config_word(dev, PCI_COMMAND, &command);
1258 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1259 r = &dev->resource[idx];
1260 if (r->parent) /* Already allocated */
1262 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1263 continue; /* Not assigned at all */
1264 /* We only allocate ROMs on pass 1 just in case they
1265 * have been screwed up by firmware
1267 if (idx == PCI_ROM_RESOURCE )
1269 if (r->flags & IORESOURCE_IO)
1270 disabled = !(command & PCI_COMMAND_IO);
1272 disabled = !(command & PCI_COMMAND_MEMORY);
1273 if (pass == disabled)
1274 alloc_resource(dev, idx);
1278 r = &dev->resource[PCI_ROM_RESOURCE];
1280 /* Turn the ROM off, leave the resource region,
1281 * but keep it unregistered.
1284 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1285 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1286 pr_debug("PCI: Switching off ROM of %s\n",
1288 r->flags &= ~IORESOURCE_ROM_ENABLE;
1289 pci_write_config_dword(dev, dev->rom_base_reg,
1290 reg & ~PCI_ROM_ADDRESS_ENABLE);
1296 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1298 struct pci_controller *hose = pci_bus_to_host(bus);
1299 resource_size_t offset;
1300 struct resource *res, *pres;
1303 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1306 if (!(hose->io_resource.flags & IORESOURCE_IO))
1308 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1309 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1310 BUG_ON(res == NULL);
1311 res->name = "Legacy IO";
1312 res->flags = IORESOURCE_IO;
1313 res->start = offset;
1314 res->end = (offset + 0xfff) & 0xfffffffful;
1315 pr_debug("Candidate legacy IO: %pR\n", res);
1316 if (request_resource(&hose->io_resource, res)) {
1318 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1319 pci_domain_nr(bus), bus->number, res);
1324 /* Check for memory */
1325 for (i = 0; i < 3; i++) {
1326 pres = &hose->mem_resources[i];
1327 offset = hose->mem_offset[i];
1328 if (!(pres->flags & IORESOURCE_MEM))
1330 pr_debug("hose mem res: %pR\n", pres);
1331 if ((pres->start - offset) <= 0xa0000 &&
1332 (pres->end - offset) >= 0xbffff)
1337 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1338 BUG_ON(res == NULL);
1339 res->name = "Legacy VGA memory";
1340 res->flags = IORESOURCE_MEM;
1341 res->start = 0xa0000 + offset;
1342 res->end = 0xbffff + offset;
1343 pr_debug("Candidate VGA memory: %pR\n", res);
1344 if (request_resource(pres, res)) {
1346 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1347 pci_domain_nr(bus), bus->number, res);
1352 void __init pcibios_resource_survey(void)
1356 /* Allocate and assign resources */
1357 list_for_each_entry(b, &pci_root_buses, node)
1358 pcibios_allocate_bus_resources(b);
1359 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1360 pcibios_allocate_resources(0);
1361 pcibios_allocate_resources(1);
1364 /* Before we start assigning unassigned resource, we try to reserve
1365 * the low IO area and the VGA memory area if they intersect the
1366 * bus available resources to avoid allocating things on top of them
1368 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1369 list_for_each_entry(b, &pci_root_buses, node)
1370 pcibios_reserve_legacy_regions(b);
1373 /* Now, if the platform didn't decide to blindly trust the firmware,
1374 * we proceed to assigning things that were left unassigned
1376 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1377 pr_debug("PCI: Assigning unassigned resources...\n");
1378 pci_assign_unassigned_resources();
1381 /* Call machine dependent fixup */
1382 if (ppc_md.pcibios_fixup)
1383 ppc_md.pcibios_fixup();
1386 /* This is used by the PCI hotplug driver to allocate resource
1387 * of newly plugged busses. We can try to consolidate with the
1388 * rest of the code later, for now, keep it as-is as our main
1389 * resource allocation function doesn't deal with sub-trees yet.
1391 void pcibios_claim_one_bus(struct pci_bus *bus)
1393 struct pci_dev *dev;
1394 struct pci_bus *child_bus;
1396 list_for_each_entry(dev, &bus->devices, bus_list) {
1399 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1400 struct resource *r = &dev->resource[i];
1402 if (r->parent || !r->start || !r->flags)
1405 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1406 pci_name(dev), i, r);
1408 if (pci_claim_resource(dev, i) == 0)
1411 pci_claim_bridge_resource(dev, i);
1415 list_for_each_entry(child_bus, &bus->children, node)
1416 pcibios_claim_one_bus(child_bus);
1418 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1421 /* pcibios_finish_adding_to_bus
1423 * This is to be called by the hotplug code after devices have been
1424 * added to a bus, this include calling it for a PHB that is just
1427 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1429 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1430 pci_domain_nr(bus), bus->number);
1432 /* Allocate bus and devices resources */
1433 pcibios_allocate_bus_resources(bus);
1434 pcibios_claim_one_bus(bus);
1435 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1437 pci_assign_unassigned_bridge_resources(bus->self);
1439 pci_assign_unassigned_bus_resources(bus);
1443 eeh_add_device_tree_late(bus);
1445 /* Add new devices to global lists. Register in proc, sysfs. */
1446 pci_bus_add_devices(bus);
1448 /* sysfs files should only be added after devices are added */
1449 eeh_add_sysfs_files(bus);
1451 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1453 int pcibios_enable_device(struct pci_dev *dev, int mask)
1455 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1457 if (phb->controller_ops.enable_device_hook)
1458 if (!phb->controller_ops.enable_device_hook(dev))
1461 return pci_enable_resources(dev, mask);
1464 void pcibios_disable_device(struct pci_dev *dev)
1466 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1468 if (phb->controller_ops.disable_device)
1469 phb->controller_ops.disable_device(dev);
1472 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1474 return (unsigned long) hose->io_base_virt - _IO_BASE;
1477 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1478 struct list_head *resources)
1480 struct resource *res;
1481 resource_size_t offset;
1484 /* Hookup PHB IO resource */
1485 res = &hose->io_resource;
1488 pr_debug("PCI: I/O resource not set for host"
1489 " bridge %pOF (domain %d)\n",
1490 hose->dn, hose->global_number);
1492 offset = pcibios_io_space_offset(hose);
1494 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1495 res, (unsigned long long)offset);
1496 pci_add_resource_offset(resources, res, offset);
1499 /* Hookup PHB Memory resources */
1500 for (i = 0; i < 3; ++i) {
1501 res = &hose->mem_resources[i];
1505 offset = hose->mem_offset[i];
1506 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1507 res, (unsigned long long)offset);
1509 pci_add_resource_offset(resources, res, offset);
1514 * Null PCI config access functions, for the case when we can't
1517 #define NULL_PCI_OP(rw, size, type) \
1519 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1521 return PCIBIOS_DEVICE_NOT_FOUND; \
1525 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1528 return PCIBIOS_DEVICE_NOT_FOUND;
1532 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1535 return PCIBIOS_DEVICE_NOT_FOUND;
1538 static struct pci_ops null_pci_ops =
1540 .read = null_read_config,
1541 .write = null_write_config,
1545 * These functions are used early on before PCI scanning is done
1546 * and all of the pci_dev and pci_bus structures have been created.
1548 static struct pci_bus *
1549 fake_pci_bus(struct pci_controller *hose, int busnr)
1551 static struct pci_bus bus;
1554 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1558 bus.ops = hose? hose->ops: &null_pci_ops;
1562 #define EARLY_PCI_OP(rw, size, type) \
1563 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1564 int devfn, int offset, type value) \
1566 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1567 devfn, offset, value); \
1570 EARLY_PCI_OP(read, byte, u8 *)
1571 EARLY_PCI_OP(read, word, u16 *)
1572 EARLY_PCI_OP(read, dword, u32 *)
1573 EARLY_PCI_OP(write, byte, u8)
1574 EARLY_PCI_OP(write, word, u16)
1575 EARLY_PCI_OP(write, dword, u32)
1577 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1580 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1583 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1585 struct pci_controller *hose = bus->sysdata;
1587 return of_node_get(hose->dn);
1591 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1592 * @hose: Pointer to the PCI host controller instance structure
1594 void pcibios_scan_phb(struct pci_controller *hose)
1596 LIST_HEAD(resources);
1597 struct pci_bus *bus;
1598 struct device_node *node = hose->dn;
1601 pr_debug("PCI: Scanning PHB %pOF\n", node);
1603 /* Get some IO space for the new PHB */
1604 pcibios_setup_phb_io_space(hose);
1606 /* Wire up PHB bus resources */
1607 pcibios_setup_phb_resources(hose, &resources);
1609 hose->busn.start = hose->first_busno;
1610 hose->busn.end = hose->last_busno;
1611 hose->busn.flags = IORESOURCE_BUS;
1612 pci_add_resource(&resources, &hose->busn);
1614 /* Create an empty bus for the toplevel */
1615 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1616 hose->ops, hose, &resources);
1618 pr_err("Failed to create bus for PCI domain %04x\n",
1619 hose->global_number);
1620 pci_free_resource_list(&resources);
1625 /* Get probe mode and perform scan */
1626 mode = PCI_PROBE_NORMAL;
1627 if (node && hose->controller_ops.probe_mode)
1628 mode = hose->controller_ops.probe_mode(bus);
1629 pr_debug(" probe mode: %d\n", mode);
1630 if (mode == PCI_PROBE_DEVTREE)
1631 of_scan_bus(node, bus);
1633 if (mode == PCI_PROBE_NORMAL) {
1634 pci_bus_update_busn_res_end(bus, 255);
1635 hose->last_busno = pci_scan_child_bus(bus);
1636 pci_bus_update_busn_res_end(bus, hose->last_busno);
1639 /* Platform gets a chance to do some global fixups before
1640 * we proceed to resource allocation
1642 if (ppc_md.pcibios_fixup_phb)
1643 ppc_md.pcibios_fixup_phb(hose);
1645 /* Configure PCI Express settings */
1646 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1647 struct pci_bus *child;
1648 list_for_each_entry(child, &bus->children, node)
1649 pcie_bus_configure_settings(child);
1652 EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1654 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1656 int i, class = dev->class >> 8;
1657 /* When configured as agent, programing interface = 1 */
1658 int prog_if = dev->class & 0xf;
1660 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1661 class == PCI_CLASS_BRIDGE_OTHER) &&
1662 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1664 (dev->bus->parent == NULL)) {
1665 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1666 dev->resource[i].start = 0;
1667 dev->resource[i].end = 0;
1668 dev->resource[i].flags = 0;
1672 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1673 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);