2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/export.h>
25 #include <linux/of_address.h>
26 #include <linux/of_pci.h>
28 #include <linux/shmem_fs.h>
29 #include <linux/list.h>
30 #include <linux/syscalls.h>
31 #include <linux/irq.h>
32 #include <linux/vmalloc.h>
33 #include <linux/slab.h>
34 #include <linux/vgaarb.h>
36 #include <asm/processor.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/byteorder.h>
41 #include <asm/machdep.h>
42 #include <asm/ppc-pci.h>
45 /* hose_spinlock protects accesses to the the phb_bitmap. */
46 static DEFINE_SPINLOCK(hose_spinlock);
49 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
50 #define MAX_PHBS 0x10000
53 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
54 * Accesses to this bitmap should be protected by hose_spinlock.
56 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
58 /* ISA Memory physical address */
59 resource_size_t isa_mem_base;
60 EXPORT_SYMBOL(isa_mem_base);
63 static const struct dma_map_ops *pci_dma_ops = &dma_nommu_ops;
65 void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
67 pci_dma_ops = dma_ops;
70 const struct dma_map_ops *get_pci_dma_ops(void)
74 EXPORT_SYMBOL(get_pci_dma_ops);
77 * This function should run under locking protection, specifically
80 static int get_phb_number(struct device_node *dn)
87 * Try fixed PHB numbering first, by checking archs and reading
88 * the respective device-tree properties. Firstly, try powernv by
89 * reading "ibm,opal-phbid", only present in OPAL environment.
91 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
93 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
98 phb_id = (int)(prop & (MAX_PHBS - 1));
100 /* We need to be sure to not use the same PHB number twice. */
101 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
105 * If not pseries nor powernv, or if fixed PHB numbering tried to add
106 * the same PHB number twice, then fallback to dynamic PHB numbering.
108 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
109 BUG_ON(phb_id >= MAX_PHBS);
110 set_bit(phb_id, phb_bitmap);
115 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
117 struct pci_controller *phb;
119 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
122 spin_lock(&hose_spinlock);
123 phb->global_number = get_phb_number(dev);
124 list_add_tail(&phb->list_node, &hose_list);
125 spin_unlock(&hose_spinlock);
127 phb->is_dynamic = slab_is_available();
130 int nid = of_node_to_nid(dev);
132 if (nid < 0 || !node_online(nid))
135 PHB_SET_NODE(phb, nid);
140 EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
142 void pcibios_free_controller(struct pci_controller *phb)
144 spin_lock(&hose_spinlock);
146 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
147 if (phb->global_number < MAX_PHBS)
148 clear_bit(phb->global_number, phb_bitmap);
150 list_del(&phb->list_node);
151 spin_unlock(&hose_spinlock);
156 EXPORT_SYMBOL_GPL(pcibios_free_controller);
159 * This function is used to call pcibios_free_controller()
160 * in a deferred manner: a callback from the PCI subsystem.
162 * _*DO NOT*_ call pcibios_free_controller() explicitly if
163 * this is used (or it may access an invalid *phb pointer).
165 * The callback occurs when all references to the root bus
166 * are dropped (e.g., child buses/devices and their users).
168 * It's called as .release_fn() of 'struct pci_host_bridge'
169 * which is associated with the 'struct pci_controller.bus'
170 * (root bus) - it expects .release_data to hold a pointer
171 * to 'struct pci_controller'.
173 * In order to use it, register .release_fn()/release_data
176 * pci_set_host_bridge_release(bridge,
177 * pcibios_free_controller_deferred
180 * e.g. in the pcibios_root_bridge_prepare() callback from
181 * pci_create_root_bus().
183 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
185 struct pci_controller *phb = (struct pci_controller *)
186 bridge->release_data;
188 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
190 pcibios_free_controller(phb);
192 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
195 * The function is used to return the minimal alignment
196 * for memory or I/O windows of the associated P2P bridge.
197 * By default, 4KiB alignment for I/O windows and 1MiB for
200 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
203 struct pci_controller *phb = pci_bus_to_host(bus);
205 if (phb->controller_ops.window_alignment)
206 return phb->controller_ops.window_alignment(bus, type);
209 * PCI core will figure out the default
210 * alignment: 4KiB for I/O and 1MiB for
216 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
218 struct pci_controller *hose = pci_bus_to_host(bus);
220 if (hose->controller_ops.setup_bridge)
221 hose->controller_ops.setup_bridge(bus, type);
224 void pcibios_reset_secondary_bus(struct pci_dev *dev)
226 struct pci_controller *phb = pci_bus_to_host(dev->bus);
228 if (phb->controller_ops.reset_secondary_bus) {
229 phb->controller_ops.reset_secondary_bus(dev);
233 pci_reset_secondary_bus(dev);
236 resource_size_t pcibios_default_alignment(void)
238 if (ppc_md.pcibios_default_alignment)
239 return ppc_md.pcibios_default_alignment();
244 #ifdef CONFIG_PCI_IOV
245 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
247 if (ppc_md.pcibios_iov_resource_alignment)
248 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
250 return pci_iov_resource_size(pdev, resno);
253 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
255 if (ppc_md.pcibios_sriov_enable)
256 return ppc_md.pcibios_sriov_enable(pdev, num_vfs);
261 int pcibios_sriov_disable(struct pci_dev *pdev)
263 if (ppc_md.pcibios_sriov_disable)
264 return ppc_md.pcibios_sriov_disable(pdev);
269 #endif /* CONFIG_PCI_IOV */
271 void pcibios_bus_add_device(struct pci_dev *pdev)
273 if (ppc_md.pcibios_bus_add_device)
274 ppc_md.pcibios_bus_add_device(pdev);
277 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
280 return hose->pci_io_size;
282 return resource_size(&hose->io_resource);
286 int pcibios_vaddr_is_ioport(void __iomem *address)
289 struct pci_controller *hose;
290 resource_size_t size;
292 spin_lock(&hose_spinlock);
293 list_for_each_entry(hose, &hose_list, list_node) {
294 size = pcibios_io_size(hose);
295 if (address >= hose->io_base_virt &&
296 address < (hose->io_base_virt + size)) {
301 spin_unlock(&hose_spinlock);
305 unsigned long pci_address_to_pio(phys_addr_t address)
307 struct pci_controller *hose;
308 resource_size_t size;
309 unsigned long ret = ~0;
311 spin_lock(&hose_spinlock);
312 list_for_each_entry(hose, &hose_list, list_node) {
313 size = pcibios_io_size(hose);
314 if (address >= hose->io_base_phys &&
315 address < (hose->io_base_phys + size)) {
317 (unsigned long)hose->io_base_virt - _IO_BASE;
318 ret = base + (address - hose->io_base_phys);
322 spin_unlock(&hose_spinlock);
326 EXPORT_SYMBOL_GPL(pci_address_to_pio);
329 * Return the domain number for this bus.
331 int pci_domain_nr(struct pci_bus *bus)
333 struct pci_controller *hose = pci_bus_to_host(bus);
335 return hose->global_number;
337 EXPORT_SYMBOL(pci_domain_nr);
339 /* This routine is meant to be used early during boot, when the
340 * PCI bus numbers have not yet been assigned, and you need to
341 * issue PCI config cycles to an OF device.
342 * It could also be used to "fix" RTAS config cycles if you want
343 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
346 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
349 struct pci_controller *hose, *tmp;
350 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
351 if (hose->dn == node)
359 * Reads the interrupt pin to determine if interrupt is use by card.
360 * If the interrupt is used, then gets the interrupt line from the
361 * openfirmware and sets it in the pci_dev and pci_config line.
363 static int pci_read_irq_line(struct pci_dev *pci_dev)
365 struct of_phandle_args oirq;
368 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
371 memset(&oirq, 0xff, sizeof(oirq));
373 /* Try to get a mapping from the device-tree */
374 if (of_irq_parse_pci(pci_dev, &oirq)) {
377 /* If that fails, lets fallback to what is in the config
378 * space and map that through the default controller. We
379 * also set the type to level low since that's what PCI
380 * interrupts are. If your platform does differently, then
381 * either provide a proper interrupt tree or don't use this
384 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
388 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
389 line == 0xff || line == 0) {
392 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
395 virq = irq_create_mapping(NULL, line);
397 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
399 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %pOF\n",
400 oirq.args_count, oirq.args[0], oirq.args[1], oirq.np);
402 virq = irq_create_of_mapping(&oirq);
406 pr_debug(" Failed to map !\n");
410 pr_debug(" Mapped to linux irq %d\n", virq);
418 * Platform support for /proc/bus/pci/X/Y mmap()s,
419 * modelled on the sparc64 implementation by Dave Miller.
424 * Adjust vm_pgoff of VMA such that it is the physical page offset
425 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
427 * Basically, the user finds the base address for his device which he wishes
428 * to mmap. They read the 32-bit value from the config space base register,
429 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
430 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
432 * Returns negative error code on failure, zero on success.
434 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
435 resource_size_t *offset,
436 enum pci_mmap_state mmap_state)
438 struct pci_controller *hose = pci_bus_to_host(dev->bus);
439 unsigned long io_offset = 0;
443 return NULL; /* should never happen */
445 /* If memory, add on the PCI bridge address offset */
446 if (mmap_state == pci_mmap_mem) {
447 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
448 *offset += hose->pci_mem_offset;
450 res_bit = IORESOURCE_MEM;
452 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
453 *offset += io_offset;
454 res_bit = IORESOURCE_IO;
458 * Check that the offset requested corresponds to one of the
459 * resources of the device.
461 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
462 struct resource *rp = &dev->resource[i];
463 int flags = rp->flags;
465 /* treat ROM as memory (should be already) */
466 if (i == PCI_ROM_RESOURCE)
467 flags |= IORESOURCE_MEM;
469 /* Active and same type? */
470 if ((flags & res_bit) == 0)
473 /* In the range of this resource? */
474 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
477 /* found it! construct the final physical address */
478 if (mmap_state == pci_mmap_io)
479 *offset += hose->io_base_phys - io_offset;
487 * This one is used by /dev/mem and fbdev who have no clue about the
488 * PCI device, it tries to find the PCI device first and calls the
491 pgprot_t pci_phys_mem_access_prot(struct file *file,
496 struct pci_dev *pdev = NULL;
497 struct resource *found = NULL;
498 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
501 if (page_is_ram(pfn))
504 prot = pgprot_noncached(prot);
505 for_each_pci_dev(pdev) {
506 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
507 struct resource *rp = &pdev->resource[i];
508 int flags = rp->flags;
510 /* Active and same type? */
511 if ((flags & IORESOURCE_MEM) == 0)
513 /* In the range of this resource? */
514 if (offset < (rp->start & PAGE_MASK) ||
524 if (found->flags & IORESOURCE_PREFETCH)
525 prot = pgprot_noncached_wc(prot);
529 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
530 (unsigned long long)offset, pgprot_val(prot));
537 * Perform the actual remap of the pages for a PCI device mapping, as
538 * appropriate for this architecture. The region in the process to map
539 * is described by vm_start and vm_end members of VMA, the base physical
540 * address is found in vm_pgoff.
541 * The pci device structure is provided so that architectures may make mapping
542 * decisions on a per-device or per-bus basis.
544 * Returns a negative error code on failure, zero on success.
546 int pci_mmap_page_range(struct pci_dev *dev, int bar,
547 struct vm_area_struct *vma,
548 enum pci_mmap_state mmap_state, int write_combine)
550 resource_size_t offset =
551 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
555 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
559 vma->vm_pgoff = offset >> PAGE_SHIFT;
561 vma->vm_page_prot = pgprot_noncached_wc(vma->vm_page_prot);
563 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
565 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
566 vma->vm_end - vma->vm_start, vma->vm_page_prot);
571 /* This provides legacy IO read access on a bus */
572 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
574 unsigned long offset;
575 struct pci_controller *hose = pci_bus_to_host(bus);
576 struct resource *rp = &hose->io_resource;
579 /* Check if port can be supported by that bus. We only check
580 * the ranges of the PHB though, not the bus itself as the rules
581 * for forwarding legacy cycles down bridges are not our problem
582 * here. So if the host bridge supports it, we do it.
584 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
587 if (!(rp->flags & IORESOURCE_IO))
589 if (offset < rp->start || (offset + size) > rp->end)
591 addr = hose->io_base_virt + port;
595 *((u8 *)val) = in_8(addr);
600 *((u16 *)val) = in_le16(addr);
605 *((u32 *)val) = in_le32(addr);
611 /* This provides legacy IO write access on a bus */
612 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
614 unsigned long offset;
615 struct pci_controller *hose = pci_bus_to_host(bus);
616 struct resource *rp = &hose->io_resource;
619 /* Check if port can be supported by that bus. We only check
620 * the ranges of the PHB though, not the bus itself as the rules
621 * for forwarding legacy cycles down bridges are not our problem
622 * here. So if the host bridge supports it, we do it.
624 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
627 if (!(rp->flags & IORESOURCE_IO))
629 if (offset < rp->start || (offset + size) > rp->end)
631 addr = hose->io_base_virt + port;
633 /* WARNING: The generic code is idiotic. It gets passed a pointer
634 * to what can be a 1, 2 or 4 byte quantity and always reads that
635 * as a u32, which means that we have to correct the location of
636 * the data read within those 32 bits for size 1 and 2
640 out_8(addr, val >> 24);
645 out_le16(addr, val >> 16);
656 /* This provides legacy IO or memory mmap access on a bus */
657 int pci_mmap_legacy_page_range(struct pci_bus *bus,
658 struct vm_area_struct *vma,
659 enum pci_mmap_state mmap_state)
661 struct pci_controller *hose = pci_bus_to_host(bus);
662 resource_size_t offset =
663 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
664 resource_size_t size = vma->vm_end - vma->vm_start;
667 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
668 pci_domain_nr(bus), bus->number,
669 mmap_state == pci_mmap_mem ? "MEM" : "IO",
670 (unsigned long long)offset,
671 (unsigned long long)(offset + size - 1));
673 if (mmap_state == pci_mmap_mem) {
676 * Because X is lame and can fail starting if it gets an error trying
677 * to mmap legacy_mem (instead of just moving on without legacy memory
678 * access) we fake it here by giving it anonymous memory, effectively
679 * behaving just like /dev/zero
681 if ((offset + size) > hose->isa_mem_size) {
683 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
684 current->comm, current->pid, pci_domain_nr(bus), bus->number);
685 if (vma->vm_flags & VM_SHARED)
686 return shmem_zero_setup(vma);
689 offset += hose->isa_mem_phys;
691 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
692 unsigned long roffset = offset + io_offset;
693 rp = &hose->io_resource;
694 if (!(rp->flags & IORESOURCE_IO))
696 if (roffset < rp->start || (roffset + size) > rp->end)
698 offset += hose->io_base_phys;
700 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
702 vma->vm_pgoff = offset >> PAGE_SHIFT;
703 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
704 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
705 vma->vm_end - vma->vm_start,
709 void pci_resource_to_user(const struct pci_dev *dev, int bar,
710 const struct resource *rsrc,
711 resource_size_t *start, resource_size_t *end)
713 struct pci_bus_region region;
715 if (rsrc->flags & IORESOURCE_IO) {
716 pcibios_resource_to_bus(dev->bus, ®ion,
717 (struct resource *) rsrc);
718 *start = region.start;
723 /* We pass a CPU physical address to userland for MMIO instead of a
724 * BAR value because X is lame and expects to be able to use that
725 * to pass to /dev/mem!
727 * That means we may have 64-bit values where some apps only expect
728 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
730 *start = rsrc->start;
735 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
736 * @hose: newly allocated pci_controller to be setup
737 * @dev: device node of the host bridge
738 * @primary: set if primary bus (32 bits only, soon to be deprecated)
740 * This function will parse the "ranges" property of a PCI host bridge device
741 * node and setup the resource mapping of a pci controller based on its
744 * Life would be boring if it wasn't for a few issues that we have to deal
747 * - We can only cope with one IO space range and up to 3 Memory space
748 * ranges. However, some machines (thanks Apple !) tend to split their
749 * space into lots of small contiguous ranges. So we have to coalesce.
751 * - Some busses have IO space not starting at 0, which causes trouble with
752 * the way we do our IO resource renumbering. The code somewhat deals with
753 * it for 64 bits but I would expect problems on 32 bits.
755 * - Some 32 bits platforms such as 4xx can have physical space larger than
756 * 32 bits so we need to use 64 bits values for the parsing
758 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
759 struct device_node *dev, int primary)
762 struct resource *res;
763 struct of_pci_range range;
764 struct of_pci_range_parser parser;
766 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
767 dev, primary ? "(primary)" : "");
769 /* Check for ranges property */
770 if (of_pci_range_parser_init(&parser, dev))
774 for_each_of_pci_range(&parser, &range) {
775 /* If we failed translation or got a zero-sized region
776 * (some FW try to feed us with non sensical zero sized regions
777 * such as power3 which look like some kind of attempt at exposing
778 * the VGA memory hole)
780 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
783 /* Act based on address space type */
785 switch (range.flags & IORESOURCE_TYPE_BITS) {
788 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
789 range.cpu_addr, range.cpu_addr + range.size - 1,
792 /* We support only one IO range */
793 if (hose->pci_io_size) {
795 " \\--> Skipped (too many) !\n");
799 /* On 32 bits, limit I/O space to 16MB */
800 if (range.size > 0x01000000)
801 range.size = 0x01000000;
803 /* 32 bits needs to map IOs here */
804 hose->io_base_virt = ioremap(range.cpu_addr,
807 /* Expect trouble if pci_addr is not 0 */
810 (unsigned long)hose->io_base_virt;
811 #endif /* CONFIG_PPC32 */
812 /* pci_io_size and io_base_phys always represent IO
813 * space starting at 0 so we factor in pci_addr
815 hose->pci_io_size = range.pci_addr + range.size;
816 hose->io_base_phys = range.cpu_addr - range.pci_addr;
819 res = &hose->io_resource;
820 range.cpu_addr = range.pci_addr;
824 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
825 range.cpu_addr, range.cpu_addr + range.size - 1,
827 (range.pci_space & 0x40000000) ?
830 /* We support only 3 memory ranges */
833 " \\--> Skipped (too many) !\n");
836 /* Handles ISA memory hole space here */
837 if (range.pci_addr == 0) {
838 if (primary || isa_mem_base == 0)
839 isa_mem_base = range.cpu_addr;
840 hose->isa_mem_phys = range.cpu_addr;
841 hose->isa_mem_size = range.size;
845 hose->mem_offset[memno] = range.cpu_addr -
847 res = &hose->mem_resources[memno++];
851 res->name = dev->full_name;
852 res->flags = range.flags;
853 res->start = range.cpu_addr;
854 res->end = range.cpu_addr + range.size - 1;
855 res->parent = res->child = res->sibling = NULL;
860 /* Decide whether to display the domain number in /proc */
861 int pci_proc_domain(struct pci_bus *bus)
863 struct pci_controller *hose = pci_bus_to_host(bus);
865 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
867 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
868 return hose->global_number != 0;
872 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
874 if (ppc_md.pcibios_root_bridge_prepare)
875 return ppc_md.pcibios_root_bridge_prepare(bridge);
880 /* This header fixup will do the resource fixup for all devices as they are
881 * probed, but not for bridge ranges
883 static void pcibios_fixup_resources(struct pci_dev *dev)
885 struct pci_controller *hose = pci_bus_to_host(dev->bus);
889 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
897 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
898 struct resource *res = dev->resource + i;
899 struct pci_bus_region reg;
903 /* If we're going to re-assign everything, we mark all resources
904 * as unset (and 0-base them). In addition, we mark BARs starting
905 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
906 * since in that case, we don't want to re-assign anything
908 pcibios_resource_to_bus(dev->bus, ®, res);
909 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
910 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
911 /* Only print message if not re-assigning */
912 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
913 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
914 pci_name(dev), i, res);
915 res->end -= res->start;
917 res->flags |= IORESOURCE_UNSET;
921 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
924 /* Call machine specific resource fixup */
925 if (ppc_md.pcibios_fixup_resources)
926 ppc_md.pcibios_fixup_resources(dev);
928 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
930 /* This function tries to figure out if a bridge resource has been initialized
931 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
932 * things go more smoothly when it gets it right. It should covers cases such
933 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
935 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
936 struct resource *res)
938 struct pci_controller *hose = pci_bus_to_host(bus);
939 struct pci_dev *dev = bus->self;
940 resource_size_t offset;
941 struct pci_bus_region region;
945 /* We don't do anything if PCI_PROBE_ONLY is set */
946 if (pci_has_flag(PCI_PROBE_ONLY))
949 /* Job is a bit different between memory and IO */
950 if (res->flags & IORESOURCE_MEM) {
951 pcibios_resource_to_bus(dev->bus, ®ion, res);
953 /* If the BAR is non-0 then it's probably been initialized */
954 if (region.start != 0)
957 /* The BAR is 0, let's check if memory decoding is enabled on
958 * the bridge. If not, we consider it unassigned
960 pci_read_config_word(dev, PCI_COMMAND, &command);
961 if ((command & PCI_COMMAND_MEMORY) == 0)
964 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
965 * resources covers that starting address (0 then it's good enough for
966 * us for memory space)
968 for (i = 0; i < 3; i++) {
969 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
970 hose->mem_resources[i].start == hose->mem_offset[i])
974 /* Well, it starts at 0 and we know it will collide so we may as
975 * well consider it as unassigned. That covers the Apple case.
979 /* If the BAR is non-0, then we consider it assigned */
980 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
981 if (((res->start - offset) & 0xfffffffful) != 0)
984 /* Here, we are a bit different than memory as typically IO space
985 * starting at low addresses -is- valid. What we do instead if that
986 * we consider as unassigned anything that doesn't have IO enabled
987 * in the PCI command register, and that's it.
989 pci_read_config_word(dev, PCI_COMMAND, &command);
990 if (command & PCI_COMMAND_IO)
993 /* It's starting at 0 and IO is disabled in the bridge, consider
1000 /* Fixup resources of a PCI<->PCI bridge */
1001 static void pcibios_fixup_bridge(struct pci_bus *bus)
1003 struct resource *res;
1006 struct pci_dev *dev = bus->self;
1008 pci_bus_for_each_resource(bus, res, i) {
1009 if (!res || !res->flags)
1011 if (i >= 3 && bus->self->transparent)
1014 /* If we're going to reassign everything, we can
1015 * shrink the P2P resource to have size as being
1016 * of 0 in order to save space.
1018 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1019 res->flags |= IORESOURCE_UNSET;
1025 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
1027 /* Try to detect uninitialized P2P bridge resources,
1028 * and clear them out so they get re-assigned later
1030 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1032 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
1037 void pcibios_setup_bus_self(struct pci_bus *bus)
1039 struct pci_controller *phb;
1041 /* Fix up the bus resources for P2P bridges */
1042 if (bus->self != NULL)
1043 pcibios_fixup_bridge(bus);
1045 /* Platform specific bus fixups. This is currently only used
1046 * by fsl_pci and I'm hoping to get rid of it at some point
1048 if (ppc_md.pcibios_fixup_bus)
1049 ppc_md.pcibios_fixup_bus(bus);
1051 /* Setup bus DMA mappings */
1052 phb = pci_bus_to_host(bus);
1053 if (phb->controller_ops.dma_bus_setup)
1054 phb->controller_ops.dma_bus_setup(bus);
1057 static void pcibios_setup_device(struct pci_dev *dev)
1059 struct pci_controller *phb;
1060 /* Fixup NUMA node as it may not be setup yet by the generic
1061 * code and is needed by the DMA init
1063 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1065 /* Hook up default DMA ops */
1066 set_dma_ops(&dev->dev, pci_dma_ops);
1067 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
1069 /* Additional platform DMA/iommu setup */
1070 phb = pci_bus_to_host(dev->bus);
1071 if (phb->controller_ops.dma_dev_setup)
1072 phb->controller_ops.dma_dev_setup(dev);
1074 /* Read default IRQs and fixup if necessary */
1075 pci_read_irq_line(dev);
1076 if (ppc_md.pci_irq_fixup)
1077 ppc_md.pci_irq_fixup(dev);
1080 int pcibios_add_device(struct pci_dev *dev)
1083 * We can only call pcibios_setup_device() after bus setup is complete,
1084 * since some of the platform specific DMA setup code depends on it.
1086 if (dev->bus->is_added)
1087 pcibios_setup_device(dev);
1089 #ifdef CONFIG_PCI_IOV
1090 if (ppc_md.pcibios_fixup_sriov)
1091 ppc_md.pcibios_fixup_sriov(dev);
1092 #endif /* CONFIG_PCI_IOV */
1097 void pcibios_setup_bus_devices(struct pci_bus *bus)
1099 struct pci_dev *dev;
1101 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1102 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1104 list_for_each_entry(dev, &bus->devices, bus_list) {
1105 /* Cardbus can call us to add new devices to a bus, so ignore
1106 * those who are already fully discovered
1111 pcibios_setup_device(dev);
1115 void pcibios_set_master(struct pci_dev *dev)
1117 /* No special bus mastering setup handling */
1120 void pcibios_fixup_bus(struct pci_bus *bus)
1122 /* When called from the generic PCI probe, read PCI<->PCI bridge
1123 * bases. This is -not- called when generating the PCI tree from
1124 * the OF device-tree.
1126 pci_read_bridge_bases(bus);
1128 /* Now fixup the bus bus */
1129 pcibios_setup_bus_self(bus);
1131 /* Now fixup devices on that bus */
1132 pcibios_setup_bus_devices(bus);
1134 EXPORT_SYMBOL(pcibios_fixup_bus);
1136 void pci_fixup_cardbus(struct pci_bus *bus)
1138 /* Now fixup devices on that bus */
1139 pcibios_setup_bus_devices(bus);
1143 static int skip_isa_ioresource_align(struct pci_dev *dev)
1145 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1146 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1152 * We need to avoid collisions with `mirrored' VGA ports
1153 * and other strange ISA hardware, so we always want the
1154 * addresses to be allocated in the 0x000-0x0ff region
1157 * Why? Because some silly external IO cards only decode
1158 * the low 10 bits of the IO address. The 0x00-0xff region
1159 * is reserved for motherboard devices that decode all 16
1160 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1161 * but we want to try to avoid allocating at 0x2900-0x2bff
1162 * which might have be mirrored at 0x0100-0x03ff..
1164 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1165 resource_size_t size, resource_size_t align)
1167 struct pci_dev *dev = data;
1168 resource_size_t start = res->start;
1170 if (res->flags & IORESOURCE_IO) {
1171 if (skip_isa_ioresource_align(dev))
1174 start = (start + 0x3ff) & ~0x3ff;
1179 EXPORT_SYMBOL(pcibios_align_resource);
1182 * Reparent resource children of pr that conflict with res
1183 * under res, and make res replace those children.
1185 static int reparent_resources(struct resource *parent,
1186 struct resource *res)
1188 struct resource *p, **pp;
1189 struct resource **firstpp = NULL;
1191 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1192 if (p->end < res->start)
1194 if (res->end < p->start)
1196 if (p->start < res->start || p->end > res->end)
1197 return -1; /* not completely contained */
1198 if (firstpp == NULL)
1201 if (firstpp == NULL)
1202 return -1; /* didn't find any conflicting entries? */
1203 res->parent = parent;
1204 res->child = *firstpp;
1208 for (p = res->child; p != NULL; p = p->sibling) {
1210 pr_debug("PCI: Reparented %s %pR under %s\n",
1211 p->name, p, res->name);
1217 * Handle resources of PCI devices. If the world were perfect, we could
1218 * just allocate all the resource regions and do nothing more. It isn't.
1219 * On the other hand, we cannot just re-allocate all devices, as it would
1220 * require us to know lots of host bridge internals. So we attempt to
1221 * keep as much of the original configuration as possible, but tweak it
1222 * when it's found to be wrong.
1224 * Known BIOS problems we have to work around:
1225 * - I/O or memory regions not configured
1226 * - regions configured, but not enabled in the command register
1227 * - bogus I/O addresses above 64K used
1228 * - expansion ROMs left enabled (this may sound harmless, but given
1229 * the fact the PCI specs explicitly allow address decoders to be
1230 * shared between expansion ROMs and other resource regions, it's
1231 * at least dangerous)
1234 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1235 * This gives us fixed barriers on where we can allocate.
1236 * (2) Allocate resources for all enabled devices. If there is
1237 * a collision, just mark the resource as unallocated. Also
1238 * disable expansion ROMs during this step.
1239 * (3) Try to allocate resources for disabled devices. If the
1240 * resources were assigned correctly, everything goes well,
1241 * if they weren't, they won't disturb allocation of other
1243 * (4) Assign new addresses to resources which were either
1244 * not configured at all or misconfigured. If explicitly
1245 * requested by the user, configure expansion ROM address
1249 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1253 struct resource *res, *pr;
1255 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1256 pci_domain_nr(bus), bus->number);
1258 pci_bus_for_each_resource(bus, res, i) {
1259 if (!res || !res->flags || res->start > res->end || res->parent)
1262 /* If the resource was left unset at this point, we clear it */
1263 if (res->flags & IORESOURCE_UNSET)
1264 goto clear_resource;
1266 if (bus->parent == NULL)
1267 pr = (res->flags & IORESOURCE_IO) ?
1268 &ioport_resource : &iomem_resource;
1270 pr = pci_find_parent_resource(bus->self, res);
1272 /* this happens when the generic PCI
1273 * code (wrongly) decides that this
1274 * bridge is transparent -- paulus
1280 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1281 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1282 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1284 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1285 struct pci_dev *dev = bus->self;
1287 if (request_resource(pr, res) == 0)
1290 * Must be a conflict with an existing entry.
1291 * Move that entry (or entries) under the
1292 * bridge resource and try again.
1294 if (reparent_resources(pr, res) == 0)
1297 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1298 pci_claim_bridge_resource(dev,
1299 i + PCI_BRIDGE_RESOURCES) == 0)
1302 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n",
1305 /* The resource might be figured out when doing
1306 * reassignment based on the resources required
1307 * by the downstream PCI devices. Here we set
1308 * the size of the resource to be 0 in order to
1316 list_for_each_entry(b, &bus->children, node)
1317 pcibios_allocate_bus_resources(b);
1320 static inline void alloc_resource(struct pci_dev *dev, int idx)
1322 struct resource *pr, *r = &dev->resource[idx];
1324 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1325 pci_name(dev), idx, r);
1327 pr = pci_find_parent_resource(dev, r);
1328 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1329 request_resource(pr, r) < 0) {
1330 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1331 " of device %s, will remap\n", idx, pci_name(dev));
1333 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1334 /* We'll assign a new address later */
1335 r->flags |= IORESOURCE_UNSET;
1341 static void __init pcibios_allocate_resources(int pass)
1343 struct pci_dev *dev = NULL;
1348 for_each_pci_dev(dev) {
1349 pci_read_config_word(dev, PCI_COMMAND, &command);
1350 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1351 r = &dev->resource[idx];
1352 if (r->parent) /* Already allocated */
1354 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1355 continue; /* Not assigned at all */
1356 /* We only allocate ROMs on pass 1 just in case they
1357 * have been screwed up by firmware
1359 if (idx == PCI_ROM_RESOURCE )
1361 if (r->flags & IORESOURCE_IO)
1362 disabled = !(command & PCI_COMMAND_IO);
1364 disabled = !(command & PCI_COMMAND_MEMORY);
1365 if (pass == disabled)
1366 alloc_resource(dev, idx);
1370 r = &dev->resource[PCI_ROM_RESOURCE];
1372 /* Turn the ROM off, leave the resource region,
1373 * but keep it unregistered.
1376 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1377 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1378 pr_debug("PCI: Switching off ROM of %s\n",
1380 r->flags &= ~IORESOURCE_ROM_ENABLE;
1381 pci_write_config_dword(dev, dev->rom_base_reg,
1382 reg & ~PCI_ROM_ADDRESS_ENABLE);
1388 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1390 struct pci_controller *hose = pci_bus_to_host(bus);
1391 resource_size_t offset;
1392 struct resource *res, *pres;
1395 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1398 if (!(hose->io_resource.flags & IORESOURCE_IO))
1400 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1401 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1402 BUG_ON(res == NULL);
1403 res->name = "Legacy IO";
1404 res->flags = IORESOURCE_IO;
1405 res->start = offset;
1406 res->end = (offset + 0xfff) & 0xfffffffful;
1407 pr_debug("Candidate legacy IO: %pR\n", res);
1408 if (request_resource(&hose->io_resource, res)) {
1410 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1411 pci_domain_nr(bus), bus->number, res);
1416 /* Check for memory */
1417 for (i = 0; i < 3; i++) {
1418 pres = &hose->mem_resources[i];
1419 offset = hose->mem_offset[i];
1420 if (!(pres->flags & IORESOURCE_MEM))
1422 pr_debug("hose mem res: %pR\n", pres);
1423 if ((pres->start - offset) <= 0xa0000 &&
1424 (pres->end - offset) >= 0xbffff)
1429 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1430 BUG_ON(res == NULL);
1431 res->name = "Legacy VGA memory";
1432 res->flags = IORESOURCE_MEM;
1433 res->start = 0xa0000 + offset;
1434 res->end = 0xbffff + offset;
1435 pr_debug("Candidate VGA memory: %pR\n", res);
1436 if (request_resource(pres, res)) {
1438 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1439 pci_domain_nr(bus), bus->number, res);
1444 void __init pcibios_resource_survey(void)
1448 /* Allocate and assign resources */
1449 list_for_each_entry(b, &pci_root_buses, node)
1450 pcibios_allocate_bus_resources(b);
1451 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1452 pcibios_allocate_resources(0);
1453 pcibios_allocate_resources(1);
1456 /* Before we start assigning unassigned resource, we try to reserve
1457 * the low IO area and the VGA memory area if they intersect the
1458 * bus available resources to avoid allocating things on top of them
1460 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1461 list_for_each_entry(b, &pci_root_buses, node)
1462 pcibios_reserve_legacy_regions(b);
1465 /* Now, if the platform didn't decide to blindly trust the firmware,
1466 * we proceed to assigning things that were left unassigned
1468 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1469 pr_debug("PCI: Assigning unassigned resources...\n");
1470 pci_assign_unassigned_resources();
1473 /* Call machine dependent fixup */
1474 if (ppc_md.pcibios_fixup)
1475 ppc_md.pcibios_fixup();
1478 /* This is used by the PCI hotplug driver to allocate resource
1479 * of newly plugged busses. We can try to consolidate with the
1480 * rest of the code later, for now, keep it as-is as our main
1481 * resource allocation function doesn't deal with sub-trees yet.
1483 void pcibios_claim_one_bus(struct pci_bus *bus)
1485 struct pci_dev *dev;
1486 struct pci_bus *child_bus;
1488 list_for_each_entry(dev, &bus->devices, bus_list) {
1491 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1492 struct resource *r = &dev->resource[i];
1494 if (r->parent || !r->start || !r->flags)
1497 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1498 pci_name(dev), i, r);
1500 if (pci_claim_resource(dev, i) == 0)
1503 pci_claim_bridge_resource(dev, i);
1507 list_for_each_entry(child_bus, &bus->children, node)
1508 pcibios_claim_one_bus(child_bus);
1510 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1513 /* pcibios_finish_adding_to_bus
1515 * This is to be called by the hotplug code after devices have been
1516 * added to a bus, this include calling it for a PHB that is just
1519 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1521 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1522 pci_domain_nr(bus), bus->number);
1524 /* Allocate bus and devices resources */
1525 pcibios_allocate_bus_resources(bus);
1526 pcibios_claim_one_bus(bus);
1527 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1529 pci_assign_unassigned_bridge_resources(bus->self);
1531 pci_assign_unassigned_bus_resources(bus);
1535 eeh_add_device_tree_late(bus);
1537 /* Add new devices to global lists. Register in proc, sysfs. */
1538 pci_bus_add_devices(bus);
1540 /* sysfs files should only be added after devices are added */
1541 eeh_add_sysfs_files(bus);
1543 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1545 int pcibios_enable_device(struct pci_dev *dev, int mask)
1547 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1549 if (phb->controller_ops.enable_device_hook)
1550 if (!phb->controller_ops.enable_device_hook(dev))
1553 return pci_enable_resources(dev, mask);
1556 void pcibios_disable_device(struct pci_dev *dev)
1558 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1560 if (phb->controller_ops.disable_device)
1561 phb->controller_ops.disable_device(dev);
1564 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1566 return (unsigned long) hose->io_base_virt - _IO_BASE;
1569 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1570 struct list_head *resources)
1572 struct resource *res;
1573 resource_size_t offset;
1576 /* Hookup PHB IO resource */
1577 res = &hose->io_resource;
1580 pr_debug("PCI: I/O resource not set for host"
1581 " bridge %pOF (domain %d)\n",
1582 hose->dn, hose->global_number);
1584 offset = pcibios_io_space_offset(hose);
1586 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1587 res, (unsigned long long)offset);
1588 pci_add_resource_offset(resources, res, offset);
1591 /* Hookup PHB Memory resources */
1592 for (i = 0; i < 3; ++i) {
1593 res = &hose->mem_resources[i];
1597 offset = hose->mem_offset[i];
1598 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1599 res, (unsigned long long)offset);
1601 pci_add_resource_offset(resources, res, offset);
1606 * Null PCI config access functions, for the case when we can't
1609 #define NULL_PCI_OP(rw, size, type) \
1611 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1613 return PCIBIOS_DEVICE_NOT_FOUND; \
1617 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1620 return PCIBIOS_DEVICE_NOT_FOUND;
1624 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1627 return PCIBIOS_DEVICE_NOT_FOUND;
1630 static struct pci_ops null_pci_ops =
1632 .read = null_read_config,
1633 .write = null_write_config,
1637 * These functions are used early on before PCI scanning is done
1638 * and all of the pci_dev and pci_bus structures have been created.
1640 static struct pci_bus *
1641 fake_pci_bus(struct pci_controller *hose, int busnr)
1643 static struct pci_bus bus;
1646 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1650 bus.ops = hose? hose->ops: &null_pci_ops;
1654 #define EARLY_PCI_OP(rw, size, type) \
1655 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1656 int devfn, int offset, type value) \
1658 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1659 devfn, offset, value); \
1662 EARLY_PCI_OP(read, byte, u8 *)
1663 EARLY_PCI_OP(read, word, u16 *)
1664 EARLY_PCI_OP(read, dword, u32 *)
1665 EARLY_PCI_OP(write, byte, u8)
1666 EARLY_PCI_OP(write, word, u16)
1667 EARLY_PCI_OP(write, dword, u32)
1669 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1672 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1675 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1677 struct pci_controller *hose = bus->sysdata;
1679 return of_node_get(hose->dn);
1683 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1684 * @hose: Pointer to the PCI host controller instance structure
1686 void pcibios_scan_phb(struct pci_controller *hose)
1688 LIST_HEAD(resources);
1689 struct pci_bus *bus;
1690 struct device_node *node = hose->dn;
1693 pr_debug("PCI: Scanning PHB %pOF\n", node);
1695 /* Get some IO space for the new PHB */
1696 pcibios_setup_phb_io_space(hose);
1698 /* Wire up PHB bus resources */
1699 pcibios_setup_phb_resources(hose, &resources);
1701 hose->busn.start = hose->first_busno;
1702 hose->busn.end = hose->last_busno;
1703 hose->busn.flags = IORESOURCE_BUS;
1704 pci_add_resource(&resources, &hose->busn);
1706 /* Create an empty bus for the toplevel */
1707 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1708 hose->ops, hose, &resources);
1710 pr_err("Failed to create bus for PCI domain %04x\n",
1711 hose->global_number);
1712 pci_free_resource_list(&resources);
1717 /* Get probe mode and perform scan */
1718 mode = PCI_PROBE_NORMAL;
1719 if (node && hose->controller_ops.probe_mode)
1720 mode = hose->controller_ops.probe_mode(bus);
1721 pr_debug(" probe mode: %d\n", mode);
1722 if (mode == PCI_PROBE_DEVTREE)
1723 of_scan_bus(node, bus);
1725 if (mode == PCI_PROBE_NORMAL) {
1726 pci_bus_update_busn_res_end(bus, 255);
1727 hose->last_busno = pci_scan_child_bus(bus);
1728 pci_bus_update_busn_res_end(bus, hose->last_busno);
1731 /* Platform gets a chance to do some global fixups before
1732 * we proceed to resource allocation
1734 if (ppc_md.pcibios_fixup_phb)
1735 ppc_md.pcibios_fixup_phb(hose);
1737 /* Configure PCI Express settings */
1738 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1739 struct pci_bus *child;
1740 list_for_each_entry(child, &bus->children, node)
1741 pcie_bus_configure_settings(child);
1744 EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1746 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1748 int i, class = dev->class >> 8;
1749 /* When configured as agent, programing interface = 1 */
1750 int prog_if = dev->class & 0xf;
1752 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1753 class == PCI_CLASS_BRIDGE_OTHER) &&
1754 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1756 (dev->bus->parent == NULL)) {
1757 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1758 dev->resource[i].start = 0;
1759 dev->resource[i].end = 0;
1760 dev->resource[i].flags = 0;
1764 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1765 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);