2 * Machine check exception handling CPU-side for power7 and power8
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * Copyright 2013 IBM Corporation
19 * Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
23 #define pr_fmt(fmt) "mce_power: " fmt
25 #include <linux/types.h>
26 #include <linux/ptrace.h>
29 #include <asm/machdep.h>
30 #include <asm/pgtable.h>
31 #include <asm/pte-walk.h>
32 #include <asm/sstep.h>
33 #include <asm/exception-64s.h>
36 * Convert an address related to an mm to a PFN. NOTE: we are in real
37 * mode, we could potentially race with page table updates.
39 unsigned long addr_to_pfn(struct pt_regs *regs, unsigned long addr)
50 local_irq_save(flags);
51 if (mm == current->mm)
52 ptep = find_current_mm_pte(mm->pgd, addr, NULL, NULL);
54 ptep = find_init_mm_pte(addr, NULL);
55 local_irq_restore(flags);
56 if (!ptep || pte_special(*ptep))
58 return pte_pfn(*ptep);
61 /* flush SLBs and reload */
62 #ifdef CONFIG_PPC_BOOK3S_64
63 void flush_and_reload_slb(void)
65 /* Invalidate all SLBs */
66 slb_flush_all_realmode();
68 #ifdef CONFIG_KVM_BOOK3S_HANDLER
70 * If machine check is hit when in guest or in transition, we will
71 * only flush the SLBs and continue.
73 if (get_paca()->kvm_hstate.in_guest)
76 if (early_radix_enabled())
80 * This probably shouldn't happen, but it may be possible it's
81 * called in early boot before SLB shadows are allocated.
83 if (!get_slb_shadow())
86 slb_restore_bolted_realmode();
90 static void flush_erat(void)
92 #ifdef CONFIG_PPC_BOOK3S_64
93 if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) {
94 flush_and_reload_slb();
98 asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT : : :"memory");
101 #define MCE_FLUSH_SLB 1
102 #define MCE_FLUSH_TLB 2
103 #define MCE_FLUSH_ERAT 3
105 static int mce_flush(int what)
107 #ifdef CONFIG_PPC_BOOK3S_64
108 if (what == MCE_FLUSH_SLB) {
109 flush_and_reload_slb();
113 if (what == MCE_FLUSH_ERAT) {
117 if (what == MCE_FLUSH_TLB) {
125 #define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42))
127 struct mce_ierror_table {
128 unsigned long srr1_mask;
129 unsigned long srr1_value;
130 bool nip_valid; /* nip is a valid indicator of faulting address */
131 unsigned int error_type;
132 unsigned int error_subtype;
133 unsigned int error_class;
134 unsigned int initiator;
135 unsigned int severity;
139 static const struct mce_ierror_table mce_p7_ierror_table[] = {
140 { 0x00000000001c0000, 0x0000000000040000, true,
141 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
142 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
143 { 0x00000000001c0000, 0x0000000000080000, true,
144 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
145 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
146 { 0x00000000001c0000, 0x00000000000c0000, true,
147 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
148 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
149 { 0x00000000001c0000, 0x0000000000100000, true,
150 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */
151 MCE_ECLASS_SOFT_INDETERMINATE,
152 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
153 { 0x00000000001c0000, 0x0000000000140000, true,
154 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
155 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
156 { 0x00000000001c0000, 0x0000000000180000, true,
157 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_HARDWARE,
158 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
159 { 0x00000000001c0000, 0x00000000001c0000, true,
160 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
161 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
162 { 0, 0, 0, 0, 0, 0, 0 } };
164 static const struct mce_ierror_table mce_p8_ierror_table[] = {
165 { 0x00000000081c0000, 0x0000000000040000, true,
166 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
167 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
168 { 0x00000000081c0000, 0x0000000000080000, true,
169 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
170 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
171 { 0x00000000081c0000, 0x00000000000c0000, true,
172 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
173 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
174 { 0x00000000081c0000, 0x0000000000100000, true,
175 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
176 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
177 { 0x00000000081c0000, 0x0000000000140000, true,
178 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
179 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
180 { 0x00000000081c0000, 0x0000000000180000, true,
181 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH,
183 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
184 { 0x00000000081c0000, 0x00000000001c0000, true,
185 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
186 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
187 { 0x00000000081c0000, 0x0000000008000000, true,
188 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_IFETCH_TIMEOUT, MCE_ECLASS_HARDWARE,
189 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
190 { 0x00000000081c0000, 0x0000000008040000, true,
191 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT,
193 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
194 { 0, 0, 0, 0, 0, 0, 0 } };
196 static const struct mce_ierror_table mce_p9_ierror_table[] = {
197 { 0x00000000081c0000, 0x0000000000040000, true,
198 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
199 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
200 { 0x00000000081c0000, 0x0000000000080000, true,
201 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
202 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
203 { 0x00000000081c0000, 0x00000000000c0000, true,
204 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
205 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
206 { 0x00000000081c0000, 0x0000000000100000, true,
207 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
208 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
209 { 0x00000000081c0000, 0x0000000000140000, true,
210 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
211 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
212 { 0x00000000081c0000, 0x0000000000180000, true,
213 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_HARDWARE,
214 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
215 { 0x00000000081c0000, 0x00000000001c0000, true,
216 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH_FOREIGN, MCE_ECLASS_SOFTWARE,
217 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
218 { 0x00000000081c0000, 0x0000000008000000, true,
219 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_IFETCH_TIMEOUT, MCE_ECLASS_HARDWARE,
220 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
221 { 0x00000000081c0000, 0x0000000008040000, true,
222 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT,
224 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
225 { 0x00000000081c0000, 0x00000000080c0000, true,
226 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH, MCE_ECLASS_SOFTWARE,
227 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
228 { 0x00000000081c0000, 0x0000000008100000, true,
229 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_SOFTWARE,
230 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
231 { 0x00000000081c0000, 0x0000000008140000, false,
232 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_STORE, MCE_ECLASS_HARDWARE,
233 MCE_INITIATOR_CPU, MCE_SEV_FATAL, false }, /* ASYNC is fatal */
234 { 0x00000000081c0000, 0x0000000008180000, false,
235 MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_STORE_TIMEOUT,
236 MCE_INITIATOR_CPU, MCE_SEV_FATAL, false }, /* ASYNC is fatal */
237 { 0x00000000081c0000, 0x00000000081c0000, true, MCE_ECLASS_HARDWARE,
238 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN,
239 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
240 { 0, 0, 0, 0, 0, 0, 0 } };
242 struct mce_derror_table {
243 unsigned long dsisr_value;
244 bool dar_valid; /* dar is a valid indicator of faulting address */
245 unsigned int error_type;
246 unsigned int error_subtype;
247 unsigned int error_class;
248 unsigned int initiator;
249 unsigned int severity;
253 static const struct mce_derror_table mce_p7_derror_table[] = {
255 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE,
256 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
258 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
260 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
262 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
263 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
265 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
266 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
268 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
269 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
271 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
272 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
274 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */
275 MCE_ECLASS_HARD_INDETERMINATE,
276 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
277 { 0, false, 0, 0, 0, 0, 0 } };
279 static const struct mce_derror_table mce_p8_derror_table[] = {
281 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE,
282 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
284 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
286 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
288 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT, MCE_ECLASS_HARDWARE,
289 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
291 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT,
293 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
295 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
296 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
298 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
299 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
301 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, /* SECONDARY ERAT */
302 MCE_ECLASS_SOFT_INDETERMINATE,
303 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
305 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, /* Before PARITY */
306 MCE_ECLASS_SOFT_INDETERMINATE,
307 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
309 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
310 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
311 { 0, false, 0, 0, 0, 0, 0 } };
313 static const struct mce_derror_table mce_p9_derror_table[] = {
315 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE,
316 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
318 MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
320 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
322 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT, MCE_ECLASS_HARDWARE,
323 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
325 MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT,
327 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
329 MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
330 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
332 MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
333 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
335 MCE_ERROR_TYPE_USER, MCE_USER_ERROR_TLBIE, MCE_ECLASS_SOFTWARE,
336 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
338 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, /* Before PARITY */
339 MCE_ECLASS_SOFT_INDETERMINATE,
340 MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
342 MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
343 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
345 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD, MCE_ECLASS_HARDWARE,
346 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
348 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
350 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
352 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN,
354 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
356 MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD_STORE_FOREIGN, MCE_ECLASS_HARDWARE,
357 MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
358 { 0, false, 0, 0, 0, 0, 0 } };
360 static int mce_find_instr_ea_and_pfn(struct pt_regs *regs, uint64_t *addr,
364 * Carefully look at the NIP to determine
365 * the instruction to analyse. Reading the NIP
366 * in real-mode is tricky and can lead to recursive
370 unsigned long pfn, instr_addr;
371 struct instruction_op op;
372 struct pt_regs tmp = *regs;
374 pfn = addr_to_pfn(regs, regs->nip);
375 if (pfn != ULONG_MAX) {
376 instr_addr = (pfn << PAGE_SHIFT) + (regs->nip & ~PAGE_MASK);
377 instr = *(unsigned int *)(instr_addr);
378 if (!analyse_instr(&op, &tmp, instr)) {
379 pfn = addr_to_pfn(regs, op.ea);
381 *phys_addr = (pfn << PAGE_SHIFT);
385 * analyse_instr() might fail if the instruction
386 * is not a load/store, although this is unexpected
387 * for load/store errors or if we got the NIP
395 static int mce_handle_ierror(struct pt_regs *regs,
396 const struct mce_ierror_table table[],
397 struct mce_error_info *mce_err, uint64_t *addr,
400 uint64_t srr1 = regs->msr;
406 for (i = 0; table[i].srr1_mask; i++) {
407 if ((srr1 & table[i].srr1_mask) != table[i].srr1_value)
410 /* attempt to correct the error */
411 switch (table[i].error_type) {
412 case MCE_ERROR_TYPE_SLB:
413 handled = mce_flush(MCE_FLUSH_SLB);
415 case MCE_ERROR_TYPE_ERAT:
416 handled = mce_flush(MCE_FLUSH_ERAT);
418 case MCE_ERROR_TYPE_TLB:
419 handled = mce_flush(MCE_FLUSH_TLB);
423 /* now fill in mce_error_info */
424 mce_err->error_type = table[i].error_type;
425 mce_err->error_class = table[i].error_class;
426 switch (table[i].error_type) {
427 case MCE_ERROR_TYPE_UE:
428 mce_err->u.ue_error_type = table[i].error_subtype;
430 case MCE_ERROR_TYPE_SLB:
431 mce_err->u.slb_error_type = table[i].error_subtype;
433 case MCE_ERROR_TYPE_ERAT:
434 mce_err->u.erat_error_type = table[i].error_subtype;
436 case MCE_ERROR_TYPE_TLB:
437 mce_err->u.tlb_error_type = table[i].error_subtype;
439 case MCE_ERROR_TYPE_USER:
440 mce_err->u.user_error_type = table[i].error_subtype;
442 case MCE_ERROR_TYPE_RA:
443 mce_err->u.ra_error_type = table[i].error_subtype;
445 case MCE_ERROR_TYPE_LINK:
446 mce_err->u.link_error_type = table[i].error_subtype;
449 mce_err->sync_error = table[i].sync_error;
450 mce_err->severity = table[i].severity;
451 mce_err->initiator = table[i].initiator;
452 if (table[i].nip_valid) {
454 if (mce_err->sync_error &&
455 table[i].error_type == MCE_ERROR_TYPE_UE) {
458 if (get_paca()->in_mce < MAX_MCE_DEPTH) {
459 pfn = addr_to_pfn(regs, regs->nip);
460 if (pfn != ULONG_MAX) {
470 mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN;
471 mce_err->error_class = MCE_ECLASS_UNKNOWN;
472 mce_err->severity = MCE_SEV_SEVERE;
473 mce_err->initiator = MCE_INITIATOR_CPU;
474 mce_err->sync_error = true;
479 static int mce_handle_derror(struct pt_regs *regs,
480 const struct mce_derror_table table[],
481 struct mce_error_info *mce_err, uint64_t *addr,
484 uint64_t dsisr = regs->dsisr;
491 for (i = 0; table[i].dsisr_value; i++) {
492 if (!(dsisr & table[i].dsisr_value))
495 /* attempt to correct the error */
496 switch (table[i].error_type) {
497 case MCE_ERROR_TYPE_SLB:
498 if (mce_flush(MCE_FLUSH_SLB))
501 case MCE_ERROR_TYPE_ERAT:
502 if (mce_flush(MCE_FLUSH_ERAT))
505 case MCE_ERROR_TYPE_TLB:
506 if (mce_flush(MCE_FLUSH_TLB))
512 * Attempt to handle multiple conditions, but only return
513 * one. Ensure uncorrectable errors are first in the table
519 /* now fill in mce_error_info */
520 mce_err->error_type = table[i].error_type;
521 mce_err->error_class = table[i].error_class;
522 switch (table[i].error_type) {
523 case MCE_ERROR_TYPE_UE:
524 mce_err->u.ue_error_type = table[i].error_subtype;
526 case MCE_ERROR_TYPE_SLB:
527 mce_err->u.slb_error_type = table[i].error_subtype;
529 case MCE_ERROR_TYPE_ERAT:
530 mce_err->u.erat_error_type = table[i].error_subtype;
532 case MCE_ERROR_TYPE_TLB:
533 mce_err->u.tlb_error_type = table[i].error_subtype;
535 case MCE_ERROR_TYPE_USER:
536 mce_err->u.user_error_type = table[i].error_subtype;
538 case MCE_ERROR_TYPE_RA:
539 mce_err->u.ra_error_type = table[i].error_subtype;
541 case MCE_ERROR_TYPE_LINK:
542 mce_err->u.link_error_type = table[i].error_subtype;
545 mce_err->sync_error = table[i].sync_error;
546 mce_err->severity = table[i].severity;
547 mce_err->initiator = table[i].initiator;
548 if (table[i].dar_valid)
550 else if (mce_err->sync_error &&
551 table[i].error_type == MCE_ERROR_TYPE_UE) {
553 * We do a maximum of 4 nested MCE calls, see
554 * kernel/exception-64s.h
556 if (get_paca()->in_mce < MAX_MCE_DEPTH)
557 mce_find_instr_ea_and_pfn(regs, addr, phys_addr);
565 mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN;
566 mce_err->error_class = MCE_ECLASS_UNKNOWN;
567 mce_err->severity = MCE_SEV_SEVERE;
568 mce_err->initiator = MCE_INITIATOR_CPU;
569 mce_err->sync_error = true;
574 static long mce_handle_ue_error(struct pt_regs *regs)
579 * On specific SCOM read via MMIO we may get a machine check
580 * exception with SRR0 pointing inside opal. If that is the
581 * case OPAL may have recovery address to re-read SCOM data in
582 * different way and hence we can recover from this MC.
585 if (ppc_md.mce_check_early_recovery) {
586 if (ppc_md.mce_check_early_recovery(regs))
592 static long mce_handle_error(struct pt_regs *regs,
593 const struct mce_derror_table dtable[],
594 const struct mce_ierror_table itable[])
596 struct mce_error_info mce_err = { 0 };
597 uint64_t addr, phys_addr = ULONG_MAX;
598 uint64_t srr1 = regs->msr;
601 if (SRR1_MC_LOADSTORE(srr1))
602 handled = mce_handle_derror(regs, dtable, &mce_err, &addr,
605 handled = mce_handle_ierror(regs, itable, &mce_err, &addr,
608 if (!handled && mce_err.error_type == MCE_ERROR_TYPE_UE)
609 handled = mce_handle_ue_error(regs);
611 save_mce_event(regs, handled, &mce_err, regs->nip, addr, phys_addr);
616 long __machine_check_early_realmode_p7(struct pt_regs *regs)
618 /* P7 DD1 leaves top bits of DSISR undefined */
619 regs->dsisr &= 0x0000ffff;
621 return mce_handle_error(regs, mce_p7_derror_table, mce_p7_ierror_table);
624 long __machine_check_early_realmode_p8(struct pt_regs *regs)
626 return mce_handle_error(regs, mce_p8_derror_table, mce_p8_ierror_table);
629 long __machine_check_early_realmode_p9(struct pt_regs *regs)
632 * On POWER9 DD2.1 and below, it's possible to get a machine check
633 * caused by a paste instruction where only DSISR bit 25 is set. This
634 * will result in the MCE handler seeing an unknown event and the kernel
635 * crashing. An MCE that occurs like this is spurious, so we don't need
636 * to do anything in terms of servicing it. If there is something that
637 * needs to be serviced, the CPU will raise the MCE again with the
638 * correct DSISR so that it can be serviced properly. So detect this
639 * case and mark it as handled.
641 if (SRR1_MC_LOADSTORE(regs->msr) && regs->dsisr == 0x02000000)
644 return mce_handle_error(regs, mce_p9_derror_table, mce_p9_ierror_table);