2 * This file contains idle entry/exit functions for POWER7,
3 * POWER8 and POWER9 CPUs.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
11 #include <linux/threads.h>
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/thread_info.h>
16 #include <asm/ppc_asm.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/ppc-opcode.h>
19 #include <asm/hw_irq.h>
20 #include <asm/kvm_book3s_asm.h>
22 #include <asm/cpuidle.h>
23 #include <asm/book3s/64/mmu-hash.h>
29 * Use unused space in the interrupt stack to save and restore
30 * registers for winkle support.
43 #define PSSCR_HV_TEMPLATE PSSCR_ESL | PSSCR_EC | \
44 PSSCR_PSLL_MASK | PSSCR_TR_MASK | \
47 /* Idle state entry routines */
49 #define IDLE_STATE_ENTER_SEQ(IDLE_INST) \
50 /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \
62 * Used by threads before entering deep idle states. Saves SPRs
63 * in interrupt stack frame
67 * Note all register i.e per-core, per-subcore or per-thread is saved
68 * here since any thread in the core might wake up first
74 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
80 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
101 * Used by threads when the lock bit of core_idle_state is set.
102 * Threads will spin in HMT_LOW until the lock bit is cleared.
103 * r14 - pointer to core_idle_state
104 * r15 - used to load contents of core_idle_state
110 andi. r15,r15,PNV_CORE_IDLE_LOCK_BIT
117 * Pass requested state in r3:
118 * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
119 * - Requested STOP state in POWER9
121 * To check IRQ_HAPPENED in r4
125 * Address to 'rfid' to in r5
127 _GLOBAL(pnv_powersave_common)
128 /* Use r3 to pass state nap/sleep/winkle */
129 /* NAP is a state loss, we create a regs frame on the
130 * stack, fill it up with the state we care about and
131 * stick a pointer to it in PACAR1. We really only
132 * need to save PC, some CR bits and the NV GPRs,
133 * but for now an interrupt frame will do.
137 stdu r1,-INT_FRAME_SIZE(r1)
141 /* Hard disable interrupts */
145 mtmsrd r9,1 /* hard-disable interrupts */
147 /* Check if something happened while soft-disabled */
148 lbz r0,PACAIRQHAPPENED(r13)
149 andi. r0,r0,~PACA_IRQ_HARD_DIS@l
153 addi r1,r1,INT_FRAME_SIZE
155 li r3,0 /* Return 0 (no nap) */
159 1: /* We mark irqs hard disabled as this is the state we'll
160 * be in when returning and we need to tell arch_local_irq_restore()
163 li r0,PACA_IRQ_HARD_DIS
164 stb r0,PACAIRQHAPPENED(r13)
166 /* We haven't lost state ... yet */
168 stb r0,PACA_NAPSTATELOST(r13)
170 /* Continue saving state */
178 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
179 /* Tell KVM we're entering idle */
180 li r4,KVM_HWTHREAD_IN_IDLE
181 stb r4,HSTATE_HWTHREAD_STATE(r13)
185 * Go to real mode to do the nap, as required by the architecture.
186 * Also, we need to be in real mode before setting hwthread_state,
187 * because as soon as we do that, another thread can switch
188 * the MMU context to the guest.
190 LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
193 mtmsrd r6, 1 /* clear RI before setting SRR0/1 */
198 .globl pnv_enter_arch207_idle_mode
199 pnv_enter_arch207_idle_mode:
200 stb r3,PACA_THREAD_IDLE_STATE(r13)
201 cmpwi cr3,r3,PNV_THREAD_SLEEP
203 IDLE_STATE_ENTER_SEQ(PPC_NAP)
206 /* Sleep or winkle */
207 lbz r7,PACA_THREAD_MASK(r13)
208 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
212 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
213 bnel core_idle_lock_held
215 andc r15,r15,r7 /* Clear thread bit */
217 andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
220 * If cr0 = 0, then current thread is the last thread of the core entering
221 * sleep. Last thread needs to execute the hardware bug workaround code if
222 * required by the platform.
223 * Make the workaround call unconditionally here. The below branch call is
224 * patched out when the idle states are discovered if the platform does not
227 .global pnv_fastsleep_workaround_at_entry
228 pnv_fastsleep_workaround_at_entry:
229 beq fastsleep_workaround_at_entry
235 common_enter: /* common code for all the threads entering sleep or winkle */
237 IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
239 fastsleep_workaround_at_entry:
240 ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
245 /* Fast sleep workaround */
248 bl opal_rm_config_cpu_idle_state
257 bl save_sprs_to_stack
259 IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
262 * r3 - requested stop state
266 * Check if the requested state is a deep idle state.
268 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
269 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
272 IDLE_STATE_ENTER_SEQ(PPC_STOP)
275 * Entering deep idle state.
276 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
277 * stack and enter stop
279 lbz r7,PACA_THREAD_MASK(r13)
280 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
284 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
285 bnel core_idle_lock_held
286 andc r15,r15,r7 /* Clear thread bit */
292 bl save_sprs_to_stack
294 IDLE_STATE_ENTER_SEQ(PPC_STOP)
297 /* Now check if user or arch enabled NAP mode */
298 LOAD_REG_ADDRBASE(r3,powersave_nap)
299 lwz r4,ADDROFF(powersave_nap)(r3)
308 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
309 b pnv_powersave_common
312 _GLOBAL(power7_sleep)
313 li r3,PNV_THREAD_SLEEP
315 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
316 b pnv_powersave_common
319 _GLOBAL(power7_winkle)
320 li r3,PNV_THREAD_WINKLE
322 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
323 b pnv_powersave_common
326 #define CHECK_HMI_INTERRUPT \
327 mfspr r0,SPRN_SRR1; \
328 BEGIN_FTR_SECTION_NESTED(66); \
329 rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
330 FTR_SECTION_ELSE_NESTED(66); \
331 rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
332 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
333 cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
335 /* Invoke opal call to handle hmi */ \
336 ld r2,PACATOC(r13); \
338 std r3,ORIG_GPR3(r1); /* Save original r3 */ \
339 li r3,0; /* NULL argument */ \
340 bl hmi_exception_realmode; \
342 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
347 * r3 - requested stop state
349 _GLOBAL(power9_idle_stop)
350 LOAD_REG_IMMEDIATE(r4, PSSCR_HV_TEMPLATE)
354 LOAD_REG_ADDR(r5,power_enter_stop)
355 b pnv_powersave_common
358 * Called from reset vector. Check whether we have woken up with
359 * hypervisor state loss. If yes, restore hypervisor state and return
360 * back to reset vector.
362 * r13 - Contents of HSPRG0
363 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
365 _GLOBAL(pnv_restore_hyp_resource)
369 * POWER ISA 3. Use PSSCR to determine if we
370 * are waking up from deep idle state
372 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
373 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
377 * 0-3 bits correspond to Power-Saving Level Status
378 * which indicates the idle state we are waking up from
382 bge cr4,pnv_wakeup_tb_loss
384 * Waking up without hypervisor state loss. Return to
389 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
392 * POWER ISA 2.07 or less.
393 * Check if last bit of HSPGR0 is set. This indicates whether we are
394 * waking up from winkle.
399 mtspr SPRN_HSPRG0,r13
401 lbz r0,PACA_THREAD_IDLE_STATE(r13)
402 cmpwi cr2,r0,PNV_THREAD_NAP
403 bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
406 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
407 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
408 * indicates we are waking with hypervisor state loss from nap.
412 blr /* Return back to System Reset vector from where
413 pnv_restore_hyp_resource was invoked */
416 * Called if waking up from idle state which can cause either partial or
417 * complete hyp state loss.
418 * In POWER8, called if waking up from fastsleep or winkle
419 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
422 * cr3 - gt if waking up with partial/complete hypervisor state loss
423 * cr4 - eq if waking up from complete hypervisor state loss.
425 _GLOBAL(pnv_wakeup_tb_loss)
428 * Before entering any idle state, the NVGPRs are saved in the stack
429 * and they are restored before switching to the process context. Hence
430 * until they are restored, they are free to be used.
432 * Save SRR1 and LR in NVGPRs as they might be clobbered in
433 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
434 * to determine the wakeup reason if we branch to kvm_start_guest. LR
435 * is required to return back to reset vector after hypervisor state
436 * restore is complete.
442 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
444 lbz r7,PACA_THREAD_MASK(r13)
445 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
448 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
450 * Lock bit is set in one of the 2 cases-
451 * a. In the sleep/winkle enter path, the last thread is executing
452 * fastsleep workaround code.
453 * b. In the wake up path, another thread is executing fastsleep
454 * workaround undo code or resyncing timebase or restoring context
455 * In either case loop until the lock bit is cleared.
457 bnel core_idle_lock_held
463 * cr2 - eq if first thread to wakeup in core
464 * cr3- gt if waking up with partial/complete hypervisor state loss
465 * cr4 - eq if waking up from complete hypervisor state loss.
468 ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
474 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
476 cmpwi r4,0 /* Check if first in subcore */
478 or r15,r15,r7 /* Set thread bit */
479 beq first_thread_in_subcore
480 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
482 or r15,r15,r7 /* Set thread bit */
483 beq cr2,first_thread_in_core
485 /* Not first thread in core or subcore to wake up */
488 first_thread_in_subcore:
490 * If waking up from sleep, subcore state is not lost. Hence
491 * skip subcore state restore
493 bne cr4,subcore_state_restored
495 /* Restore per-subcore state */
504 subcore_state_restored:
506 * Check if the thread is also the first thread in the core. If not,
507 * skip to clear_lock.
511 first_thread_in_core:
514 * First thread in the core waking up from any state which can cause
515 * partial or complete hypervisor state loss. It needs to
516 * call the fastsleep workaround code if the platform requires it.
517 * Call it unconditionally here. The below branch instruction will
518 * be patched out if the platform does not have fastsleep or does not
519 * require the workaround. Patching will be performed during the
520 * discovery of idle-states.
522 .global pnv_fastsleep_workaround_at_exit
523 pnv_fastsleep_workaround_at_exit:
524 b fastsleep_workaround_at_exit
528 * Use cr3 which indicates that we are waking up with atleast partial
529 * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
532 /* Time base re-sync */
533 bl opal_rm_resync_timebase;
535 * If waking up from sleep, per core state is not lost, skip to
541 * First thread in the core to wake up and its waking up with
542 * complete hypervisor state loss. Restore per core hypervisor
550 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
558 andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
564 * Common to all threads.
566 * If waking up from sleep, hypervisor state is not lost. Hence
567 * skip hypervisor state restore.
569 bne cr4,hypervisor_state_restored
571 /* Waking up from winkle */
573 BEGIN_MMU_FTR_SECTION
575 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
576 /* Restore SLB from PACA */
577 ld r8,PACA_SLBSHADOWPTR(r13)
580 li r3, SLBSHADOW_SAVEAREA
584 andis. r7,r5,SLB_ESID_V@h
591 /* Restore per thread state */
602 /* Call cur_cpu_spec->cpu_restore() */
603 LOAD_REG_ADDR(r4, cur_cpu_spec)
605 ld r12,CPU_SPEC_RESTORE(r4)
606 #ifdef PPC64_ELF_ABI_v1
612 hypervisor_state_restored:
616 blr /* Return back to System Reset vector from where
617 pnv_restore_hyp_resource was invoked */
619 fastsleep_workaround_at_exit:
622 bl opal_rm_config_cpu_idle_state
626 * R3 here contains the value that will be returned to the caller
629 _GLOBAL(pnv_wakeup_loss)
633 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
639 addi r1,r1,INT_FRAME_SIZE
646 * R3 here contains the value that will be returned to the caller
649 _GLOBAL(pnv_wakeup_noloss)
650 lbz r0,PACA_NAPSTATELOST(r13)
655 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
660 addi r1,r1,INT_FRAME_SIZE