2 * Kernel execution entry point code.
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 * Low-level exception handers, MMU support, and rewrite.
10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 * PowerPC 8xx modifications.
12 * Copyright (c) 1998-1999 TiVo, Inc.
13 * PowerPC 403GCX modifications.
14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 * PowerPC 403GCX/405GP modifications.
16 * Copyright 2000 MontaVista Software Inc.
17 * PPC405 modifications
18 * PowerPC 403GCX/405GP modifications.
19 * Author: MontaVista Software, Inc.
20 * frank_rowand@mvista.com or source@mvista.com
21 * debbie_chu@mvista.com
22 * Copyright 2002-2004 MontaVista Software, Inc.
23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 * Copyright 2004 Freescale Semiconductor, Inc
25 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License as published by the
29 * Free Software Foundation; either version 2 of the License, or (at your
30 * option) any later version.
33 #include <linux/init.h>
34 #include <linux/threads.h>
35 #include <asm/processor.h>
38 #include <asm/pgtable.h>
39 #include <asm/cputable.h>
40 #include <asm/thread_info.h>
41 #include <asm/ppc_asm.h>
42 #include <asm/asm-offsets.h>
43 #include <asm/cache.h>
44 #include <asm/ptrace.h>
45 #include <asm/export.h>
46 #include <asm/feature-fixups.h>
47 #include "head_booke.h"
49 /* As with the other PowerPC ports, it is expected that when code
50 * execution begins here, the following registers contain valid, yet
51 * optional, information:
53 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
54 * r4 - Starting address of the init RAM disk
55 * r5 - Ending address of the init RAM disk
56 * r6 - Start of kernel command line string (e.g. "mem=128")
57 * r7 - End of kernel command line string
64 * Reserve a word at a fixed location to store the address
69 /* Translate device tree address to physical, save in r30/r31 */
74 li r25,0 /* phys kernel start (low) */
75 li r24,0 /* CPU number */
76 li r23,0 /* phys kernel start (high) */
78 #ifdef CONFIG_RELOCATABLE
79 LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */
81 /* Translate _stext address to physical, save in r23/r25 */
88 addis r3,r8,(is_second_reloc - 0b)@ha
89 lwz r19,(is_second_reloc - 0b)@l(r3)
91 /* Check if this is the second relocation. */
96 * For the second relocation, we already get the real memstart_addr
97 * from device tree. So we will map PAGE_OFFSET to memstart_addr,
98 * then the virtual address of start kernel should be:
99 * PAGE_OFFSET + (kernstart_addr - memstart_addr)
100 * Since the offset between kernstart_addr and memstart_addr should
101 * never be beyond 1G, so we can just use the lower 32bit of them
102 * for the calculation.
106 addis r4,r8,(kernstart_addr - 0b)@ha
107 addi r4,r4,(kernstart_addr - 0b)@l
110 addis r6,r8,(memstart_addr - 0b)@ha
111 addi r6,r6,(memstart_addr - 0b)@l
120 * We have the runtime (virutal) address of our base.
121 * We calculate our shift of offset from a 64M page.
122 * We could map the 64M page we belong to at PAGE_OFFSET and
123 * get going from there.
126 ori r4,r4,KERNELBASE@l
127 rlwinm r6,r25,0,0x3ffffff /* r6 = PHYS_START % 64M */
128 rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */
129 subf r3,r5,r6 /* r3 = r6 - r5 */
130 add r3,r4,r3 /* Required Virtual Address */
135 * For the second relocation, we already set the right tlb entries
136 * for the kernel space, so skip the code in fsl_booke_entry_mapping.S
142 /* We try to not make any assumptions about how the boot loader
143 * setup or used the TLBs. We invalidate all mappings from the
144 * boot loader and load a single entry in TLB1[0] to map the
145 * first 64M of kernel memory. Any boot info passed from the
146 * bootloader needs to live in this first 64M.
148 * Requirement on bootloader:
149 * - The page we're executing in needs to reside in TLB1 and
150 * have IPROT=1. If not an invalidate broadcast could
151 * evict the entry we're currently executing in.
153 * r3 = Index of TLB1 were executing in
154 * r4 = Current MSR[IS]
155 * r5 = Index of TLB1 temp mapping
157 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
161 _ENTRY(__early_start)
163 #define ENTRY_MAPPING_BOOT_SETUP
164 #include "fsl_booke_entry_mapping.S"
165 #undef ENTRY_MAPPING_BOOT_SETUP
168 /* Establish the interrupt vector offsets */
169 SET_IVOR(0, CriticalInput);
170 SET_IVOR(1, MachineCheck);
171 SET_IVOR(2, DataStorage);
172 SET_IVOR(3, InstructionStorage);
173 SET_IVOR(4, ExternalInput);
174 SET_IVOR(5, Alignment);
175 SET_IVOR(6, Program);
176 SET_IVOR(7, FloatingPointUnavailable);
177 SET_IVOR(8, SystemCall);
178 SET_IVOR(9, AuxillaryProcessorUnavailable);
179 SET_IVOR(10, Decrementer);
180 SET_IVOR(11, FixedIntervalTimer);
181 SET_IVOR(12, WatchdogTimer);
182 SET_IVOR(13, DataTLBError);
183 SET_IVOR(14, InstructionTLBError);
184 SET_IVOR(15, DebugCrit);
186 /* Establish the interrupt vector base */
187 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
190 /* Setup the defaults for TLB entries */
191 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
193 oris r2,r2,MAS4_TLBSELD(1)@h
200 oris r2,r2,HID0_DOZE@h
204 #if !defined(CONFIG_BDI_SWITCH)
206 * The Abatron BDI JTAG debugger does not tolerate others
207 * mucking with the debug registers.
212 /* clear any residual debug events */
218 /* Check to see if we're the second processor, and jump
219 * to the secondary_start code if so
221 LOAD_REG_ADDR_PIC(r24, boot_cpuid)
225 bne __secondary_start
229 * This is where the main kernel code starts.
234 ori r2,r2,init_task@l
236 /* ptr to current thread */
237 addi r4,r2,THREAD /* init task's THREAD */
238 mtspr SPRN_SPRG_THREAD,r4
241 lis r1,init_thread_union@h
242 ori r1,r1,init_thread_union@l
244 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
247 CURRENT_THREAD_INFO(r22, r1)
253 #ifdef CONFIG_RELOCATABLE
256 #ifdef CONFIG_PHYS_64BIT
265 #ifdef CONFIG_DYNAMIC_MEMSTART
266 lis r3,kernstart_addr@ha
267 la r3,kernstart_addr@l(r3)
268 #ifdef CONFIG_PHYS_64BIT
277 * Decide what sort of machine this is and initialize the MMU.
284 /* Setup PTE pointers for the Abatron bdiGDB */
285 lis r6, swapper_pg_dir@h
286 ori r6, r6, swapper_pg_dir@l
287 lis r5, abatron_pteptrs@h
288 ori r5, r5, abatron_pteptrs@l
290 ori r4, r4, KERNELBASE@l
291 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
295 lis r4,start_kernel@h
296 ori r4,r4,start_kernel@l
298 ori r3,r3,MSR_KERNEL@l
301 rfi /* change context and jump to start_kernel */
303 /* Macros to hide the PTE size differences
305 * FIND_PTE -- walks the page tables given EA & pgdir pointer
307 * r11 -- PGDIR pointer
309 * label 2: is the bailout case
311 * if we find the pte (fall through):
312 * r11 is low pte word
313 * r12 is pointer to the pte
314 * r10 is the pshift from the PGD, if we're a hugepage
316 #ifdef CONFIG_PTE_64BIT
317 #ifdef CONFIG_HUGETLB_PAGE
319 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
320 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
321 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
322 blt 1000f; /* Normal non-huge page */ \
323 beq 2f; /* Bail if no table */ \
324 oris r11, r11, PD_HUGE@h; /* Put back address bit */ \
325 andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \
326 xor r12, r10, r11; /* drop size bits from pointer */ \
328 1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
329 li r10, 0; /* clear r10 */ \
330 1001: lwz r11, 4(r12); /* Get pte entry */
333 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
334 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
335 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
336 beq 2f; /* Bail if no table */ \
337 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
338 lwz r11, 4(r12); /* Get pte entry */
339 #endif /* HUGEPAGE */
340 #else /* !PTE_64BIT */
342 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
343 lwz r11, 0(r11); /* Get L1 entry */ \
344 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
345 beq 2f; /* Bail if no table */ \
346 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
347 lwz r11, 0(r12); /* Get Linux PTE */
351 * Interrupt vector entry code
353 * The Book E MMUs are always on so we don't need to handle
354 * interrupts in real mode as with previous PPC processors. In
355 * this case we handle interrupts in the kernel virtual address
358 * Interrupt vectors are dynamically placed relative to the
359 * interrupt prefix as determined by the address of interrupt_base.
360 * The interrupt vectors offsets are programmed using the labels
361 * for each interrupt vector entry.
363 * Interrupt vectors must be aligned on a 16 byte boundary.
364 * We align on a 32 byte cache line boundary for good measure.
368 /* Critical Input Interrupt */
369 CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
371 /* Machine Check Interrupt */
373 /* no RFMCI, MCSRRs on E200 */
374 CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \
375 machine_check_exception)
377 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
380 /* Data Storage Interrupt */
381 START_EXCEPTION(DataStorage)
382 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE)
383 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
385 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
386 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
388 EXC_XFER_LITE(0x0300, handle_page_fault)
390 addi r3,r1,STACK_FRAME_OVERHEAD
391 EXC_XFER_EE_LITE(0x0300, CacheLockingException)
393 /* Instruction Storage Interrupt */
394 INSTRUCTION_STORAGE_EXCEPTION
396 /* External Input Interrupt */
397 EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE)
399 /* Alignment Interrupt */
402 /* Program Interrupt */
405 /* Floating Point Unavailable Interrupt */
406 #ifdef CONFIG_PPC_FPU
407 FP_UNAVAILABLE_EXCEPTION
410 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
411 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
412 program_check_exception, EXC_XFER_EE)
414 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
415 unknown_exception, EXC_XFER_EE)
419 /* System Call Interrupt */
420 START_EXCEPTION(SystemCall)
421 NORMAL_EXCEPTION_PROLOG(SYSCALL)
422 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
424 /* Auxiliary Processor Unavailable Interrupt */
425 EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \
426 unknown_exception, EXC_XFER_EE)
428 /* Decrementer Interrupt */
429 DECREMENTER_EXCEPTION
431 /* Fixed Internal Timer Interrupt */
432 /* TODO: Add FIT support */
433 EXCEPTION(0x3100, FIT, FixedIntervalTimer, \
434 unknown_exception, EXC_XFER_EE)
436 /* Watchdog Timer Interrupt */
437 #ifdef CONFIG_BOOKE_WDT
438 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException)
440 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception)
443 /* Data TLB Error Interrupt */
444 START_EXCEPTION(DataTLBError)
445 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
446 mfspr r10, SPRN_SPRG_THREAD
447 stw r11, THREAD_NORMSAVE(0)(r10)
448 #ifdef CONFIG_KVM_BOOKE_HV
451 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
453 stw r12, THREAD_NORMSAVE(1)(r10)
454 stw r13, THREAD_NORMSAVE(2)(r10)
456 stw r13, THREAD_NORMSAVE(3)(r10)
457 DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1
458 START_BTB_FLUSH_SECTION
464 END_BTB_FLUSH_SECTION
465 mfspr r10, SPRN_DEAR /* Get faulting address */
467 /* If we are faulting a kernel address, we have to use the
468 * kernel page tables.
470 lis r11, PAGE_OFFSET@h
473 lis r11, swapper_pg_dir@h
474 ori r11, r11, swapper_pg_dir@l
476 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
477 rlwinm r12,r12,0,16,1
482 /* Get the PGD for the current thread */
484 mfspr r11,SPRN_SPRG_THREAD
488 /* Mask of required permission bits. Note that while we
489 * do copy ESR:ST to _PAGE_RW position as trying to write
490 * to an RO page is pretty common, we don't do it with
491 * _PAGE_DIRTY. We could do it, but it's a fairly rare
492 * event so I'd rather take the overhead when it happens
493 * rather than adding an instruction here. We should measure
494 * whether the whole thing is worth it in the first place
495 * as we could avoid loading SPRN_ESR completely in the first
498 * TODO: Is it worth doing that mfspr & rlwimi in the first
499 * place or can we save a couple of instructions here ?
502 #ifdef CONFIG_PTE_64BIT
504 oris r13,r13,_PAGE_ACCESSED@h
506 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
508 rlwimi r13,r12,11,29,29
511 andc. r13,r13,r11 /* Check permission */
513 #ifdef CONFIG_PTE_64BIT
515 subf r13,r11,r12 /* create false data dep */
516 lwzx r13,r11,r13 /* Get upper pte bits */
518 lwz r13,0(r12) /* Get upper pte bits */
522 bne 2f /* Bail if permission/valid mismach */
524 /* Jump to common tlb load */
527 /* The bailout. Restore registers to pre-exception conditions
528 * and call the heavyweights to help us out.
530 mfspr r10, SPRN_SPRG_THREAD
531 lwz r11, THREAD_NORMSAVE(3)(r10)
533 lwz r13, THREAD_NORMSAVE(2)(r10)
534 lwz r12, THREAD_NORMSAVE(1)(r10)
535 lwz r11, THREAD_NORMSAVE(0)(r10)
536 mfspr r10, SPRN_SPRG_RSCRATCH0
539 /* Instruction TLB Error Interrupt */
541 * Nearly the same as above, except we get our
542 * information from different registers and bailout
543 * to a different point.
545 START_EXCEPTION(InstructionTLBError)
546 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
547 mfspr r10, SPRN_SPRG_THREAD
548 stw r11, THREAD_NORMSAVE(0)(r10)
549 #ifdef CONFIG_KVM_BOOKE_HV
552 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
554 stw r12, THREAD_NORMSAVE(1)(r10)
555 stw r13, THREAD_NORMSAVE(2)(r10)
557 stw r13, THREAD_NORMSAVE(3)(r10)
558 DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1
559 START_BTB_FLUSH_SECTION
565 END_BTB_FLUSH_SECTION
567 mfspr r10, SPRN_SRR0 /* Get faulting address */
569 /* If we are faulting a kernel address, we have to use the
570 * kernel page tables.
572 lis r11, PAGE_OFFSET@h
575 lis r11, swapper_pg_dir@h
576 ori r11, r11, swapper_pg_dir@l
578 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
579 rlwinm r12,r12,0,16,1
582 /* Make up the required permissions for kernel code */
583 #ifdef CONFIG_PTE_64BIT
584 li r13,_PAGE_PRESENT | _PAGE_BAP_SX
585 oris r13,r13,_PAGE_ACCESSED@h
587 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
591 /* Get the PGD for the current thread */
593 mfspr r11,SPRN_SPRG_THREAD
596 /* Make up the required permissions for user code */
597 #ifdef CONFIG_PTE_64BIT
598 li r13,_PAGE_PRESENT | _PAGE_BAP_UX
599 oris r13,r13,_PAGE_ACCESSED@h
601 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
606 andc. r13,r13,r11 /* Check permission */
608 #ifdef CONFIG_PTE_64BIT
610 subf r13,r11,r12 /* create false data dep */
611 lwzx r13,r11,r13 /* Get upper pte bits */
613 lwz r13,0(r12) /* Get upper pte bits */
617 bne 2f /* Bail if permission mismach */
619 /* Jump to common TLB load point */
623 /* The bailout. Restore registers to pre-exception conditions
624 * and call the heavyweights to help us out.
626 mfspr r10, SPRN_SPRG_THREAD
627 lwz r11, THREAD_NORMSAVE(3)(r10)
629 lwz r13, THREAD_NORMSAVE(2)(r10)
630 lwz r12, THREAD_NORMSAVE(1)(r10)
631 lwz r11, THREAD_NORMSAVE(0)(r10)
632 mfspr r10, SPRN_SPRG_RSCRATCH0
635 /* Define SPE handlers for e200 and e500v2 */
637 /* SPE Unavailable */
638 START_EXCEPTION(SPEUnavailable)
639 NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL)
642 b fast_exception_return
643 1: addi r3,r1,STACK_FRAME_OVERHEAD
644 EXC_XFER_EE_LITE(0x2010, KernelSPE)
645 #elif defined(CONFIG_SPE_POSSIBLE)
646 EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \
647 unknown_exception, EXC_XFER_EE)
648 #endif /* CONFIG_SPE_POSSIBLE */
650 /* SPE Floating Point Data */
652 EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData,
653 SPEFloatingPointException, EXC_XFER_EE)
655 /* SPE Floating Point Round */
656 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
657 SPEFloatingPointRoundException, EXC_XFER_EE)
658 #elif defined(CONFIG_SPE_POSSIBLE)
659 EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData,
660 unknown_exception, EXC_XFER_EE)
661 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
662 unknown_exception, EXC_XFER_EE)
663 #endif /* CONFIG_SPE_POSSIBLE */
666 /* Performance Monitor */
667 EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
668 performance_monitor_exception, EXC_XFER_STD)
670 EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD)
672 CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \
673 CriticalDoorbell, unknown_exception)
675 /* Debug Interrupt */
676 DEBUG_DEBUG_EXCEPTION
679 GUEST_DOORBELL_EXCEPTION
681 CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \
685 EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_EE)
687 /* Embedded Hypervisor Privilege */
688 EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_EE)
697 * Both the instruction and data TLB miss get to this
698 * point to load the TLB.
699 * r10 - tsize encoding (if HUGETLB_PAGE) or available to use
700 * r11 - TLB (info from Linux PTE)
701 * r12 - available to use
702 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
703 * CR5 - results of addr >= PAGE_OFFSET
704 * MAS0, MAS1 - loaded with proper value when we get here
705 * MAS2, MAS3 - will need additional info from Linux PTE
706 * Upon exit, we reload everything and RFI.
709 #ifdef CONFIG_HUGETLB_PAGE
710 cmpwi 6, r10, 0 /* check for huge page */
711 beq 6, finish_tlb_load_cont /* !huge */
713 /* Alas, we need more scratch registers for hugepages */
714 mfspr r12, SPRN_SPRG_THREAD
715 stw r14, THREAD_NORMSAVE(4)(r12)
716 stw r15, THREAD_NORMSAVE(5)(r12)
717 stw r16, THREAD_NORMSAVE(6)(r12)
718 stw r17, THREAD_NORMSAVE(7)(r12)
720 /* Get the next_tlbcam_idx percpu var */
722 lwz r15, TI_CPU-THREAD(r12)
723 lis r14, __per_cpu_offset@h
724 ori r14, r14, __per_cpu_offset@l
725 rlwinm r15, r15, 2, 0, 29
730 lis r17, next_tlbcam_idx@h
731 ori r17, r17, next_tlbcam_idx@l
732 add r17, r17, r16 /* r17 = *next_tlbcam_idx */
733 lwz r15, 0(r17) /* r15 = next_tlbcam_idx */
735 lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */
736 rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */
739 /* Extract TLB1CFG(NENTRY) */
740 mfspr r16, SPRN_TLB1CFG
741 andi. r16, r16, 0xfff
743 /* Update next_tlbcam_idx, wrapping when necessary */
747 lis r14, tlbcam_index@h
748 ori r14, r14, tlbcam_index@l
753 * Calc MAS1_TSIZE from r10 (which has pshift encoded)
754 * tlb_enc = (pshift - 10).
758 rlwimi r16, r15, 7, 20, 24
761 /* copy the pshift for use later */
766 #endif /* CONFIG_HUGETLB_PAGE */
769 * We set execute, because we don't have the granularity to
770 * properly set this at the page level (Linux problem).
771 * Many of these bits are software only. Bits we don't set
772 * here we (properly should) assume have the appropriate value.
774 finish_tlb_load_cont:
775 #ifdef CONFIG_PTE_64BIT
776 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
777 andi. r10, r11, _PAGE_DIRTY
779 li r10, MAS3_SW | MAS3_UW
781 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
782 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
783 2: mtspr SPRN_MAS3, r12
784 BEGIN_MMU_FTR_SECTION
785 srwi r10, r13, 12 /* grab RPN[12:31] */
787 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
789 li r10, (_PAGE_EXEC | _PAGE_PRESENT)
791 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
793 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
797 rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */
802 #ifdef CONFIG_PTE_64BIT
803 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
805 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
807 #ifdef CONFIG_HUGETLB_PAGE
808 beq 6, 3f /* don't mask if page isn't huge */
812 rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */
813 andc r12, r12, r13 /* mask off ea bits within the page */
815 3: mtspr SPRN_MAS2, r12
818 /* Round robin TLB1 entries assignment */
821 /* Extract TLB1CFG(NENTRY) */
822 mfspr r11, SPRN_TLB1CFG
823 andi. r11, r11, 0xfff
825 /* Extract MAS0(NV) */
826 andi. r13, r12, 0xfff
831 /* check if we need to wrap */
834 /* wrap back to first free tlbcam entry */
835 lis r13, tlbcam_index@ha
836 lwz r13, tlbcam_index@l(r13)
837 rlwimi r12, r13, 0, 20, 31
840 #endif /* CONFIG_E200 */
845 /* Done...restore registers and get out of here. */
846 mfspr r10, SPRN_SPRG_THREAD
847 #ifdef CONFIG_HUGETLB_PAGE
848 beq 6, 8f /* skip restore for 4k page faults */
849 lwz r14, THREAD_NORMSAVE(4)(r10)
850 lwz r15, THREAD_NORMSAVE(5)(r10)
851 lwz r16, THREAD_NORMSAVE(6)(r10)
852 lwz r17, THREAD_NORMSAVE(7)(r10)
854 8: lwz r11, THREAD_NORMSAVE(3)(r10)
856 lwz r13, THREAD_NORMSAVE(2)(r10)
857 lwz r12, THREAD_NORMSAVE(1)(r10)
858 lwz r11, THREAD_NORMSAVE(0)(r10)
859 mfspr r10, SPRN_SPRG_RSCRATCH0
860 rfi /* Force context change */
863 /* Note that the SPE support is closely modeled after the AltiVec
864 * support. Changes to one are likely to be applicable to the
868 * Disable SPE for the task which had SPE previously,
869 * and save its SPE registers in its thread_struct.
870 * Enables SPE for use in the kernel on return.
871 * On SMP we know the SPE units are free, since we give it up every
876 mtmsr r5 /* enable use of SPE now */
878 /* enable use of SPE after return */
880 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
883 stw r4,THREAD_USED_SPE(r5)
886 REST_32EVRS(0,r10,r5,THREAD_EVR0)
890 * SPE unavailable trap from kernel - print a message, but let
891 * the task use SPE in the kernel until it returns to user mode.
896 stw r3,_MSR(r1) /* enable use of SPE after return */
900 mr r4,r2 /* current */
906 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
910 #endif /* CONFIG_SPE */
913 * Translate the effec addr in r3 to phys addr. The phys addr will be put
914 * into r3(higher 32bit) and r4(lower 32bit)
919 rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */
920 rlwimi r9,r8,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */
923 tlbsx 0,r3 /* must succeed */
927 rlwinm r9,r8,25,0x1f /* r9 = log2(page size) */
929 slw r10,r10,r9 /* r10 = page size */
931 and r11,r3,r10 /* r11 = page offset */
932 andc r4,r12,r10 /* r4 = page base */
933 or r4,r4,r11 /* r4 = devtree phys addr */
934 #ifdef CONFIG_PHYS_64BIT
944 /* Adjust or setup IVORs for e200 */
945 _GLOBAL(__setup_e200_ivors)
948 li r3,SPEUnavailable@l
950 li r3,SPEFloatingPointData@l
952 li r3,SPEFloatingPointRound@l
959 #ifndef CONFIG_PPC_E500MC
960 /* Adjust or setup IVORs for e500v1/v2 */
961 _GLOBAL(__setup_e500_ivors)
964 li r3,SPEUnavailable@l
966 li r3,SPEFloatingPointData@l
968 li r3,SPEFloatingPointRound@l
970 li r3,PerformanceMonitor@l
975 /* Adjust or setup IVORs for e500mc */
976 _GLOBAL(__setup_e500mc_ivors)
979 li r3,PerformanceMonitor@l
983 li r3,CriticalDoorbell@l
988 /* setup ehv ivors for */
989 _GLOBAL(__setup_ehv_ivors)
990 li r3,GuestDoorbell@l
992 li r3,CriticalGuestDoorbell@l
1000 #endif /* CONFIG_PPC_E500MC */
1001 #endif /* CONFIG_E500 */
1005 * extern void __giveup_spe(struct task_struct *prev)
1008 _GLOBAL(__giveup_spe)
1009 addi r3,r3,THREAD /* want THREAD of task */
1012 SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
1013 evxor evr6, evr6, evr6 /* clear out evr6 */
1014 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
1016 evstddx evr6, r4, r3 /* save off accumulator */
1018 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1020 andc r4,r4,r3 /* disable SPE for previous task */
1021 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1024 #endif /* CONFIG_SPE */
1027 * extern void abort(void)
1029 * At present, this routine just applies a system reset.
1033 mtspr SPRN_DBCR0,r13 /* disable all debug events */
1036 ori r13,r13,MSR_DE@l /* Enable Debug Events */
1039 mfspr r13,SPRN_DBCR0
1040 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1041 mtspr SPRN_DBCR0,r13
1044 _GLOBAL(set_context)
1046 #ifdef CONFIG_BDI_SWITCH
1047 /* Context switch the PTE pointer for the Abatron BDI2000.
1048 * The PGDIR is the second parameter.
1050 lis r5, abatron_pteptrs@h
1051 ori r5, r5, abatron_pteptrs@l
1055 isync /* Force context change */
1059 /* When we get here, r24 needs to hold the CPU # */
1060 .globl __secondary_start
1062 LOAD_REG_ADDR_PIC(r3, tlbcam_index)
1065 li r26,0 /* r26 safe? */
1068 mr r27,r3 /* tlb entry */
1069 /* Load each CAM entry */
1074 mr r3,r27 /* tlb entry */
1075 LOAD_REG_ADDR_PIC(r4, memstart_addr)
1077 mr r5,r25 /* phys kernel start */
1078 rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */
1079 subf r4,r5,r4 /* memstart_addr - phys kernel start */
1080 li r5,0 /* no device tree */
1081 li r6,0 /* not boot cpu */
1085 lis r3,__secondary_hold_acknowledge@h
1086 ori r3,r3,__secondary_hold_acknowledge@l
1090 mr r4,r24 /* Why? */
1093 /* get current's stack and current */
1094 lis r1,secondary_ti@ha
1095 lwz r2,secondary_ti@l(r1)
1096 lwz r1,TASK_STACK(r2)
1099 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1103 /* ptr to current thread */
1104 addi r4,r2,THREAD /* address of our thread_struct */
1105 mtspr SPRN_SPRG_THREAD,r4
1107 /* Setup the defaults for TLB entries */
1108 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1111 /* Jump to start_secondary */
1113 ori r4,r4,MSR_KERNEL@l
1114 lis r3,start_secondary@h
1115 ori r3,r3,start_secondary@l
1122 .globl __secondary_hold_acknowledge
1123 __secondary_hold_acknowledge:
1128 * Create a tlb entry with the same effective and physical address as
1129 * the tlb entry used by the current running code. But set the TS to 1.
1130 * Then switch to the address space 1. It will return with the r3 set to
1131 * the ESEL of the new created tlb.
1133 _GLOBAL(switch_to_as1)
1136 /* Find a entry not used */
1137 mfspr r3,SPRN_TLB1CFG
1140 rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */
1142 1: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */
1144 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1148 andis. r4,r4,MAS1_VALID@h
1151 /* Get the tlb entry used by the current running code */
1157 ori r4,r4,MAS1_TS /* Set the TS = 1 */
1161 rlwinm r4,r4,0,~MAS0_ESEL_MASK
1162 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1169 ori r4,r4,MSR_IS | MSR_DS
1176 * Restore to the address space 0 and also invalidate the tlb entry created
1178 * r3 - the tlb entry which should be invalidated
1179 * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
1180 * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
1183 _GLOBAL(restore_to_as0)
1191 * We may map the PAGE_OFFSET in AS0 to a different physical address,
1192 * so we need calculate the right jump and device tree address based
1193 * on the offset passed by r4.
1200 li r8,(MSR_IS | MSR_DS)
1208 /* Invalidate the temporary tlb entry for AS1 */
1209 1: lis r9,0x1000 /* Set MAS0(TLBSEL) = 1 */
1210 rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1214 rlwinm r9,r9,0,2,31 /* Clear MAS1 Valid and IPPROT */
1222 bne 3f /* offset != 0 && is_boot_cpu */
1227 * The PAGE_OFFSET will map to a different physical address,
1228 * jump to _start to do another relocation again.
1234 * We put a few things here that have to be page-aligned. This stuff
1235 * goes at the beginning of the data segment, which is page-aligned.
1241 .globl empty_zero_page
1244 EXPORT_SYMBOL(empty_zero_page)
1245 .globl swapper_pg_dir
1247 .space PGD_TABLE_SIZE
1250 * Room for two PTE pointers, usually the kernel and current user pointers
1251 * to their respective root page table.