1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Adapted for Power Macintosh by Paul Mackerras.
9 * Low-level exception handlers and MMU support
10 * rewritten by Paul Mackerras.
11 * Copyright (C) 1996 Paul Mackerras.
12 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
14 * This file contains the low-level support and setup for the
15 * PowerPC platform, including trap and interrupt dispatch.
16 * (The PPC 8xx embedded CPUs use head_8xx.S instead.)
19 #include <linux/init.h>
20 #include <linux/pgtable.h>
24 #include <asm/cputable.h>
25 #include <asm/cache.h>
26 #include <asm/thread_info.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/ptrace.h>
31 #include <asm/kvm_book3s_asm.h>
32 #include <asm/export.h>
33 #include <asm/feature-fixups.h>
37 #define LOAD_BAT(n, reg, RA, RB) \
38 /* see the comment for clear_bats() -- Cort */ \
40 mtspr SPRN_IBAT##n##U,RA; \
41 mtspr SPRN_DBAT##n##U,RA; \
42 lwz RA,(n*16)+0(reg); \
43 lwz RB,(n*16)+4(reg); \
44 mtspr SPRN_IBAT##n##U,RA; \
45 mtspr SPRN_IBAT##n##L,RB; \
46 lwz RA,(n*16)+8(reg); \
47 lwz RB,(n*16)+12(reg); \
48 mtspr SPRN_DBAT##n##U,RA; \
49 mtspr SPRN_DBAT##n##L,RB
52 .stabs "arch/powerpc/kernel/",N_SO,0,0,0f
53 .stabs "head_book3s_32.S",N_SO,0,0,0f
58 * _start is defined this way because the XCOFF loader in the OpenFirmware
59 * on the powermac expects the entry point to be a procedure descriptor.
63 * These are here for legacy reasons, the kernel used to
64 * need to look like a coff function entry for the pmac
65 * but we're always started by some kind of bootloader now.
68 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
69 nop /* used by __secondary_hold on prep (mtx) and chrp smp */
73 * Enter here with the kernel text, data and bss loaded starting at
74 * 0, running with virtual == physical mapping.
75 * r5 points to the prom entry point (the client interface handler
76 * address). Address translation is turned on, with the prom
77 * managing the hash table. Interrupts are disabled. The stack
78 * pointer (r1) points to just below the end of the half-meg region
79 * from 0x380000 - 0x400000, which is mapped in already.
81 * If we are booted from MacOS via BootX, we enter with the kernel
82 * image loaded somewhere, and the following values in registers:
83 * r3: 'BooX' (0x426f6f58)
84 * r4: virtual address of boot_infos_t
88 * This is jumped to on prep systems right after the kernel is relocated
89 * to its proper place in memory by the boot loader. The expected layout
91 * r3: ptr to residual data
92 * r4: initrd_start or if no initrd then 0
93 * r5: initrd_end - unused if r4 is 0
94 * r6: Start of command line string
95 * r7: End of command line string
97 * This just gets a minimal mmu environment setup so we can call
98 * start_here() to do the real work.
105 * We have to do any OF calls before we map ourselves to KERNELBASE,
106 * because OF may have I/O devices mapped into that area
107 * (particularly on CHRP).
112 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
113 /* find out where we are now */
115 0: mflr r8 /* r8 = runtime addr here */
116 addis r8,r8,(_stext - 0b)@ha
117 addi r8,r8,(_stext - 0b)@l /* current runtime base addr */
119 #endif /* CONFIG_PPC_OF_BOOT_TRAMPOLINE */
121 /* We never return. We also hit that trap if trying to boot
122 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
126 * Check for BootX signature when supporting PowerMac and branch to
127 * appropriate trampoline if it's present
129 #ifdef CONFIG_PPC_PMAC
136 #endif /* CONFIG_PPC_PMAC */
138 1: mr r31,r3 /* save device tree ptr */
142 * early_init() does the early machine identification and does
143 * the necessary low-level setup and clears the BSS
144 * -- Cort <cort@fsmlabs.com>
148 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
149 * the physical address we are running at, returned by early_init()
157 bl load_segment_registers
160 #if defined(CONFIG_BOOTX_TEXT)
163 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
166 #ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
167 bl setup_usbgecko_bat
171 * Call setup_cpu for CPU 0 and initialize 6xx Idle
175 bl call_setup_cpu /* Call setup_cpu for this CPU */
181 * We need to run with _start at physical address 0.
182 * On CHRP, we are loaded at 0x10000 since OF on CHRP uses
183 * the exception vectors at 0 (and therefore this copy
184 * overwrites OF's exception vectors with our own).
185 * The MMU is off at this point.
189 addis r4,r3,KERNELBASE@h /* current address of _start */
190 lis r5,PHYSICAL_START@h
191 cmplw 0,r4,r5 /* already running at PHYSICAL_START? */
194 * we now have the 1st 16M of ram mapped with the bats.
195 * prep needs the mmu to be turned on here, but pmac already has it on.
196 * this shouldn't bother the pmac since it just gets turned on again
197 * as we jump to our code at KERNELBASE. -- Cort
198 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
199 * off, and in other cases, we now turn it off before changing BATs above.
203 ori r0,r0,MSR_DR|MSR_IR|MSR_RI
206 ori r0,r0,start_here@l
208 rfi /* enables MMU */
211 * We need __secondary_hold as a place to hold the other cpus on
212 * an SMP machine, even when we are running a UP kernel.
214 . = 0xc0 /* for prep bootloader */
215 li r3,1 /* MTX only has 1 cpu */
216 .globl __secondary_hold
218 /* tell the master we're here */
219 stw r3,__secondary_hold_acknowledge@l(0)
222 /* wait until we're told to start */
225 /* our cpu # was at addr 0 - go */
226 mr r24,r3 /* cpu # */
230 #endif /* CONFIG_SMP */
232 .globl __secondary_hold_spinloop
233 __secondary_hold_spinloop:
235 .globl __secondary_hold_acknowledge
236 __secondary_hold_acknowledge:
240 /* core99 pmac starts the seconary here by changing the vector, and
241 putting it back to what it was (unknown_exception) when done. */
242 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
246 * On CHRP, this is complicated by the fact that we could get a
247 * machine check inside RTAS, and we have no guarantee that certain
248 * critical registers will have the values we expect. The set of
249 * registers that might have bad values includes all the GPRs
250 * and all the BATs. We indicate that we are in RTAS by putting
251 * a non-zero value, the address of the exception frame to use,
252 * in thread.rtas_sp. The machine check handler checks thread.rtas_sp
253 * and uses its value if it is non-zero.
254 * (Other exception handlers assume that r1 is a valid kernel stack
255 * pointer when we take an exception from supervisor mode.)
262 #ifdef CONFIG_PPC_CHRP
263 mfspr r11, SPRN_SPRG_THREAD
264 lwz r11, RTAS_SP(r11)
267 #endif /* CONFIG_PPC_CHRP */
268 EXCEPTION_PROLOG_1 for_rtas=1
269 7: EXCEPTION_PROLOG_2
270 addi r3,r1,STACK_FRAME_OVERHEAD
271 #ifdef CONFIG_PPC_CHRP
272 #ifdef CONFIG_VMAP_STACK
273 mfspr r4, SPRN_SPRG_THREAD
278 beq cr1, machine_check_tramp
281 b machine_check_tramp
284 /* Data access exception. */
288 #ifdef CONFIG_VMAP_STACK
289 #ifdef CONFIG_PPC_BOOK3S_604
290 BEGIN_MMU_FTR_SECTION
291 mtspr SPRN_SPRG_SCRATCH2,r10
292 mfspr r10, SPRN_SPRG_THREAD
294 mfspr r10, SPRN_DSISR
296 andis. r10, r10, (DSISR_BAD_FAULT_32S | DSISR_DABRMATCH)@h
297 mfspr r10, SPRN_SPRG_THREAD
299 .Lhash_page_dsi_cont:
302 mfspr r10, SPRN_SPRG_SCRATCH2
305 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE)
307 1: EXCEPTION_PROLOG_0 handle_dar_dsisr=1
309 b handle_page_fault_tramp_1
310 #else /* CONFIG_VMAP_STACK */
311 EXCEPTION_PROLOG handle_dar_dsisr=1
312 get_and_save_dar_dsisr_on_stack r4, r5, r11
313 #ifdef CONFIG_PPC_BOOK3S_604
314 BEGIN_MMU_FTR_SECTION
315 andis. r0, r5, (DSISR_BAD_FAULT_32S | DSISR_DABRMATCH)@h
316 bne handle_page_fault_tramp_2 /* if not, try to put a PTE */
317 rlwinm r3, r5, 32 - 15, 21, 21 /* DSISR_STORE -> _PAGE_RW */
319 b handle_page_fault_tramp_1
322 b handle_page_fault_tramp_2
323 #ifdef CONFIG_PPC_BOOK3S_604
324 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE)
326 #endif /* CONFIG_VMAP_STACK */
328 /* Instruction access exception. */
332 #ifdef CONFIG_VMAP_STACK
333 mtspr SPRN_SPRG_SCRATCH0,r10
334 mtspr SPRN_SPRG_SCRATCH1,r11
335 mfspr r10, SPRN_SPRG_THREAD
338 mfspr r11, SPRN_SRR1 /* check whether user or kernel */
341 #ifdef CONFIG_PPC_BOOK3S_604
342 BEGIN_MMU_FTR_SECTION
343 andis. r11, r11, SRR1_ISI_NOPT@h /* no pte found? */
345 .Lhash_page_isi_cont:
346 mfspr r11, SPRN_SRR1 /* check whether user or kernel */
347 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
349 andi. r11, r11, MSR_PR
353 #else /* CONFIG_VMAP_STACK */
355 andis. r0,r9,SRR1_ISI_NOPT@h /* no pte found? */
356 beq 1f /* if so, try to put a PTE */
357 li r3,0 /* into the hash table */
358 mr r4,r12 /* SRR0 is fault address */
359 #ifdef CONFIG_PPC_BOOK3S_604
360 BEGIN_MMU_FTR_SECTION
362 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
364 #endif /* CONFIG_VMAP_STACK */
365 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
368 EXC_XFER_LITE(0x400, handle_page_fault)
370 /* External interrupt */
371 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
373 /* Alignment exception */
377 EXCEPTION_PROLOG handle_dar_dsisr=1
378 save_dar_dsisr_on_stack r4, r5, r11
379 addi r3,r1,STACK_FRAME_OVERHEAD
380 b alignment_exception_tramp
382 /* Program check exception */
383 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
385 /* Floating-point unavailable */
389 #ifdef CONFIG_PPC_FPU
392 * Certain Freescale cores don't have a FPU and treat fp instructions
393 * as a FP Unavailable exception. Redirect to illegal/emulation handling.
396 END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
399 bl load_up_fpu /* if from user, just load it up */
400 b fast_exception_return
401 1: addi r3,r1,STACK_FRAME_OVERHEAD
402 EXC_XFER_LITE(0x800, kernel_fp_unavailable_exception)
408 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
410 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_STD)
411 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_STD)
419 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
420 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_STD)
423 * The Altivec unavailable trap is at 0x0f20. Foo.
424 * We effectively remap it to 0x3000.
425 * We include an altivec unavailable exception vector even if
426 * not configured for Altivec, so that you can't panic a
427 * non-altivec kernel running on a machine with altivec just
428 * by executing an altivec instruction.
439 * Handle TLB miss for instruction on 603/603e.
440 * Note: we get an alternate set of r0 - r3 to use automatically.
446 * r1: linux style pte ( later becomes ppc hardware pte )
447 * r2: ptr to linux-style pte
450 /* Get PTE (linux-style) and check access */
452 #ifdef CONFIG_MODULES
453 lis r1, TASK_SIZE@h /* check if kernel address */
457 li r1,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
458 rlwinm r2, r2, 28, 0xfffff000
459 #ifdef CONFIG_MODULES
461 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
462 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
464 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
465 lwz r2,0(r2) /* get pmd entry */
466 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
467 beq- InstructionAddressInvalid /* return if no mapping */
468 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
469 lwz r0,0(r2) /* get linux-style pte */
470 andc. r1,r1,r0 /* check access & ~permission */
471 bne- InstructionAddressInvalid /* return if access not permitted */
472 /* Convert linux-style PTE to low word of PPC-style PTE */
473 rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
474 ori r1, r1, 0xe06 /* clear out reserved bits */
475 andc r1, r0, r1 /* PP = user? 1 : 0 */
477 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
478 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
481 mfspr r3,SPRN_SRR1 /* Need to restore CR0 */
484 InstructionAddressInvalid:
486 rlwinm r1,r3,9,6,6 /* Get load/store bit */
489 mtspr SPRN_DSISR,r1 /* (shouldn't be needed) */
490 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
493 mfspr r1,SPRN_IMISS /* Get failing address */
494 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
495 rlwimi r2,r2,1,30,30 /* change 1 -> 3 */
497 mtspr SPRN_DAR,r1 /* Set fault address */
498 mfmsr r0 /* Restore "normal" registers */
499 xoris r0,r0,MSR_TGPR>>16
500 mtcrf 0x80,r3 /* Restore CR0 */
505 * Handle TLB miss for DATA Load operation on 603/603e
511 * r1: linux style pte ( later becomes ppc hardware pte )
512 * r2: ptr to linux-style pte
515 /* Get PTE (linux-style) and check access */
517 lis r1, TASK_SIZE@h /* check if kernel address */
520 li r1, _PAGE_PRESENT | _PAGE_ACCESSED
521 rlwinm r2, r2, 28, 0xfffff000
523 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
524 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
525 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
526 lwz r2,0(r2) /* get pmd entry */
527 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
528 beq- DataAddressInvalid /* return if no mapping */
529 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
530 lwz r0,0(r2) /* get linux-style pte */
531 andc. r1,r1,r0 /* check access & ~permission */
532 bne- DataAddressInvalid /* return if access not permitted */
534 * NOTE! We are assuming this is not an SMP system, otherwise
535 * we would need to update the pte atomically with lwarx/stwcx.
537 /* Convert linux-style PTE to low word of PPC-style PTE */
538 rlwinm r1,r0,32-9,30,30 /* _PAGE_RW -> PP msb */
539 rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
540 rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
541 ori r1,r1,0xe04 /* clear out reserved bits */
542 andc r1,r0,r1 /* PP = user? rw? 1: 3: 0 */
544 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
545 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
547 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
549 BEGIN_MMU_FTR_SECTION
551 mfspr r1,SPRN_SPRG_603_LRU
552 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
556 mtspr SPRN_SPRG_603_LRU,r1
558 rlwimi r2,r0,31-14,14,14
560 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
565 rlwinm r1,r3,9,6,6 /* Get load/store bit */
568 andi. r2,r3,0xFFFF /* Clear upper bits of SRR1 */
570 mfspr r1,SPRN_DMISS /* Get failing address */
571 rlwinm. r2,r2,0,31,31 /* Check for little endian access */
572 beq 20f /* Jump if big endian */
574 20: mtspr SPRN_DAR,r1 /* Set fault address */
575 mfmsr r0 /* Restore "normal" registers */
576 xoris r0,r0,MSR_TGPR>>16
577 mtcrf 0x80,r3 /* Restore CR0 */
582 * Handle TLB miss for DATA Store on 603/603e
588 * r1: linux style pte ( later becomes ppc hardware pte )
589 * r2: ptr to linux-style pte
592 /* Get PTE (linux-style) and check access */
594 lis r1, TASK_SIZE@h /* check if kernel address */
597 li r1, _PAGE_RW | _PAGE_DIRTY | _PAGE_PRESENT | _PAGE_ACCESSED
598 rlwinm r2, r2, 28, 0xfffff000
600 lis r2, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
601 addi r2, r2, (swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
602 112: rlwimi r2,r3,12,20,29 /* insert top 10 bits of address */
603 lwz r2,0(r2) /* get pmd entry */
604 rlwinm. r2,r2,0,0,19 /* extract address of pte page */
605 beq- DataAddressInvalid /* return if no mapping */
606 rlwimi r2,r3,22,20,29 /* insert next 10 bits of address */
607 lwz r0,0(r2) /* get linux-style pte */
608 andc. r1,r1,r0 /* check access & ~permission */
609 bne- DataAddressInvalid /* return if access not permitted */
611 * NOTE! We are assuming this is not an SMP system, otherwise
612 * we would need to update the pte atomically with lwarx/stwcx.
614 /* Convert linux-style PTE to low word of PPC-style PTE */
615 rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
616 li r1,0xe06 /* clear out reserved bits & PP msb */
617 andc r1,r0,r1 /* PP = user? 1: 0 */
619 rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */
620 END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)
622 mfspr r2,SPRN_SRR1 /* Need to restore CR0 */
624 BEGIN_MMU_FTR_SECTION
626 mfspr r1,SPRN_SPRG_603_LRU
627 rlwinm r2,r3,20,27,31 /* Get Address bits 15:19 */
631 mtspr SPRN_SPRG_603_LRU,r1
633 rlwimi r2,r0,31-14,14,14
635 END_MMU_FTR_SECTION_IFSET(MMU_FTR_NEED_DTLB_SW_LRU)
639 #ifndef CONFIG_ALTIVEC
640 #define altivec_assist_exception unknown_exception
643 #ifndef CONFIG_TAU_INT
644 #define TAUException unknown_exception
647 EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_STD)
648 EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_STD)
649 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_STD)
650 EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_STD)
651 EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
652 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_STD)
653 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_STD)
654 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_STD)
655 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_STD)
656 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_STD)
657 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_STD)
658 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_STD)
659 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_STD)
660 EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_STD)
661 EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_STD)
662 EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_STD)
663 EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_STD)
664 EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_STD)
665 EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_STD)
666 EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_STD)
667 EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_STD)
668 EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_STD)
669 EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_STD)
670 EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_STD)
671 EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_STD)
672 EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_STD)
673 EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_STD)
674 EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_STD)
675 EXCEPTION(0x2f00, Trap_2f, unknown_exception, EXC_XFER_STD)
680 EXC_XFER_STD(0x200, machine_check_exception)
682 alignment_exception_tramp:
683 EXC_XFER_STD(0x600, alignment_exception)
685 handle_page_fault_tramp_1:
686 #ifdef CONFIG_VMAP_STACK
687 EXCEPTION_PROLOG_2 handle_dar_dsisr=1
691 handle_page_fault_tramp_2:
692 andis. r0, r5, DSISR_DABRMATCH@h
694 EXC_XFER_LITE(0x300, handle_page_fault)
695 1: EXC_XFER_STD(0x300, do_break)
697 #ifdef CONFIG_VMAP_STACK
698 #ifdef CONFIG_PPC_BOOK3S_604
699 .macro save_regs_thread thread
700 stw r0, THR0(\thread)
701 stw r3, THR3(\thread)
702 stw r4, THR4(\thread)
703 stw r5, THR5(\thread)
704 stw r6, THR6(\thread)
705 stw r8, THR8(\thread)
706 stw r9, THR9(\thread)
708 stw r0, THLR(\thread)
710 stw r0, THCTR(\thread)
713 .macro restore_regs_thread thread
714 lwz r0, THLR(\thread)
716 lwz r0, THCTR(\thread)
718 lwz r0, THR0(\thread)
719 lwz r3, THR3(\thread)
720 lwz r4, THR4(\thread)
721 lwz r5, THR5(\thread)
722 lwz r6, THR6(\thread)
723 lwz r8, THR8(\thread)
724 lwz r9, THR9(\thread)
733 rlwinm r3, r3, 32 - 15, _PAGE_RW /* DSISR_STORE -> _PAGE_RW */
735 mfspr r10, SPRN_SPRG_THREAD
736 restore_regs_thread r10
737 b .Lhash_page_dsi_cont
741 mfspr r10, SPRN_SPRG_THREAD
747 mfspr r10, SPRN_SPRG_THREAD
748 restore_regs_thread r10
750 b .Lhash_page_isi_cont
752 .globl fast_hash_page_return
753 fast_hash_page_return:
754 andis. r10, r9, SRR1_ISI_NOPT@h /* Set on ISI, cleared on DSI */
755 mfspr r10, SPRN_SPRG_THREAD
756 restore_regs_thread r10
762 mfspr r10, SPRN_SPRG_SCRATCH2
767 mfspr r11, SPRN_SPRG_SCRATCH1
768 mfspr r10, SPRN_SPRG_SCRATCH0
770 #endif /* CONFIG_PPC_BOOK3S_604 */
773 vmap_stack_overflow_exception
778 #ifdef CONFIG_ALTIVEC
780 bl load_up_altivec /* if from user, just load it up */
781 b fast_exception_return
782 #endif /* CONFIG_ALTIVEC */
783 1: addi r3,r1,STACK_FRAME_OVERHEAD
784 EXC_XFER_LITE(0xf20, altivec_unavailable_exception)
788 addi r3,r1,STACK_FRAME_OVERHEAD
789 EXC_XFER_STD(0xf00, performance_monitor_exception)
793 * This code is jumped to from the startup code to copy
794 * the kernel image to physical address PHYSICAL_START.
797 addis r9,r26,klimit@ha /* fetch klimit */
799 addis r25,r25,-KERNELBASE@h
800 lis r3,PHYSICAL_START@h /* Destination base address */
801 li r6,0 /* Destination offset */
802 li r5,0x4000 /* # bytes of memory to copy */
803 bl copy_and_flush /* copy the first 0x4000 bytes */
804 addi r0,r3,4f@l /* jump to the address of 4f */
805 mtctr r0 /* in copy and do the rest. */
806 bctr /* jump to the copy */
808 bl copy_and_flush /* copy the rest */
812 * Copy routine used to copy the kernel to start at physical address 0
813 * and flush and invalidate the caches as needed.
814 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
815 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
817 _ENTRY(copy_and_flush)
820 4: li r0,L1_CACHE_BYTES/4
822 3: addi r6,r6,4 /* copy a cache line */
826 dcbst r6,r3 /* write it to memory */
828 icbi r6,r3 /* flush the icache line */
831 sync /* additional sync needed on g4 */
838 .globl __secondary_start_mpc86xx
839 __secondary_start_mpc86xx:
841 stw r3, __secondary_hold_acknowledge@l(0)
842 mr r24, r3 /* cpu # */
845 .globl __secondary_start_pmac_0
846 __secondary_start_pmac_0:
847 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
856 /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
857 set to map the 0xf0000000 - 0xffffffff region */
859 rlwinm r0,r0,0,28,26 /* clear DR (0x10) */
863 .globl __secondary_start
865 /* Copy some CPU settings from CPU 0 */
866 bl __restore_cpu_setup
870 bl call_setup_cpu /* Call setup_cpu for this CPU */
874 /* get current's stack and current */
875 lis r2,secondary_current@ha
877 lwz r2,secondary_current@l(r2)
879 lwz r1,TASK_STACK(r1)
882 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
887 /* load up the MMU */
888 bl load_segment_registers
891 /* ptr to phys current thread */
893 addi r4,r4,THREAD /* phys address of our thread_struct */
894 mtspr SPRN_SPRG_THREAD,r4
895 BEGIN_MMU_FTR_SECTION
896 lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
897 ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
898 rlwinm r4, r4, 4, 0xffff01ff
900 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_HPTE_TABLE)
902 /* enable MMU and jump to start_secondary */
904 lis r3,start_secondary@h
905 ori r3,r3,start_secondary@l
909 #endif /* CONFIG_SMP */
911 #ifdef CONFIG_KVM_BOOK3S_HANDLER
912 #include "../kvm/book3s_rmhandlers.S"
916 * Load stuff into the MMU. Intended to be called with
920 sync /* Force all PTE updates to finish */
922 tlbia /* Clear all TLB entries */
923 sync /* wait for tlbia/tlbie to finish */
924 TLBSYNC /* ... on all CPUs */
925 /* Load the SDR1 register (hash table base & size) */
926 lis r6, early_hash - PAGE_OFFSET@h
927 ori r6, r6, 3 /* 256kB table */
932 sync /* Force all PTE updates to finish */
934 tlbia /* Clear all TLB entries */
935 sync /* wait for tlbia/tlbie to finish */
936 TLBSYNC /* ... on all CPUs */
937 BEGIN_MMU_FTR_SECTION
938 /* Load the SDR1 register (hash table base & size) */
943 END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
945 /* Load the BAT registers with the values set up by MMU_init. */
953 BEGIN_MMU_FTR_SECTION
958 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
961 _GLOBAL(load_segment_registers)
962 li r0, NUM_USER_SEGMENTS /* load up user segment register values */
963 mtctr r0 /* for context 0 */
964 li r3, 0 /* Kp = 0, Ks = 0, VSID = 0 */
965 #ifdef CONFIG_PPC_KUEP
966 oris r3, r3, SR_NX@h /* Set Nx */
968 #ifdef CONFIG_PPC_KUAP
969 oris r3, r3, SR_KS@h /* Set Ks */
973 addi r3, r3, 0x111 /* increment VSID */
974 addis r4, r4, 0x1000 /* address of next segment */
976 li r0, 16 - NUM_USER_SEGMENTS /* load up kernel segment registers */
977 mtctr r0 /* for context 0 */
978 rlwinm r3, r3, 0, ~SR_NX /* Nx = 0 */
979 rlwinm r3, r3, 0, ~SR_KS /* Ks = 0 */
980 oris r3, r3, SR_KP@h /* Kp = 1 */
982 addi r3, r3, 0x111 /* increment VSID */
983 addis r4, r4, 0x1000 /* address of next segment */
988 * This is where the main kernel code starts.
993 ori r2,r2,init_task@l
994 /* Set up for using our exception vectors */
995 /* ptr to phys current thread */
997 addi r4,r4,THREAD /* init task's THREAD */
998 mtspr SPRN_SPRG_THREAD,r4
999 BEGIN_MMU_FTR_SECTION
1000 lis r4, (swapper_pg_dir - PAGE_OFFSET)@h
1001 ori r4, r4, (swapper_pg_dir - PAGE_OFFSET)@l
1002 rlwinm r4, r4, 4, 0xffff01ff
1004 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_HPTE_TABLE)
1007 lis r1,init_thread_union@ha
1008 addi r1,r1,init_thread_union@l
1010 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
1012 * Do early platform-specific initialization,
1013 * and set up the MMU.
1023 bl MMU_init_hw_patch
1026 * Go back to running unmapped so we can load up new values
1027 * for SDR1 (hash table pointer) and the segment registers
1028 * and change to using our exception vectors.
1033 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
1039 /* Load up the kernel context */
1042 #ifdef CONFIG_BDI_SWITCH
1043 /* Add helper information for the Abatron bdiGDB debugger.
1044 * We do this here because we know the mmu is disabled, and
1045 * will be enabled for real in just a few instructions.
1047 lis r5, abatron_pteptrs@h
1048 ori r5, r5, abatron_pteptrs@l
1049 stw r5, 0xf0(0) /* This much match your Abatron config */
1050 lis r6, swapper_pg_dir@h
1051 ori r6, r6, swapper_pg_dir@l
1054 #endif /* CONFIG_BDI_SWITCH */
1056 /* Now turn on the MMU for real! */
1058 lis r3,start_kernel@h
1059 ori r3,r3,start_kernel@l
1065 * void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next);
1067 * Set up the segment registers for a new context.
1069 _ENTRY(switch_mmu_context)
1070 lwz r3,MMCONTEXTID(r4)
1073 mulli r3,r3,897 /* multiply context by skew factor */
1074 rlwinm r3,r3,4,8,27 /* VSID = (context & 0xfffff) << 4 */
1075 #ifdef CONFIG_PPC_KUEP
1076 oris r3, r3, SR_NX@h /* Set Nx */
1078 #ifdef CONFIG_PPC_KUAP
1079 oris r3, r3, SR_KS@h /* Set Ks */
1081 li r0,NUM_USER_SEGMENTS
1084 #ifdef CONFIG_BDI_SWITCH
1085 /* Context switch the PTE pointer for the Abatron BDI2000.
1086 * The PGDIR is passed as second argument.
1089 lis r5, abatron_pteptrs@ha
1090 stw r4, abatron_pteptrs@l + 0x4(r5)
1092 BEGIN_MMU_FTR_SECTION
1093 #ifndef CONFIG_BDI_SWITCH
1097 rlwinm r4, r4, 4, 0xffff01ff
1099 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_HPTE_TABLE)
1104 addi r3,r3,0x111 /* next VSID */
1105 rlwinm r3,r3,0,8,3 /* clear out any overflow from VSID field */
1106 addis r4,r4,0x1000 /* address of next segment */
1112 EMIT_BUG_ENTRY 4b,__FILE__,__LINE__,0
1114 EXPORT_SYMBOL(switch_mmu_context)
1117 * An undocumented "feature" of 604e requires that the v bit
1118 * be cleared before changing BAT values.
1120 * Also, newer IBM firmware does not clear bat3 and 4 so
1121 * this makes sure it's done.
1127 mtspr SPRN_DBAT0U,r10
1128 mtspr SPRN_DBAT0L,r10
1129 mtspr SPRN_DBAT1U,r10
1130 mtspr SPRN_DBAT1L,r10
1131 mtspr SPRN_DBAT2U,r10
1132 mtspr SPRN_DBAT2L,r10
1133 mtspr SPRN_DBAT3U,r10
1134 mtspr SPRN_DBAT3L,r10
1135 mtspr SPRN_IBAT0U,r10
1136 mtspr SPRN_IBAT0L,r10
1137 mtspr SPRN_IBAT1U,r10
1138 mtspr SPRN_IBAT1L,r10
1139 mtspr SPRN_IBAT2U,r10
1140 mtspr SPRN_IBAT2L,r10
1141 mtspr SPRN_IBAT3U,r10
1142 mtspr SPRN_IBAT3L,r10
1143 BEGIN_MMU_FTR_SECTION
1144 /* Here's a tweak: at this point, CPU setup have
1145 * not been called yet, so HIGH_BAT_EN may not be
1146 * set in HID0 for the 745x processors. However, it
1147 * seems that doesn't affect our ability to actually
1148 * write to these SPRs.
1150 mtspr SPRN_DBAT4U,r10
1151 mtspr SPRN_DBAT4L,r10
1152 mtspr SPRN_DBAT5U,r10
1153 mtspr SPRN_DBAT5L,r10
1154 mtspr SPRN_DBAT6U,r10
1155 mtspr SPRN_DBAT6L,r10
1156 mtspr SPRN_DBAT7U,r10
1157 mtspr SPRN_DBAT7L,r10
1158 mtspr SPRN_IBAT4U,r10
1159 mtspr SPRN_IBAT4L,r10
1160 mtspr SPRN_IBAT5U,r10
1161 mtspr SPRN_IBAT5L,r10
1162 mtspr SPRN_IBAT6U,r10
1163 mtspr SPRN_IBAT6L,r10
1164 mtspr SPRN_IBAT7U,r10
1165 mtspr SPRN_IBAT7L,r10
1166 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1175 li r3, MSR_KERNEL & ~(MSR_IR | MSR_DR)
1176 rlwinm r0, r6, 0, ~MSR_RI
1177 rlwinm r0, r0, 0, ~MSR_EE
1188 LOAD_BAT(0, r3, r4, r5)
1189 LOAD_BAT(1, r3, r4, r5)
1190 LOAD_BAT(2, r3, r4, r5)
1191 LOAD_BAT(3, r3, r4, r5)
1192 BEGIN_MMU_FTR_SECTION
1193 LOAD_BAT(4, r3, r4, r5)
1194 LOAD_BAT(5, r3, r4, r5)
1195 LOAD_BAT(6, r3, r4, r5)
1196 LOAD_BAT(7, r3, r4, r5)
1197 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
1198 li r3, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI)
1206 1: addic. r10, r10, -0x1000
1213 addi r4, r3, __after_mmu_off - _start
1215 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1225 /* We use one BAT to map up to 256M of RAM at _PAGE_OFFSET */
1227 lis r11,PAGE_OFFSET@h
1230 ori r8,r8,0x12 /* R/W access, M=1 */
1232 ori r8,r8,2 /* R/W access */
1233 #endif /* CONFIG_SMP */
1234 ori r11,r11,BL_256M<<2|0x2 /* set up BAT registers for 604 */
1236 mtspr SPRN_DBAT0L,r8 /* N.B. 6xx have valid */
1237 mtspr SPRN_DBAT0U,r11 /* bit in upper BAT register */
1238 mtspr SPRN_IBAT0L,r8
1239 mtspr SPRN_IBAT0U,r11
1243 #ifdef CONFIG_BOOTX_TEXT
1246 * setup the display bat prepared for us in prom.c
1251 addis r8,r3,disp_BAT@ha
1252 addi r8,r8,disp_BAT@l
1257 mtspr SPRN_DBAT3L,r8
1258 mtspr SPRN_DBAT3U,r11
1260 #endif /* CONFIG_BOOTX_TEXT */
1262 #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
1266 mtspr SPRN_DBAT1L, r8
1269 ori r11, r11, (BL_1M << 2) | 2
1270 mtspr SPRN_DBAT1U, r11
1275 #ifdef CONFIG_PPC_EARLY_DEBUG_USBGECKO
1277 /* prepare a BAT for early io */
1278 #if defined(CONFIG_GAMECUBE)
1280 #elif defined(CONFIG_WII)
1283 #error Invalid platform for USB Gecko based early debugging.
1286 * The virtual address used must match the virtual address
1287 * associated to the fixmap entry FIX_EARLY_DEBUG_BASE.
1289 lis r11, 0xfffe /* top 128K */
1290 ori r8, r8, 0x002a /* uncached, guarded ,rw */
1291 ori r11, r11, 0x2 /* 128K, Vs=1, Vp=0 */
1292 mtspr SPRN_DBAT1L, r8
1293 mtspr SPRN_DBAT1U, r11
1298 /* Jump into the system reset for the rom.
1299 * We first disable the MMU, and then jump to the ROM reset address.
1301 * r3 is the board info structure, r4 is the location for starting.
1302 * I use this for building a small kernel that can load other kernels,
1303 * rather than trying to write or rely on a rom monitor that can tftp load.
1308 rlwinm r0,r0,0,17,15 /* clear MSR_EE in r0 */
1312 mfspr r11, SPRN_HID0
1314 ori r10,r10,HID0_ICE|HID0_DCE
1316 mtspr SPRN_HID0, r11
1318 li r5, MSR_ME|MSR_RI
1320 addis r6,r6,-KERNELBASE@h
1334 * We put a few things here that have to be page-aligned.
1335 * This stuff goes at the beginning of the data segment,
1336 * which is page-aligned.
1341 .globl empty_zero_page
1344 EXPORT_SYMBOL(empty_zero_page)
1346 .globl swapper_pg_dir
1348 .space PGD_TABLE_SIZE
1350 /* Room for two PTE pointers, usually the kernel and current user pointers
1351 * to their respective root page table.