1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications by Dan Malek
11 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
13 * This file contains low-level support and setup for PowerPC 8xx
14 * embedded processors, including trap and interrupt dispatch.
17 #include <linux/init.h>
18 #include <asm/processor.h>
21 #include <asm/cache.h>
22 #include <asm/pgtable.h>
23 #include <asm/cputable.h>
24 #include <asm/thread_info.h>
25 #include <asm/ppc_asm.h>
26 #include <asm/asm-offsets.h>
27 #include <asm/ptrace.h>
28 #include <asm/export.h>
29 #include <asm/code-patching-asm.h>
33 #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
34 /* By simply checking Address >= 0x80000000, we know if its a kernel address */
35 #define SIMPLE_KERNEL_ADDRESS 1
39 * We need an ITLB miss handler for kernel addresses if:
40 * - Either we have modules
41 * - Or we have not pinned the first 8M
43 #if defined(CONFIG_MODULES) || !defined(CONFIG_PIN_TLB_TEXT) || \
44 defined(CONFIG_DEBUG_PAGEALLOC)
45 #define ITLB_MISS_KERNEL 1
49 * Value for the bits that have fixed value in RPN entries.
50 * Also used for tagging DAR for DTLBerror.
52 #define RPN_PATTERN 0x00f0
54 #define PAGE_SHIFT_512K 19
55 #define PAGE_SHIFT_8M 23
62 * This port was done on an MBX board with an 860. Right now I only
63 * support an ELF compressed (zImage) boot from EPPC-Bug because the
64 * code there loads up some registers before calling us:
65 * r3: ptr to board info data
66 * r4: initrd_start or if no initrd then 0
67 * r5: initrd_end - unused if r4 is 0
68 * r6: Start of command line string
69 * r7: End of command line string
71 * I decided to use conditional compilation instead of checking PVR and
72 * adding more processor specific branches around code I don't need.
73 * Since this is an embedded processor, I also appreciate any memory
76 * The MPC8xx does not have any BATs, but it supports large page sizes.
77 * We first initialize the MMU to support 8M byte pages, then load one
78 * entry into each of the instruction and data TLBs to map the first
79 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
80 * the "internal" processor registers before MMU_init is called.
86 mr r31,r3 /* save device tree ptr */
88 /* We have to turn on the MMU right away so we get cache modes
93 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
99 ori r0,r0,MSR_DR|MSR_IR
102 ori r0,r0,start_here@l
104 rfi /* enables MMU */
107 #ifdef CONFIG_PERF_EVENTS
110 .globl itlb_miss_counter
114 .globl dtlb_miss_counter
118 .globl instruction_counter
124 EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD)
133 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
136 addi r3,r1,STACK_FRAME_OVERHEAD
137 EXC_XFER_STD(0x200, machine_check_exception)
139 /* Data access exception.
140 * This is "never generated" by the MPC8xx.
145 /* Instruction access exception.
146 * This is "never generated" by the MPC8xx.
151 /* External interrupt */
152 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
154 /* Alignment exception */
161 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
164 addi r3,r1,STACK_FRAME_OVERHEAD
165 EXC_XFER_STD(0x600, alignment_exception)
167 /* Program check exception */
168 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
170 /* No FPU on MPC8xx. This exception is not supposed to happen.
172 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
175 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
177 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_STD)
178 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_STD)
185 /* Single step - not used on 601 */
186 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
187 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_STD)
188 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_STD)
190 /* On the MPC8xx, this is a software emulation interrupt. It occurs
191 * for all unimplemented and illegal instructions.
193 EXCEPTION(0x1000, SoftEmu, program_check_exception, EXC_XFER_STD)
195 /* Called from DataStoreTLBMiss when perf TLB misses events are activated */
196 #ifdef CONFIG_PERF_EVENTS
197 patch_site 0f, patch__dtlbmiss_perf
198 0: lwz r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
200 stw r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
201 mfspr r10, SPRN_SPRG_SCRATCH0
202 mfspr r11, SPRN_SPRG_SCRATCH1
208 * For the MPC8xx, this is a software tablewalk to load the instruction
209 * TLB. The task switch loads the M_TWB register with the pointer to the first
211 * If we discover there is no second level table (value is zero) or if there
212 * is an invalid pte, we load that into the TLB, which causes another fault
213 * into the TLB Error interrupt where we can handle such problems.
214 * We have to use the MD_xxx registers for the tablewalk because the
215 * equivalent MI_xxx registers only perform the attribute functions.
218 #ifdef CONFIG_8xx_CPU15
219 #define INVALIDATE_ADJACENT_PAGES_CPU15(addr) \
220 addi addr, addr, PAGE_SIZE; \
222 addi addr, addr, -(PAGE_SIZE << 1); \
224 addi addr, addr, PAGE_SIZE
226 #define INVALIDATE_ADJACENT_PAGES_CPU15(addr)
230 mtspr SPRN_SPRG_SCRATCH0, r10
231 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
232 mtspr SPRN_SPRG_SCRATCH1, r11
235 /* If we are faulting a kernel address, we have to use the
236 * kernel page tables.
238 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
239 INVALIDATE_ADJACENT_PAGES_CPU15(r10)
240 mtspr SPRN_MD_EPN, r10
241 /* Only modules will cause ITLB Misses as we always
242 * pin the first 8MB of kernel memory */
243 #ifdef ITLB_MISS_KERNEL
245 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
246 cmpi cr0, r10, 0 /* Address >= 0x80000000 */
248 rlwinm r10, r10, 16, 0xfff8
249 cmpli cr0, r10, PAGE_OFFSET@h
250 #ifndef CONFIG_PIN_TLB_TEXT
251 /* It is assumed that kernel code fits into the first 32M */
252 0: cmpli cr7, r10, (PAGE_OFFSET + 0x2000000)@h
253 patch_site 0b, patch__itlbmiss_linmem_top
257 mfspr r10, SPRN_M_TWB /* Get level 1 table */
258 #ifdef ITLB_MISS_KERNEL
259 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
264 #ifndef CONFIG_PIN_TLB_TEXT
265 blt cr7, ITLBMissLinear
267 rlwinm r10, r10, 0, 20, 31
268 oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
271 lwz r10, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
272 mtspr SPRN_MI_TWC, r10 /* Set segment attributes */
274 mtspr SPRN_MD_TWC, r10
275 mfspr r10, SPRN_MD_TWC
276 lwz r10, 0(r10) /* Get the pte */
277 #ifdef ITLB_MISS_KERNEL
281 rlwinm r11, r10, 32-5, _PAGE_PRESENT
283 rlwimi r10, r11, 0, _PAGE_PRESENT
285 /* The Linux PTE won't go exactly into the MMU TLB.
286 * Software indicator bits 20 and 23 must be clear.
287 * Software indicator bits 22, 24, 25, 26, and 27 must be
288 * set. All other Linux PTE bits control the behavior
291 rlwimi r10, r10, 0, 0x0f00 /* Clear bits 20-23 */
292 rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
293 ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */
294 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
296 /* Restore registers */
297 0: mfspr r10, SPRN_SPRG_SCRATCH0
298 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
299 mfspr r11, SPRN_SPRG_SCRATCH1
302 patch_site 0b, patch__itlbmiss_exit_1
304 #ifdef CONFIG_PERF_EVENTS
305 patch_site 0f, patch__itlbmiss_perf
306 0: lwz r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
308 stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
309 mfspr r10, SPRN_SPRG_SCRATCH0
310 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_SWAP)
311 mfspr r11, SPRN_SPRG_SCRATCH1
316 #ifndef CONFIG_PIN_TLB_TEXT
319 #if defined(CONFIG_STRICT_KERNEL_RWX) && CONFIG_ETEXT_SHIFT < 23
320 patch_site 0f, patch__itlbmiss_linmem_top8
323 0: subis r11, r10, (PAGE_OFFSET - 0x80000000)@ha
324 rlwinm r11, r11, 4, MI_PS8MEG ^ MI_PS512K
325 ori r11, r11, MI_PS512K | MI_SVALID
326 rlwinm r10, r10, 0, 0x0ff80000 /* 8xx supports max 256Mb RAM */
328 /* Set 8M byte page and mark it valid */
329 li r11, MI_PS8MEG | MI_SVALID
330 rlwinm r10, r10, 20, 0x0f800000 /* 8xx supports max 256Mb RAM */
332 mtspr SPRN_MI_TWC, r11
333 ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
335 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
337 0: mfspr r10, SPRN_SPRG_SCRATCH0
338 mfspr r11, SPRN_SPRG_SCRATCH1
340 patch_site 0b, patch__itlbmiss_exit_2
345 mtspr SPRN_SPRG_SCRATCH0, r10
346 mtspr SPRN_SPRG_SCRATCH1, r11
349 /* If we are faulting a kernel address, we have to use the
350 * kernel page tables.
352 mfspr r10, SPRN_MD_EPN
353 rlwinm r10, r10, 16, 0xfff8
354 cmpli cr0, r10, PAGE_OFFSET@h
355 #ifndef CONFIG_PIN_TLB_IMMR
356 cmpli cr6, r10, VIRT_IMMR_BASE@h
358 0: cmpli cr7, r10, (PAGE_OFFSET + 0x2000000)@h
359 patch_site 0b, patch__dtlbmiss_linmem_top
361 mfspr r10, SPRN_M_TWB /* Get level 1 table */
363 #ifndef CONFIG_PIN_TLB_IMMR
364 0: beq- cr6, DTLBMissIMMR
365 patch_site 0b, patch__dtlbmiss_immr_jmp
367 blt cr7, DTLBMissLinear
368 rlwinm r10, r10, 0, 20, 31
369 oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
372 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
374 mtspr SPRN_MD_TWC, r11
375 mfspr r10, SPRN_MD_TWC
376 lwz r10, 0(r10) /* Get the pte */
378 /* Insert the Guarded flag into the TWC from the Linux PTE.
379 * It is bit 27 of both the Linux PTE and the TWC (at least
380 * I got that right :-). It will be better when we can put
381 * this into the Linux pgd/pmd and load it in the operation
384 rlwimi r11, r10, 0, _PAGE_GUARDED
385 mtspr SPRN_MD_TWC, r11
387 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
388 * We also need to know if the insn is a load/store, so:
389 * Clear _PAGE_PRESENT and load that which will
390 * trap into DTLB Error with store bit set accordinly.
392 /* PRESENT=0x1, ACCESSED=0x20
393 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
394 * r10 = (r10 & ~PRESENT) | r11;
397 rlwinm r11, r10, 32-5, _PAGE_PRESENT
399 rlwimi r10, r11, 0, _PAGE_PRESENT
401 /* The Linux PTE won't go exactly into the MMU TLB.
402 * Software indicator bits 24, 25, 26, and 27 must be
403 * set. All other Linux PTE bits control the behavior
407 rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */
408 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
410 /* Restore registers */
411 mtspr SPRN_DAR, r11 /* Tag DAR */
413 0: mfspr r10, SPRN_SPRG_SCRATCH0
414 mfspr r11, SPRN_SPRG_SCRATCH1
416 patch_site 0b, patch__dtlbmiss_exit_1
420 /* Set 512k byte guarded page and mark it valid */
421 li r10, MD_PS512K | MD_GUARDED | MD_SVALID
422 mtspr SPRN_MD_TWC, r10
423 mfspr r10, SPRN_IMMR /* Get current IMMR */
424 rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
425 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
426 _PAGE_PRESENT | _PAGE_NO_CACHE
427 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
430 mtspr SPRN_DAR, r11 /* Tag DAR */
432 0: mfspr r10, SPRN_SPRG_SCRATCH0
433 mfspr r11, SPRN_SPRG_SCRATCH1
435 patch_site 0b, patch__dtlbmiss_exit_2
439 rlwinm r10, r10, 20, 0x0f800000 /* 8xx supports max 256Mb RAM */
440 #if defined(CONFIG_STRICT_KERNEL_RWX) && CONFIG_DATA_SHIFT < 23
441 patch_site 0f, patch__dtlbmiss_romem_top8
443 0: subis r11, r10, (PAGE_OFFSET - 0x80000000)@ha
444 rlwinm r11, r11, 0, 0xff800000
447 rlwinm r11, r11, 4, MI_PS8MEG ^ MI_PS512K
448 ori r11, r11, MI_PS512K | MI_SVALID
449 mfspr r10, SPRN_MD_EPN
450 rlwinm r10, r10, 0, 0x0ff80000 /* 8xx supports max 256Mb RAM */
452 /* Set 8M byte page and mark it valid */
453 li r11, MD_PS8MEG | MD_SVALID
455 mtspr SPRN_MD_TWC, r11
456 #ifdef CONFIG_STRICT_KERNEL_RWX
457 patch_site 0f, patch__dtlbmiss_romem_top
460 rlwimi r10, r11, 11, _PAGE_RO
462 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
464 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
467 mtspr SPRN_DAR, r11 /* Tag DAR */
469 0: mfspr r10, SPRN_SPRG_SCRATCH0
470 mfspr r11, SPRN_SPRG_SCRATCH1
472 patch_site 0b, patch__dtlbmiss_exit_3
474 /* This is an instruction TLB error on the MPC8xx. This could be due
475 * to many reasons, such as executing guarded memory or illegal instruction
476 * addresses. There is nothing to do but handle a big time error fault.
482 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
483 andis. r10,r9,SRR1_ISI_NOPT@h
486 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
488 EXC_XFER_LITE(0x400, handle_page_fault)
490 /* This is the data TLB error on the MPC8xx. This could be due to
491 * many reasons, including a dirty update to a pte. We bail out to
492 * a higher level function that can handle it.
496 mtspr SPRN_SPRG_SCRATCH0, r10
497 mtspr SPRN_SPRG_SCRATCH1, r11
501 cmpwi cr0, r11, RPN_PATTERN
502 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
503 DARFixed:/* Return from dcbx instruction bug workaround */
509 andis. r10,r5,DSISR_NOHPTE@h
514 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
515 /* 0x300 is DataAccess exception, needed by bad_page_fault() */
516 EXC_XFER_LITE(0x300, handle_page_fault)
518 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_STD)
519 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_STD)
520 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_STD)
521 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_STD)
522 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_STD)
523 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_STD)
524 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_STD)
526 /* On the MPC8xx, these next four traps are used for development
527 * support of breakpoints and such. Someday I will get around to
532 mtspr SPRN_SPRG_SCRATCH0, r10
533 mtspr SPRN_SPRG_SCRATCH1, r11
536 cmplwi cr0, r11, (.Ldtlbie - PAGE_OFFSET)@l
537 cmplwi cr7, r11, (.Litlbie - PAGE_OFFSET)@l
542 addi r3,r1,STACK_FRAME_OVERHEAD
546 EXC_XFER_STD(0x1c00, do_break)
549 mfspr r10, SPRN_SPRG_SCRATCH0
550 mfspr r11, SPRN_SPRG_SCRATCH1
553 #ifdef CONFIG_PERF_EVENTS
555 InstructionBreakpoint:
556 mtspr SPRN_SPRG_SCRATCH0, r10
557 lwz r10, (instruction_counter - PAGE_OFFSET)@l(0)
559 stw r10, (instruction_counter - PAGE_OFFSET)@l(0)
562 mtspr SPRN_COUNTA, r10
563 mfspr r10, SPRN_SPRG_SCRATCH0
566 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_STD)
568 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_STD)
569 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_STD)
573 /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
574 * by decoding the registers used by the dcbx instruction and adding them.
575 * DAR is set to the calculated address.
577 /* define if you don't want to use self modifying code */
578 #define NO_SELF_MODIFYING_CODE
579 FixupDAR:/* Entry point for dcbx workaround. */
581 /* fetch instruction from memory. */
583 mtspr SPRN_MD_EPN, r10
584 rlwinm r11, r10, 16, 0xfff8
585 cmpli cr0, r11, PAGE_OFFSET@h
586 mfspr r11, SPRN_M_TWB /* Get level 1 table */
588 rlwinm r11, r10, 16, 0xfff8
590 0: cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
591 patch_site 0b, patch__fixupdar_linmem_top
593 /* create physical page address from effective address */
596 mfspr r11, SPRN_M_TWB /* Get level 1 table */
597 rlwinm r11, r11, 0, 20, 31
598 oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha
600 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
601 mtspr SPRN_MD_TWC, r11
603 mfspr r11, SPRN_MD_TWC
604 lwz r11, 0(r11) /* Get the pte */
605 bt 28,200f /* bit 28 = Large page (8M) */
606 bt 29,202f /* bit 29 = Large page (8M or 512K) */
607 /* concat physical page address(r11) and page offset(r10) */
608 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
610 /* Check if it really is a dcbx instruction. */
611 /* dcbt and dcbtst does not generate DTLB Misses/Errors,
612 * no need to include them here */
613 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
614 rlwinm r10, r10, 0, 21, 5
615 cmpwi cr0, r10, 2028 /* Is dcbz? */
617 cmpwi cr0, r10, 940 /* Is dcbi? */
619 cmpwi cr0, r10, 108 /* Is dcbst? */
620 beq+ 144f /* Fix up store bit! */
621 cmpwi cr0, r10, 172 /* Is dcbf? */
623 cmpwi cr0, r10, 1964 /* Is icbi? */
625 141: mfspr r10,SPRN_M_TW
626 b DARFixed /* Nope, go back to normal TLB processing */
629 /* concat physical page address(r11) and page offset(r10) */
630 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31
634 /* concat physical page address(r11) and page offset(r10) */
635 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_512K, 31
638 144: mfspr r10, SPRN_DSISR
639 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
640 mtspr SPRN_DSISR, r10
641 142: /* continue, it was a dcbx, dcbi instruction. */
642 #ifndef NO_SELF_MODIFYING_CODE
643 andis. r10,r11,0x1f /* test if reg RA is r0 */
644 li r10,modified_instr@l
645 dcbtst r0,r10 /* touch for store */
646 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
647 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
649 stw r11,0(r10) /* store add/and instruction */
650 dcbf 0,r10 /* flush new instr. to memory. */
651 icbi 0,r10 /* invalidate instr. cache line */
652 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
653 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
654 isync /* Wait until new instr is loaded from memory */
656 .space 4 /* this is where the add instr. is stored */
658 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
659 143: mtdar r10 /* store faulting EA in DAR */
661 b DARFixed /* Go back to normal TLB handling */
664 mtdar r10 /* save ctr reg in DAR */
665 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
666 addi r10, r10, 150f@l /* add start of table */
667 mtctr r10 /* load ctr with jump address */
668 xor r10, r10, r10 /* sum starts at zero */
669 bctr /* jump into table */
671 add r10, r10, r0 ;b 151f
672 add r10, r10, r1 ;b 151f
673 add r10, r10, r2 ;b 151f
674 add r10, r10, r3 ;b 151f
675 add r10, r10, r4 ;b 151f
676 add r10, r10, r5 ;b 151f
677 add r10, r10, r6 ;b 151f
678 add r10, r10, r7 ;b 151f
679 add r10, r10, r8 ;b 151f
680 add r10, r10, r9 ;b 151f
681 mtctr r11 ;b 154f /* r10 needs special handling */
682 mtctr r11 ;b 153f /* r11 needs special handling */
683 add r10, r10, r12 ;b 151f
684 add r10, r10, r13 ;b 151f
685 add r10, r10, r14 ;b 151f
686 add r10, r10, r15 ;b 151f
687 add r10, r10, r16 ;b 151f
688 add r10, r10, r17 ;b 151f
689 add r10, r10, r18 ;b 151f
690 add r10, r10, r19 ;b 151f
691 add r10, r10, r20 ;b 151f
692 add r10, r10, r21 ;b 151f
693 add r10, r10, r22 ;b 151f
694 add r10, r10, r23 ;b 151f
695 add r10, r10, r24 ;b 151f
696 add r10, r10, r25 ;b 151f
697 add r10, r10, r26 ;b 151f
698 add r10, r10, r27 ;b 151f
699 add r10, r10, r28 ;b 151f
700 add r10, r10, r29 ;b 151f
701 add r10, r10, r30 ;b 151f
704 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */
705 beq 152f /* if reg RA is zero, don't add it */
706 addi r11, r11, 150b@l /* add start of table */
707 mtctr r11 /* load ctr with jump address */
708 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
709 bctr /* jump into table */
712 mtctr r11 /* restore ctr reg from DAR */
713 mtdar r10 /* save fault EA to DAR */
715 b DARFixed /* Go back to normal TLB handling */
717 /* special handling for r10,r11 since these are modified already */
718 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
719 add r10, r10, r11 /* add it */
720 mfctr r11 /* restore r11 */
722 154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
723 add r10, r10, r11 /* add it */
724 mfctr r11 /* restore r11 */
729 * This is where the main kernel code starts.
734 ori r2,r2,init_task@l
736 /* ptr to phys current thread */
738 addi r4,r4,THREAD /* init task's THREAD */
739 mtspr SPRN_SPRG_THREAD,r4
742 lis r1,init_thread_union@ha
743 addi r1,r1,init_thread_union@l
745 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
747 lis r6, swapper_pg_dir@ha
751 bl early_init /* We have to do this with MMU on */
754 * Decide what sort of machine this is and initialize the MMU.
765 * Go back to running unmapped so we can load up new values
766 * and change to using our exception vectors.
767 * On the 8xx, all we have to do is invalidate the TLB to clear
768 * the old 8M byte TLB mappings and load the page table base register.
770 /* The right way to do this would be to track it down through
771 * init's THREAD like the context switch code does, but this is
772 * easier......until someone changes init's static structures.
777 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
781 /* Load up the kernel context */
783 tlbia /* Clear all TLB entries */
784 sync /* wait for tlbia/tlbie to finish */
786 /* set up the PTE pointers for the Abatron bdiGDB.
788 lis r5, abatron_pteptrs@h
789 ori r5, r5, abatron_pteptrs@l
790 stw r5, 0xf0(0) /* Must match your Abatron config file */
792 lis r6, swapper_pg_dir@h
793 ori r6, r6, swapper_pg_dir@l
796 /* Now turn on the MMU for real! */
798 lis r3,start_kernel@h
799 ori r3,r3,start_kernel@l
802 rfi /* enable MMU and jump to start_kernel */
804 /* Set up the initial MMU state so we can do the first level of
805 * kernel initialization. This maps the first 8 MBytes of memory 1:1
806 * virtual to physical. Also, set the cache mode since that is defined
807 * by TLB entries and perform any additional mapping (like of the IMMR).
808 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
809 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by
810 * these mappings is mapped by page tables.
814 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */
815 lis r10, MD_RESETVAL@h
816 #ifndef CONFIG_8xx_COPYBACK
817 oris r10, r10, MD_WTDEF@h
819 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */
821 tlbia /* Invalidate all TLB entries */
822 #ifdef CONFIG_PIN_TLB_DATA
823 oris r10, r10, MD_RSV4I@h
824 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
827 lis r8, MI_APG_INIT@h /* Set protection modes */
828 ori r8, r8, MI_APG_INIT@l
830 lis r8, MD_APG_INIT@h
831 ori r8, r8, MD_APG_INIT@l
834 /* Map a 512k page for the IMMR to get the processor
835 * internal registers (among other things).
837 #ifdef CONFIG_PIN_TLB_IMMR
838 oris r10, r10, MD_RSV4I@h
840 mtspr SPRN_MD_CTR, r10
842 mfspr r9, 638 /* Get current IMMR */
843 andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */
845 lis r8, VIRT_IMMR_BASE@h /* Create vaddr for TLB */
846 ori r8, r8, MD_EVALID /* Mark it valid */
847 mtspr SPRN_MD_EPN, r8
848 li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */
849 ori r8, r8, MD_SVALID /* Make it valid */
850 mtspr SPRN_MD_TWC, r8
851 mr r8, r9 /* Create paddr for TLB */
852 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
853 mtspr SPRN_MD_RPN, r8
856 /* Now map the lower RAM (up to 32 Mbytes) into the ITLB. */
857 #ifdef CONFIG_PIN_TLB_TEXT
861 li r9, 4 /* up to 4 pages of 8M */
863 lis r9, KERNELBASE@h /* Create vaddr for TLB */
864 li r10, MI_PS8MEG | MI_SVALID /* Set 8M byte page */
865 li r11, MI_BOOTINIT /* Create RPN for address 0 */
866 lis r12, _einittext@h
867 ori r12, r12, _einittext@l
869 #ifdef CONFIG_PIN_TLB_TEXT
870 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
874 ori r0, r9, MI_EVALID /* Mark it valid */
875 mtspr SPRN_MI_EPN, r0
876 mtspr SPRN_MI_TWC, r10
877 mtspr SPRN_MI_RPN, r11 /* Store TLB entry */
884 /* Since the cache is enabled according to the information we
885 * just loaded into the TLB, invalidate and enable the caches here.
886 * We should probably check/set other modes....later.
889 mtspr SPRN_IC_CST, r8
890 mtspr SPRN_DC_CST, r8
892 mtspr SPRN_IC_CST, r8
893 #ifdef CONFIG_8xx_COPYBACK
894 mtspr SPRN_DC_CST, r8
896 /* For a debug option, I left this here to easily enable
897 * the write through cache mode
900 mtspr SPRN_DC_CST, r8
902 mtspr SPRN_DC_CST, r8
904 /* Disable debug mode entry on breakpoints */
906 #ifdef CONFIG_PERF_EVENTS
907 rlwinm r8, r8, 0, ~0xc
909 rlwinm r8, r8, 0, ~0x8
916 * We put a few things here that have to be page-aligned.
917 * This stuff goes at the beginning of the data segment,
918 * which is page-aligned.
923 .globl empty_zero_page
927 EXPORT_SYMBOL(empty_zero_page)
929 .globl swapper_pg_dir
931 .space PGD_TABLE_SIZE
933 /* Room for two PTE table poiners, usually the kernel and current user
934 * pointer to their respective root page table (pgdir).
936 .globl abatron_pteptrs