1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
7 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
8 * Adapted for Power Macintosh by Paul Mackerras.
9 * Low-level exception handlers and MMU support
10 * rewritten by Paul Mackerras.
11 * Copyright (C) 1996 Paul Mackerras.
13 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
14 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
16 * This file contains the entry point for the 64-bit kernel along
17 * with some early initialization code common to all 64-bit powerpc
21 #include <linux/threads.h>
22 #include <linux/init.h>
26 #include <asm/ppc_asm.h>
27 #include <asm/head-64.h>
28 #include <asm/asm-offsets.h>
30 #include <asm/cputable.h>
31 #include <asm/setup.h>
32 #include <asm/hvcall.h>
33 #include <asm/thread_info.h>
34 #include <asm/firmware.h>
35 #include <asm/page_64.h>
36 #include <asm/irqflags.h>
37 #include <asm/kvm_book3s_asm.h>
38 #include <asm/ptrace.h>
39 #include <asm/hw_irq.h>
40 #include <asm/cputhreads.h>
41 #include <asm/ppc-opcode.h>
42 #include <asm/export.h>
43 #include <asm/feature-fixups.h>
44 #ifdef CONFIG_PPC_BOOK3S
45 #include <asm/exception-64s.h>
47 #include <asm/exception-64e.h>
50 /* The physical memory is laid out such that the secondary processor
51 * spin code sits at 0x0000...0x00ff. On server, the vectors follow
52 * using the layout described in exceptions-64s.S
56 * Entering into this code we make the following assumptions:
58 * For pSeries or server processors:
59 * 1. The MMU is off & open firmware is running in real mode.
60 * 2. The primary CPU enters at __start.
61 * 3. If the RTAS supports "query-cpu-stopped-state", then secondary
62 * CPUs will enter as directed by "start-cpu" RTAS call, which is
63 * generic_secondary_smp_init, with PIR in r3.
64 * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as
65 * directed by the "start-cpu" RTS call, with PIR in r3.
66 * -or- For OPAL entry:
67 * 1. The MMU is off, processor in HV mode.
68 * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base
69 * in r8, and entry in r9 for debugging purposes.
70 * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which
71 * is at generic_secondary_smp_init, with PIR in r3.
73 * For Book3E processors:
74 * 1. The MMU is on running in AS0 in a state defined in ePAPR
75 * 2. The kernel is entered at __start
78 OPEN_FIXED_SECTION(first_256B, 0x0, 0x100)
79 USE_FIXED_SECTION(first_256B)
81 * Offsets are relative from the start of fixed section, and
82 * first_256B starts at 0. Offsets are a bit easier to use here
83 * than the fixed section entry macros.
87 /* NOP this out unconditionally */
90 b __start_initialization_multiplatform
93 /* Catch branch to 0 in real mode */
96 /* Secondary processors spin on this value until it becomes non-zero.
97 * When non-zero, it contains the real address of the function the cpu
101 .globl __secondary_hold_spinloop
102 __secondary_hold_spinloop:
105 /* Secondary processors write this value with their cpu # */
106 /* after they enter the spin loop immediately below. */
107 .globl __secondary_hold_acknowledge
108 __secondary_hold_acknowledge:
111 #ifdef CONFIG_RELOCATABLE
112 /* This flag is set to 1 by a loader if the kernel should run
113 * at the loaded address instead of the linked address. This
114 * is used by kexec-tools to keep the kdump kernel in the
115 * crash_kernel region. The loader is responsible for
116 * observing the alignment requirement.
119 #ifdef CONFIG_RELOCATABLE_TEST
120 #define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */
122 #define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */
125 /* Do not move this variable as kexec-tools knows about it. */
129 DEFINE_FIXED_SYMBOL(__run_at_load, first_256B)
130 .long RUN_AT_LOAD_DEFAULT
135 * The following code is used to hold secondary processors
136 * in a spin loop after they have entered the kernel, but
137 * before the bulk of the kernel has been relocated. This code
138 * is relocated to physical address 0x60 before prom_init is run.
139 * All of it must fit below the first exception vector at 0x100.
140 * Use .globl here not _GLOBAL because we want __secondary_hold
141 * to be the actual text address, not a descriptor.
143 .globl __secondary_hold
146 #ifndef CONFIG_PPC_BOOK3E_64
149 mtmsrd r24 /* RI on */
151 /* Grab our physical cpu number */
153 /* stash r4 for book3e */
156 /* Tell the master cpu we're here */
157 /* Relocation is off & we are located at an address less */
158 /* than 0x100, so only need to grab low order offset. */
159 std r24,(ABS_ADDR(__secondary_hold_acknowledge, first_256B))(0)
163 #ifdef CONFIG_PPC_BOOK3E_64
166 /* All secondary cpus wait here until told to start. */
167 100: ld r12,(ABS_ADDR(__secondary_hold_spinloop, first_256B))(r26)
171 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
172 #ifdef CONFIG_PPC_BOOK3E_64
178 * it may be the case that other platforms have r4 right to
179 * begin with, this gives us some safety in case it is not
181 #ifdef CONFIG_PPC_BOOK3E_64
186 /* Make sure that patched code is visible */
191 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
193 CLOSE_FIXED_SECTION(first_256B)
196 * On server, we include the exception vectors code here as it
197 * relies on absolute addressing which is only possible within
198 * this compilation unit
200 #ifdef CONFIG_PPC_BOOK3S
201 #include "exceptions-64s.S"
203 OPEN_TEXT_SECTION(0x100)
208 #include "interrupt_64.S"
210 #ifdef CONFIG_PPC_BOOK3E_64
212 * The booting_thread_hwid holds the thread id we want to boot in cpu
213 * hotplug case. It is set by cpu hotplug code, and is invalid by default.
214 * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID]
217 .globl booting_thread_hwid
219 .long INVALID_THREAD_HWID
222 * start a thread in the same core
224 * r3 = the thread physical id
225 * r4 = the entry point where thread starts
227 _GLOBAL(book3e_start_thread)
228 LOAD_REG_IMMEDIATE(r5, MSR_KERNEL)
233 /* If the thread id is invalid, just exit. */
251 * stop a thread in the same core
253 * r3 = the thread physical id
255 _GLOBAL(book3e_stop_thread)
260 /* If the thread id is invalid, just exit. */
269 _GLOBAL(fsl_secondary_thread_init)
272 /* Enable branch prediction */
274 ori r3,r3,BUCSR_INIT@l
279 * Fix PIR to match the linear numbering in the device tree.
281 * On e6500, the reset value of PIR uses the low three bits for
282 * the thread within a core, and the upper bits for the core
283 * number. There are two threads per core, so shift everything
284 * but the low bit right by two bits so that the cpu numbering is
287 * If the old value of BUCSR is non-zero, this thread has run
288 * before. Thus, we assume we are coming from kexec or a similar
289 * scenario, and PIR is already set to the correct value. This
290 * is a bit of a hack, but there are limited opportunities for
291 * getting information into the thread and the alternatives
292 * seemed like they'd be overkill. We can't tell just by looking
293 * at the old PIR value which state it's in, since the same value
294 * could be valid for one thread out of reset and for a different
301 rlwimi r3, r3, 30, 2, 30
306 /* turn on 64-bit mode */
309 /* get a valid TOC pointer, wherever we're mapped at */
313 /* Book3E initialization */
315 bl book3e_secondary_thread_init
316 b generic_secondary_common_init
318 #endif /* CONFIG_PPC_BOOK3E_64 */
321 * On pSeries and most other platforms, secondary processors spin
322 * in the following code.
323 * At entry, r3 = this processor's number (physical cpu id)
325 * On Book3E, r4 = 1 to indicate that the initial TLB entry for
326 * this core already exists (setup via some other mechanism such
327 * as SCOM before entry).
329 _GLOBAL(generic_secondary_smp_init)
334 /* turn on 64-bit mode */
337 /* get a valid TOC pointer, wherever we're mapped at */
341 #ifdef CONFIG_PPC_BOOK3E_64
342 /* Book3E initialization */
345 bl book3e_secondary_core_init
348 * After common core init has finished, check if the current thread is the
349 * one we wanted to boot. If not, start the specified thread and stop the
352 LOAD_REG_ADDR(r4, booting_thread_hwid)
354 li r5, INVALID_THREAD_HWID
359 * The value of booting_thread_hwid has been stored in r3,
360 * so make it invalid.
365 * Get the current thread id and check if it is the one we wanted.
366 * If not, start the one specified in booting_thread_hwid and stop
367 * the current thread.
373 /* start the specified thread */
374 LOAD_REG_ADDR(r5, fsl_secondary_thread_init)
376 bl book3e_start_thread
378 /* stop the current thread */
380 bl book3e_stop_thread
386 generic_secondary_common_init:
387 /* Set up a paca value for this processor. Since we have the
388 * physical cpu id in r24, we need to search the pacas to find
389 * which logical id maps to our physical one.
392 b kexec_wait /* wait for next kernel if !SMP */
394 LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */
395 ld r8,0(r8) /* Get base vaddr of array */
396 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */
397 lwz r7,0(r7) /* also the max paca allocated */
398 li r5,0 /* logical cpu id */
400 sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */
401 ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */
402 lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
403 cmpw r6,r24 /* Compare to our id */
406 cmpw r5,r7 /* Check if more pacas exist */
409 mr r3,r24 /* not found, copy phys to r3 */
410 b kexec_wait /* next kernel might do better */
413 #ifdef CONFIG_PPC_BOOK3E_64
414 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
415 mtspr SPRN_SPRG_TLB_EXFRAME,r12
418 /* From now on, r24 is expected to be logical cpuid */
421 /* Create a temp kernel stack for use before relocation is on. */
422 ld r1,PACAEMERGSP(r13)
423 subi r1,r1,STACK_FRAME_OVERHEAD
425 /* See if we need to call a cpu state restore handler */
426 LOAD_REG_ADDR(r23, cur_cpu_spec)
428 ld r12,CPU_SPEC_RESTORE(r23)
431 #ifdef CONFIG_PPC64_ELF_ABI_V1
437 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
445 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
448 beq 4b /* Loop until told to go */
450 sync /* order paca.run and cur_cpu_spec */
451 isync /* In case code patching happened */
458 * Assumes we're mapped EA == RA if the MMU is on.
460 #ifdef CONFIG_PPC_BOOK3S
463 andi. r0,r3,MSR_IR|MSR_DR
471 b . /* prevent speculative execution */
476 * Here is our main kernel entry point. We support currently 2 kind of entries
477 * depending on the value of r5.
479 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
482 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
483 * DT block, r4 is a physical pointer to the kernel itself
486 __start_initialization_multiplatform:
487 /* Make sure we are running in 64 bits mode */
490 /* Zero r13 (paca) so early program check / mce don't use it */
493 /* Get TOC pointer (current runtime address) */
496 /* find out where we are now */
498 0: mflr r26 /* r26 = runtime addr here */
499 addis r26,r26,(_stext - 0b)@ha
500 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
503 * Are we booted from a PROM Of-type client-interface ?
507 b __boot_from_prom /* yes -> prom */
509 /* Save parameters */
512 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
513 /* Save OPAL entry */
518 #ifdef CONFIG_PPC_BOOK3E_64
519 bl start_initialization_book3e
522 /* Setup some critical 970 SPRs before switching MMU off */
525 cmpwi r0,0x39 /* 970 */
527 cmpwi r0,0x3c /* 970FX */
529 cmpwi r0,0x44 /* 970MP */
531 cmpwi r0,0x45 /* 970GX */
533 1: bl __cpu_preinit_ppc970
536 /* Switch off MMU if not already off */
539 #endif /* CONFIG_PPC_BOOK3E_64 */
543 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
544 /* Save parameters */
552 * Align the stack to 16-byte boundary
553 * Depending on the size and layout of the ELF sections in the initial
554 * boot binary, the stack pointer may be unaligned on PowerMac
558 #ifdef CONFIG_RELOCATABLE
559 /* Relocate code for where we are now */
564 /* Restore parameters */
571 /* Do all of the interaction with OF client interface */
574 #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
576 /* We never return. We also hit that trap if trying to boot
577 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
582 #ifdef CONFIG_RELOCATABLE
583 /* process relocations for the final address of the kernel */
584 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
586 #if defined(CONFIG_PPC_BOOK3E_64)
587 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
589 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
590 #if defined(CONFIG_PPC_BOOK3E_64)
593 cmplwi cr0,r7,1 /* flagged to stay where we are ? */
598 #if defined(CONFIG_PPC_BOOK3E_64)
599 /* IVPR needs to be set after relocation. */
605 * We need to run with _stext at physical address PHYSICAL_START.
606 * This will leave some code in the first 256B of
607 * real memory, which are reserved for software use.
609 * Note: This process overwrites the OF exception vectors.
611 li r3,0 /* target addr */
612 #ifdef CONFIG_PPC_BOOK3E_64
613 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */
615 mr. r4,r26 /* In some cases the loader may */
616 #if defined(CONFIG_PPC_BOOK3E_64)
619 beq 9f /* have already put us at zero */
620 li r6,0x100 /* Start offset, the first 0x100 */
621 /* bytes were copied earlier. */
623 #ifdef CONFIG_RELOCATABLE
625 * Check if the kernel has to be running as relocatable kernel based on the
626 * variable __run_at_load, if it is set the kernel is treated as relocatable
627 * kernel, otherwise it will be moved to PHYSICAL_START
629 #if defined(CONFIG_PPC_BOOK3E_64)
630 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
632 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
636 #ifdef CONFIG_PPC_BOOK3E_64
637 LOAD_REG_ADDR(r5, __end_interrupts)
638 LOAD_REG_ADDR(r11, _stext)
641 /* just copy interrupts */
642 LOAD_REG_IMMEDIATE_SYM(r5, r11, FIXED_SYMBOL_ABS_ADDR(__end_interrupts))
647 /* # bytes of memory to copy */
648 lis r5,(ABS_ADDR(copy_to_here, text))@ha
649 addi r5,r5,(ABS_ADDR(copy_to_here, text))@l
651 bl copy_and_flush /* copy the first n bytes */
652 /* this includes the code being */
654 /* Jump to the copy of this code that we just made */
655 addis r8,r3,(ABS_ADDR(4f, text))@ha
656 addi r12,r8,(ABS_ADDR(4f, text))@l
661 p_end: .8byte _end - copy_to_here
665 * Now copy the rest of the kernel up to _end, add
666 * _end - copy_to_here to the copy limit and run again.
668 addis r8,r26,(ABS_ADDR(p_end, text))@ha
669 ld r8,(ABS_ADDR(p_end, text))@l(r8)
671 5: bl copy_and_flush /* copy the rest */
673 9: b start_here_multiplatform
676 * Copy routine used to copy the kernel to start at physical address 0
677 * and flush and invalidate the caches as needed.
678 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
679 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
681 * Note: this routine *only* clobbers r0, r6 and lr
683 _GLOBAL(copy_and_flush)
686 4: li r0,8 /* Use the smallest common */
687 /* denominator cache line */
688 /* size. This results in */
689 /* extra cache line flushes */
690 /* but operation is correct. */
691 /* Can't get cache line size */
692 /* from NACA as it is being */
695 mtctr r0 /* put # words/line in ctr */
696 3: addi r6,r6,8 /* copy a cache line */
700 dcbst r6,r3 /* write it to memory */
702 icbi r6,r3 /* flush the icache line */
711 _ASM_NOKPROBE_SYMBOL(copy_and_flush); /* Called in real mode */
717 #ifdef CONFIG_PPC_PMAC
719 * On PowerMac, secondary processors starts from the reset vector, which
720 * is temporarily turned into a call to one of the functions below.
725 .globl __secondary_start_pmac_0
726 __secondary_start_pmac_0:
727 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
737 _GLOBAL(pmac_secondary_start)
738 /* turn on 64-bit mode */
743 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
750 /* get TOC pointer (real address) */
754 /* Copy some CPU settings from CPU 0 */
755 bl __restore_cpu_ppc970
757 /* pSeries do that early though I don't think we really need it */
760 mtmsrd r3 /* RI on */
762 /* Set up a paca value for this processor. */
763 LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */
764 ld r4,0(r4) /* Get base vaddr of paca_ptrs array */
765 sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */
766 ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */
767 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/
769 /* Mark interrupts soft and hard disabled (they might be enabled
770 * in the PACA when doing hotplug)
773 stb r0,PACAIRQSOFTMASK(r13)
774 li r0,PACA_IRQ_HARD_DIS
775 stb r0,PACAIRQHAPPENED(r13)
777 /* Create a temp kernel stack for use before relocation is on. */
778 ld r1,PACAEMERGSP(r13)
779 subi r1,r1,STACK_FRAME_OVERHEAD
783 #endif /* CONFIG_PPC_PMAC */
786 * This function is called after the master CPU has released the
787 * secondary processors. The execution environment is relocation off.
788 * The paca for this processor has the following fields initialized at
790 * 1. Processor number
791 * 2. Segment table pointer (virtual address)
792 * On entry the following are set:
793 * r1 = stack pointer (real addr of temp stack)
794 * r24 = cpu# (in Linux terms)
795 * r13 = paca virtual address
796 * SPRG_PACA = paca virtual address
801 .globl __secondary_start
803 /* Set thread priority to MEDIUM */
807 * Do early setup for this CPU, in particular initialising the MMU so we
808 * can turn it on below. This is a call to C, which is OK, we're still
809 * running on the emergency stack.
811 bl early_setup_secondary
814 * The primary has initialized our kernel stack for us in the paca, grab
815 * it and put it in r1. We must *not* use it until we turn on the MMU
816 * below, because it may not be inside the RMO.
818 ld r1, PACAKSAVE(r13)
820 /* Clear backchain so we get nice backtraces */
824 /* Mark interrupts soft and hard disabled (they might be enabled
825 * in the PACA when doing hotplug)
828 stb r7,PACAIRQSOFTMASK(r13)
829 li r0,PACA_IRQ_HARD_DIS
830 stb r0,PACAIRQHAPPENED(r13)
832 /* enable MMU and jump to start_secondary */
833 LOAD_REG_ADDR(r3, start_secondary_prolog)
834 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
839 b . /* prevent speculative execution */
842 * Running with relocation on at this point. All we want to do is
843 * zero the stack back-chain pointer and get the TOC virtual address
844 * before going into C code.
846 start_secondary_prolog:
849 std r3,0(r1) /* Zero the stack frame pointer */
853 * Reset stack pointer and call start_secondary
854 * to continue with online operation when woken up
855 * from cede in cpu offline.
857 _GLOBAL(start_secondary_resume)
858 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
860 std r3,0(r1) /* Zero the stack frame pointer */
866 * This subroutine clobbers r11 and r12
869 mfmsr r11 /* grab the current MSR */
870 #ifdef CONFIG_PPC_BOOK3E_64
871 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
873 #else /* CONFIG_PPC_BOOK3E_64 */
874 LOAD_REG_IMMEDIATE(r12, MSR_64BIT)
882 * This puts the TOC pointer into r2, offset by 0x8000 (as expected
883 * by the toolchain). It computes the correct value for wherever we
884 * are running at the moment, using position-independent code.
886 * Note: The compiler constructs pointers using offsets from the
887 * TOC in -mcmodel=medium mode. After we relocate to 0 but before
888 * the MMU is on we need our TOC to be a virtual address otherwise
889 * these pointers will be real addresses which may get stored and
890 * accessed later with the MMU on. We use tovirt() at the call
891 * sites to handle this.
893 _GLOBAL(relative_toc)
897 ld r2,(p_toc - 0b)(r11)
903 p_toc: .8byte .TOC. - 0b
906 * This is where the main kernel code starts.
909 start_here_multiplatform:
914 /* Clear out the BSS. It may have been done in prom_init,
915 * already but that's irrelevant since prom_init will soon
916 * be detached from the kernel completely. Besides, we need
917 * to clear it now for kexec-style entry.
919 LOAD_REG_ADDR(r11,__bss_stop)
920 LOAD_REG_ADDR(r8,__bss_start)
921 sub r11,r11,r8 /* bss size */
922 addi r11,r11,7 /* round up to an even double word */
923 srdi. r11,r11,3 /* shift right by 3 */
927 mtctr r11 /* zero this many doublewords */
932 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
933 /* Setup OPAL entry */
934 LOAD_REG_ADDR(r11, opal)
939 #ifndef CONFIG_PPC_BOOK3E_64
942 mtmsrd r6 /* RI on */
945 #ifdef CONFIG_RELOCATABLE
946 /* Save the physical address we're running at in kernstart_addr */
947 LOAD_REG_ADDR(r4, kernstart_addr)
952 /* set up a stack pointer */
953 LOAD_REG_ADDR(r3,init_thread_union)
954 LOAD_REG_IMMEDIATE(r1,THREAD_SIZE)
957 stdu r0,-STACK_FRAME_OVERHEAD(r1)
960 * Do very early kernel initializations, including initial hash table
961 * and SLB setup before we turn on relocation.
967 /* Restore parameters passed from prom_init/kexec */
969 LOAD_REG_ADDR(r12, DOTSYM(early_setup))
971 bctrl /* also sets r13 and SPRG_PACA */
973 LOAD_REG_ADDR(r3, start_here_common)
978 b . /* prevent speculative execution */
980 /* This is where all platforms converge execution */
983 /* relocation is on at this point */
984 std r1,PACAKSAVE(r13)
986 /* Load the TOC (virtual address) */
989 /* Mark interrupts soft and hard disabled (they might be enabled
990 * in the PACA when doing hotplug)
993 stb r0,PACAIRQSOFTMASK(r13)
994 li r0,PACA_IRQ_HARD_DIS
995 stb r0,PACAIRQHAPPENED(r13)
997 /* Generic kernel entry */
1002 EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0