1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This file contains the 64-bit "server" PowerPC variant
4 * of the low level exception handling including exception
5 * vectors, exception return, part of the slb and stab
6 * handling and other fixed offset specific things.
8 * This file is meant to be #included from head_64.S due to
9 * position dependent assembly.
11 * Most of this originates from head_64.S and thus has the same
16 #include <asm/hw_irq.h>
17 #include <asm/exception-64s.h>
18 #include <asm/ptrace.h>
19 #include <asm/cpuidle.h>
20 #include <asm/head-64.h>
21 #include <asm/feature-fixups.h>
24 /* PACA save area offsets (exgen, exmc, etc) */
35 #if defined(CONFIG_RELOCATABLE)
38 .error "EX_SIZE is wrong"
42 .error "EX_SIZE is wrong"
47 * We're short on space and time in the exception prolog, so we can't
48 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label.
49 * Instead we get the base of the kernel from paca->kernelbase and or in the low
50 * part of label. This requires that the label be within 64KB of kernelbase, and
51 * that kernelbase be 64K aligned.
53 #define LOAD_HANDLER(reg, label) \
54 ld reg,PACAKBASE(r13); /* get high part of &label */ \
55 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label)
57 #define __LOAD_HANDLER(reg, label) \
58 ld reg,PACAKBASE(r13); \
59 ori reg,reg,(ABS_ADDR(label))@l
62 * Branches from unrelocated code (e.g., interrupts) to labels outside
63 * head-y require >64K offsets.
65 #define __LOAD_FAR_HANDLER(reg, label) \
66 ld reg,PACAKBASE(r13); \
67 ori reg,reg,(ABS_ADDR(label))@l; \
68 addis reg,reg,(ABS_ADDR(label))@h
70 /* Exception register prefixes */
74 #if defined(CONFIG_RELOCATABLE)
76 * If we support interrupts with relocation on AND we're a relocatable kernel,
77 * we need to use CTR to get to the 2nd level handler. So, save/restore it
80 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13)
81 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13)
82 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg
84 /* ...else CTR is unused and in register. */
85 #define SAVE_CTR(reg, area)
86 #define GET_CTR(reg, area) mfctr reg
87 #define RESTORE_CTR(reg, area)
91 * PPR save/restore macros used in exceptions-64s.S
92 * Used for P7 or later processors
94 #define SAVE_PPR(area, ra) \
95 BEGIN_FTR_SECTION_NESTED(940) \
96 ld ra,area+EX_PPR(r13); /* Read PPR from paca */ \
98 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940)
100 #define RESTORE_PPR_PACA(area, ra) \
101 BEGIN_FTR_SECTION_NESTED(941) \
102 ld ra,area+EX_PPR(r13); \
104 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941)
107 * Get an SPR into a register if the CPU has the given feature
109 #define OPT_GET_SPR(ra, spr, ftr) \
110 BEGIN_FTR_SECTION_NESTED(943) \
112 END_FTR_SECTION_NESTED(ftr,ftr,943)
115 * Set an SPR from a register if the CPU has the given feature
117 #define OPT_SET_SPR(ra, spr, ftr) \
118 BEGIN_FTR_SECTION_NESTED(943) \
120 END_FTR_SECTION_NESTED(ftr,ftr,943)
123 * Save a register to the PACA if the CPU has the given feature
125 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \
126 BEGIN_FTR_SECTION_NESTED(943) \
127 std ra,offset(r13); \
128 END_FTR_SECTION_NESTED(ftr,ftr,943)
130 .macro EXCEPTION_PROLOG_0 area
132 std r9,\area\()+EX_R9(r13) /* save r9 */
133 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR)
135 std r10,\area\()+EX_R10(r13) /* save r10 - r12 */
136 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
139 .macro EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, bitmask
140 OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR)
141 OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR)
143 SAVE_CTR(r10, \area\())
149 lbz r10,PACAIRQSOFTMASK(r13)
150 andi. r10,r10,\bitmask
151 /* Associate vector numbers with bits in paca->irq_happened */
152 .if \vec == 0x500 || \vec == 0xea0
154 .elseif \vec == 0x900
156 .elseif \vec == 0xa00 || \vec == 0xe80
157 li r10,PACA_IRQ_DBELL
158 .elseif \vec == 0xe60
160 .elseif \vec == 0xf00
163 .abort "Bad maskable vector"
167 bne masked_Hinterrupt
173 std r11,\area\()+EX_R11(r13)
174 std r12,\area\()+EX_R12(r13)
176 std r10,\area\()+EX_R13(r13)
179 .macro EXCEPTION_PROLOG_2_REAL label, hsrr, set_ri
180 ld r10,PACAKMSR(r13) /* get MSR value for kernel */
182 xori r10,r10,MSR_RI /* Clear MSR_RI */
185 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
186 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
189 mfspr r11,SPRN_SRR0 /* save SRR0 */
190 mfspr r12,SPRN_SRR1 /* and SRR1 */
193 LOAD_HANDLER(r10, \label\())
201 b . /* prevent speculative execution */
204 .macro EXCEPTION_PROLOG_2_VIRT label, hsrr
205 #ifdef CONFIG_RELOCATABLE
207 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
209 mfspr r11,SPRN_SRR0 /* save SRR0 */
211 LOAD_HANDLER(r12, \label\())
214 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
216 mfspr r12,SPRN_SRR1 /* and HSRR1 */
219 mtmsrd r10,1 /* Set RI (EE=0) */
223 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
224 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
226 mfspr r11,SPRN_SRR0 /* save SRR0 */
227 mfspr r12,SPRN_SRR1 /* and SRR1 */
230 mtmsrd r10,1 /* Set RI (EE=0) */
236 * Branch to label using its 0xC000 address. This results in instruction
237 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned
238 * on using mtmsr rather than rfid.
240 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than
241 * load KBASE for a slight optimisation.
243 #define BRANCH_TO_C000(reg, label) \
244 __LOAD_HANDLER(reg, label); \
248 #ifdef CONFIG_RELOCATABLE
249 #define BRANCH_LINK_TO_FAR(label) \
250 __LOAD_FAR_HANDLER(r12, label); \
255 #define BRANCH_LINK_TO_FAR(label) \
259 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
260 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
262 * If hv is possible, interrupts come into to the hv version
263 * of the kvmppc_interrupt code, which then jumps to the PR handler,
264 * kvmppc_interrupt_pr, if the guest is a PR guest.
266 #define kvmppc_interrupt kvmppc_interrupt_hv
268 #define kvmppc_interrupt kvmppc_interrupt_pr
271 .macro KVMTEST hsrr, n
272 lbz r10,HSTATE_IN_GUEST(r13)
281 .macro KVM_HANDLER area, hsrr, n, skip
283 cmpwi r10,KVM_GUEST_MODE_SKIP
286 BEGIN_FTR_SECTION_NESTED(947)
287 ld r10,\area+EX_CFAR(r13)
288 std r10,HSTATE_CFAR(r13)
289 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947)
292 BEGIN_FTR_SECTION_NESTED(948)
293 ld r10,\area+EX_PPR(r13)
294 std r10,HSTATE_PPR(r13)
295 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
296 ld r10,\area+EX_R10(r13)
297 std r12,HSTATE_SCRATCH0(r13)
299 /* HSRR variants have the 0x2 bit added to their trap number */
301 ori r12,r12,(\n + 0x2)
306 #ifdef CONFIG_RELOCATABLE
308 * KVM requires __LOAD_FAR_HANDLER beause kvmppc_interrupt lives
309 * outside the head section. CONFIG_RELOCATABLE KVM expects CTR
310 * to be saved in HSTATE_SCRATCH1.
313 std r9,HSTATE_SCRATCH1(r13)
314 __LOAD_FAR_HANDLER(r9, kvmppc_interrupt)
316 ld r9,\area+EX_R9(r13)
319 ld r9,\area+EX_R9(r13)
326 ld r9,\area+EX_R9(r13)
327 ld r10,\area+EX_R10(r13)
329 b kvmppc_skip_Hinterrupt
331 b kvmppc_skip_interrupt
337 .macro KVMTEST hsrr, n
339 .macro KVM_HANDLER area, hsrr, n, skip
343 #define EXCEPTION_PROLOG_COMMON_1() \
344 std r9,_CCR(r1); /* save CR in stackframe */ \
345 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
346 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
347 std r10,0(r1); /* make stack chain pointer */ \
348 std r0,GPR0(r1); /* save r0 in stackframe */ \
349 std r10,GPR1(r1); /* save r1 in stackframe */ \
351 /* Save original regs values from save area to stack frame. */
352 #define EXCEPTION_PROLOG_COMMON_2(area) \
353 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
354 ld r10,area+EX_R10(r13); \
357 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
358 ld r10,area+EX_R12(r13); \
359 ld r11,area+EX_R13(r13); \
363 BEGIN_FTR_SECTION_NESTED(66); \
364 ld r10,area+EX_CFAR(r13); \
365 std r10,ORIG_GPR3(r1); \
366 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
367 GET_CTR(r10, area); \
370 #define EXCEPTION_PROLOG_COMMON_3(trap) \
371 std r2,GPR2(r1); /* save r2 in stackframe */ \
372 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
373 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
374 mflr r9; /* Get LR, later save to stack */ \
375 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
377 lbz r10,PACAIRQSOFTMASK(r13); \
378 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
382 std r9,_TRAP(r1); /* set trap number */ \
384 ld r11,exception_marker@toc(r2); \
385 std r10,RESULT(r1); /* clear regs->result */ \
386 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
389 * On entry r13 points to the paca, r9-r13 are saved in the paca,
390 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
391 * SRR1, and relocation is on.
393 #define EXCEPTION_COMMON(area, trap) \
394 andi. r10,r12,MSR_PR; /* See if coming from user */ \
395 mr r10,r1; /* Save r1 */ \
396 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
398 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
399 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \
400 blt+ cr1,3f; /* abort if it is */ \
401 li r1,(trap); /* will be reloaded later */ \
402 sth r1,PACA_TRAP_SAVE(r13); \
403 std r3,area+EX_R3(r13); \
404 addi r3,r13,area; /* r3 -> where regs are saved*/ \
405 RESTORE_CTR(r1, area); \
407 3: EXCEPTION_PROLOG_COMMON_1(); \
408 kuap_save_amr_and_lock r9, r10, cr1, cr0; \
409 beq 4f; /* if from kernel mode */ \
410 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \
411 SAVE_PPR(area, r9); \
412 4: EXCEPTION_PROLOG_COMMON_2(area); \
413 EXCEPTION_PROLOG_COMMON_3(trap); \
418 * Exception where stack is already set in r1, r1 is saved in r10.
419 * PPR save and CPU accounting is not done (for some reason).
421 #define EXCEPTION_COMMON_STACK(area, trap) \
422 EXCEPTION_PROLOG_COMMON_1(); \
423 kuap_save_amr_and_lock r9, r10, cr1; \
424 EXCEPTION_PROLOG_COMMON_2(area); \
425 EXCEPTION_PROLOG_COMMON_3(trap)
428 #define RUNLATCH_ON \
430 ld r3, PACA_THREAD_INFO(r13); \
431 ld r4,TI_LOCAL_FLAGS(r3); \
432 andi. r0,r4,_TLF_RUNLATCH; \
433 beql ppc64_runlatch_on_trampoline; \
434 END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
437 * When the idle code in power4_idle puts the CPU into NAP mode,
438 * it has to do so in a loop, and relies on the external interrupt
439 * and decrementer interrupt entry code to get it out of the loop.
440 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
441 * to signal that it is in the loop and needs help to get out.
443 #ifdef CONFIG_PPC_970_NAP
446 ld r11, PACA_THREAD_INFO(r13); \
447 ld r9,TI_LOCAL_FLAGS(r11); \
448 andi. r10,r9,_TLF_NAPPING; \
449 bnel power4_fixup_nap; \
450 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
456 * Following are the BOOK3S exception handler helper macros.
457 * Handlers come in a number of types, and each type has a number of varieties.
459 * EXC_REAL_* - real, unrelocated exception vectors
460 * EXC_VIRT_* - virt (AIL), unrelocated exception vectors
461 * TRAMP_REAL_* - real, unrelocated helpers (virt can call these)
462 * TRAMP_VIRT_* - virt, unreloc helpers (in practice, real can use)
463 * TRAMP_KVM - KVM handlers that get put into real, unrelocated
464 * EXC_COMMON - virt, relocated common handlers
466 * The EXC handlers are given a name, and branch to name_common, or the
467 * appropriate KVM or masking function. Vector handler verieties are as
470 * EXC_{REAL|VIRT}_BEGIN/END - used to open-code the exception
472 * EXC_{REAL|VIRT} - standard exception
474 * EXC_{REAL|VIRT}_suffix
476 * - _MASKABLE - maskable exception
477 * - _OOL - out of line with trampoline to common handler
478 * - _HV - HV exception
480 * There can be combinations, e.g., EXC_VIRT_OOL_MASKABLE_HV
482 * The one unusual case is __EXC_REAL_OOL_HV_DIRECT, which is
483 * an OOL vector that branches to a specified handler rather than the usual
484 * trampoline that goes to common. It, and other underscore macros, should
487 * KVM handlers come in the following verieties:
493 * COMMON handlers come in the following verieties:
494 * EXC_COMMON_BEGIN/END - used to open-code the handler
498 * TRAMP_REAL and TRAMP_VIRT can be used with BEGIN/END. KVM
499 * and OOL handlers are implemented as types of TRAMP and TRAMP_VIRT handlers.
502 #define __EXC_REAL(name, start, size, area) \
503 EXC_REAL_BEGIN(name, start, size); \
504 SET_SCRATCH0(r13); /* save r13 */ \
505 EXCEPTION_PROLOG_0 area ; \
506 EXCEPTION_PROLOG_1 EXC_STD, area, 1, start, 0 ; \
507 EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \
508 EXC_REAL_END(name, start, size)
510 #define EXC_REAL(name, start, size) \
511 __EXC_REAL(name, start, size, PACA_EXGEN)
513 #define __EXC_VIRT(name, start, size, realvec, area) \
514 EXC_VIRT_BEGIN(name, start, size); \
515 SET_SCRATCH0(r13); /* save r13 */ \
516 EXCEPTION_PROLOG_0 area ; \
517 EXCEPTION_PROLOG_1 EXC_STD, area, 0, realvec, 0; \
518 EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \
519 EXC_VIRT_END(name, start, size)
521 #define EXC_VIRT(name, start, size, realvec) \
522 __EXC_VIRT(name, start, size, realvec, PACA_EXGEN)
524 #define EXC_REAL_MASKABLE(name, start, size, bitmask) \
525 EXC_REAL_BEGIN(name, start, size); \
526 SET_SCRATCH0(r13); /* save r13 */ \
527 EXCEPTION_PROLOG_0 PACA_EXGEN ; \
528 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, start, bitmask ; \
529 EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \
530 EXC_REAL_END(name, start, size)
532 #define EXC_VIRT_MASKABLE(name, start, size, realvec, bitmask) \
533 EXC_VIRT_BEGIN(name, start, size); \
534 SET_SCRATCH0(r13); /* save r13 */ \
535 EXCEPTION_PROLOG_0 PACA_EXGEN ; \
536 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, bitmask ; \
537 EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \
538 EXC_VIRT_END(name, start, size)
540 #define EXC_REAL_HV(name, start, size) \
541 EXC_REAL_BEGIN(name, start, size); \
542 SET_SCRATCH0(r13); /* save r13 */ \
543 EXCEPTION_PROLOG_0 PACA_EXGEN; \
544 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, start, 0 ; \
545 EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 ; \
546 EXC_REAL_END(name, start, size)
548 #define EXC_VIRT_HV(name, start, size, realvec) \
549 EXC_VIRT_BEGIN(name, start, size); \
550 SET_SCRATCH0(r13); /* save r13 */ \
551 EXCEPTION_PROLOG_0 PACA_EXGEN; \
552 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0 ; \
553 EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV ; \
554 EXC_VIRT_END(name, start, size)
556 #define __EXC_REAL_OOL(name, start, size) \
557 EXC_REAL_BEGIN(name, start, size); \
559 EXCEPTION_PROLOG_0 PACA_EXGEN ; \
560 b tramp_real_##name ; \
561 EXC_REAL_END(name, start, size)
563 #define __TRAMP_REAL_OOL(name, vec) \
564 TRAMP_REAL_BEGIN(tramp_real_##name); \
565 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, 0 ; \
566 EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1
568 #define EXC_REAL_OOL(name, start, size) \
569 __EXC_REAL_OOL(name, start, size); \
570 __TRAMP_REAL_OOL(name, start)
572 #define __EXC_REAL_OOL_MASKABLE(name, start, size) \
573 __EXC_REAL_OOL(name, start, size)
575 #define __TRAMP_REAL_OOL_MASKABLE(name, vec, bitmask) \
576 TRAMP_REAL_BEGIN(tramp_real_##name); \
577 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, bitmask ; \
578 EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1
580 #define EXC_REAL_OOL_MASKABLE(name, start, size, bitmask) \
581 __EXC_REAL_OOL_MASKABLE(name, start, size); \
582 __TRAMP_REAL_OOL_MASKABLE(name, start, bitmask)
584 #define __EXC_REAL_OOL_HV_DIRECT(name, start, size, handler) \
585 EXC_REAL_BEGIN(name, start, size); \
587 EXCEPTION_PROLOG_0 PACA_EXGEN ; \
589 EXC_REAL_END(name, start, size)
591 #define __EXC_REAL_OOL_HV(name, start, size) \
592 __EXC_REAL_OOL(name, start, size)
594 #define __TRAMP_REAL_OOL_HV(name, vec) \
595 TRAMP_REAL_BEGIN(tramp_real_##name); \
596 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0 ; \
597 EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1
599 #define EXC_REAL_OOL_HV(name, start, size) \
600 __EXC_REAL_OOL_HV(name, start, size); \
601 __TRAMP_REAL_OOL_HV(name, start)
603 #define __EXC_REAL_OOL_MASKABLE_HV(name, start, size) \
604 __EXC_REAL_OOL(name, start, size)
606 #define __TRAMP_REAL_OOL_MASKABLE_HV(name, vec, bitmask) \
607 TRAMP_REAL_BEGIN(tramp_real_##name); \
608 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, bitmask ; \
609 EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1
611 #define EXC_REAL_OOL_MASKABLE_HV(name, start, size, bitmask) \
612 __EXC_REAL_OOL_MASKABLE_HV(name, start, size); \
613 __TRAMP_REAL_OOL_MASKABLE_HV(name, start, bitmask)
615 #define __EXC_VIRT_OOL(name, start, size) \
616 EXC_VIRT_BEGIN(name, start, size); \
618 EXCEPTION_PROLOG_0 PACA_EXGEN ; \
619 b tramp_virt_##name; \
620 EXC_VIRT_END(name, start, size)
622 #define __TRAMP_VIRT_OOL(name, realvec) \
623 TRAMP_VIRT_BEGIN(tramp_virt_##name); \
624 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, vec, 0 ; \
625 EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD
627 #define EXC_VIRT_OOL(name, start, size, realvec) \
628 __EXC_VIRT_OOL(name, start, size); \
629 __TRAMP_VIRT_OOL(name, realvec)
631 #define __EXC_VIRT_OOL_MASKABLE(name, start, size) \
632 __EXC_VIRT_OOL(name, start, size)
634 #define __TRAMP_VIRT_OOL_MASKABLE(name, realvec, bitmask) \
635 TRAMP_VIRT_BEGIN(tramp_virt_##name); \
636 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, bitmask ; \
637 EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1
639 #define EXC_VIRT_OOL_MASKABLE(name, start, size, realvec, bitmask) \
640 __EXC_VIRT_OOL_MASKABLE(name, start, size); \
641 __TRAMP_VIRT_OOL_MASKABLE(name, realvec, bitmask)
643 #define __EXC_VIRT_OOL_HV(name, start, size) \
644 __EXC_VIRT_OOL(name, start, size)
646 #define __TRAMP_VIRT_OOL_HV(name, realvec) \
647 TRAMP_VIRT_BEGIN(tramp_virt_##name); \
648 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0 ; \
649 EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV
651 #define EXC_VIRT_OOL_HV(name, start, size, realvec) \
652 __EXC_VIRT_OOL_HV(name, start, size); \
653 __TRAMP_VIRT_OOL_HV(name, realvec)
655 #define __EXC_VIRT_OOL_MASKABLE_HV(name, start, size) \
656 __EXC_VIRT_OOL(name, start, size)
658 #define __TRAMP_VIRT_OOL_MASKABLE_HV(name, realvec, bitmask) \
659 TRAMP_VIRT_BEGIN(tramp_virt_##name); \
660 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, bitmask ; \
661 EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV
663 #define EXC_VIRT_OOL_MASKABLE_HV(name, start, size, realvec, bitmask) \
664 __EXC_VIRT_OOL_MASKABLE_HV(name, start, size); \
665 __TRAMP_VIRT_OOL_MASKABLE_HV(name, realvec, bitmask)
667 #define TRAMP_KVM(area, n) \
668 TRAMP_KVM_BEGIN(do_kvm_##n); \
669 KVM_HANDLER area, EXC_STD, n, 0
671 #define TRAMP_KVM_SKIP(area, n) \
672 TRAMP_KVM_BEGIN(do_kvm_##n); \
673 KVM_HANDLER area, EXC_STD, n, 1
675 #define TRAMP_KVM_HV(area, n) \
676 TRAMP_KVM_BEGIN(do_kvm_H##n); \
677 KVM_HANDLER area, EXC_HV, n, 0
679 #define TRAMP_KVM_HV_SKIP(area, n) \
680 TRAMP_KVM_BEGIN(do_kvm_H##n); \
681 KVM_HANDLER area, EXC_HV, n, 1
683 #define EXC_COMMON(name, realvec, hdlr) \
684 EXC_COMMON_BEGIN(name); \
685 EXCEPTION_COMMON(PACA_EXGEN, realvec); \
687 RECONCILE_IRQ_STATE(r10, r11); \
688 addi r3,r1,STACK_FRAME_OVERHEAD; \
693 * Like EXC_COMMON, but for exceptions that can occur in the idle task and
694 * therefore need the special idle handling (finish nap and runlatch)
696 #define EXC_COMMON_ASYNC(name, realvec, hdlr) \
697 EXC_COMMON_BEGIN(name); \
698 EXCEPTION_COMMON(PACA_EXGEN, realvec); \
700 RECONCILE_IRQ_STATE(r10, r11); \
702 addi r3,r1,STACK_FRAME_OVERHEAD; \
704 b ret_from_except_lite
708 * There are a few constraints to be concerned with.
709 * - Real mode exceptions code/data must be located at their physical location.
710 * - Virtual mode exceptions must be mapped at their 0xc000... location.
711 * - Fixed location code must not call directly beyond the __end_interrupts
712 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
714 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
716 * - Conditional branch targets must be within +/-32K of caller.
718 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
719 * therefore don't have to run in physically located code or rfid to
720 * virtual mode kernel code. However on relocatable kernels they do have
721 * to branch to KERNELBASE offset because the rest of the kernel (outside
722 * the exception vectors) may be located elsewhere.
724 * Virtual exceptions correspond with physical, except their entry points
725 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
726 * offset applied. Virtual exceptions are enabled with the Alternate
727 * Interrupt Location (AIL) bit set in the LPCR. However this does not
728 * guarantee they will be delivered virtually. Some conditions (see the ISA)
729 * cause exceptions to be delivered in real mode.
731 * It's impossible to receive interrupts below 0x300 via AIL.
733 * KVM: None of the virtual exceptions are from the guest. Anything that
734 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
737 * We layout physical memory as follows:
738 * 0x0000 - 0x00ff : Secondary processor spin code
739 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
740 * 0x1900 - 0x3fff : Real mode trampolines
741 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
742 * 0x5900 - 0x6fff : Relon mode trampolines
743 * 0x7000 - 0x7fff : FWNMI data area
744 * 0x8000 - .... : Common interrupt handlers, remaining early
745 * setup code, rest of kernel.
747 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
748 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
751 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
752 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000)
753 OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900)
754 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
756 #ifdef CONFIG_PPC_POWERNV
757 .globl start_real_trampolines
758 .globl end_real_trampolines
759 .globl start_virt_trampolines
760 .globl end_virt_trampolines
763 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
765 * Data area reserved for FWNMI option.
766 * This address (0x7000) is fixed by the RPA.
767 * pseries and powernv need to keep the whole page from
768 * 0x7000 to 0x8000 free for use by the firmware
770 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
771 OPEN_TEXT_SECTION(0x8000)
773 OPEN_TEXT_SECTION(0x7000)
776 USE_FIXED_SECTION(real_vectors)
779 * This is the start of the interrupt handlers for pSeries
780 * This code runs with relocation off.
781 * Code from here to __end_interrupts gets copied down to real
782 * address 0x100 when we are running a relocatable kernel.
783 * Therefore any relative branches in this section must only
784 * branch to labels in this section.
786 .globl __start_interrupts
789 /* No virt vectors corresponding with 0x0..0x100 */
790 EXC_VIRT_NONE(0x4000, 0x100)
793 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
795 EXCEPTION_PROLOG_0 PACA_EXNMI
797 /* This is EXCEPTION_PROLOG_1 with the idle feature section added */
798 OPT_SAVE_REG_TO_PACA(PACA_EXNMI+EX_PPR, r9, CPU_FTR_HAS_PPR)
799 OPT_SAVE_REG_TO_PACA(PACA_EXNMI+EX_CFAR, r10, CPU_FTR_CFAR)
801 SAVE_CTR(r10, PACA_EXNMI)
804 #ifdef CONFIG_PPC_P7_NAP
806 * If running native on arch 2.06 or later, check if we are waking up
807 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1
808 * bits 46:47. A non-0 value indicates that we are coming from a power
809 * saving state. The idle wakeup handler initially runs in real mode,
810 * but we branch to the 0xc000... address so we can turn on relocation
815 rlwinm. r10,r10,47-31,30,31
819 bltlr cr1 /* no state loss, return to idle caller */
820 BRANCH_TO_C000(r10, system_reset_idle_common)
822 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
825 KVMTEST EXC_STD 0x100
826 std r11,PACA_EXNMI+EX_R11(r13)
827 std r12,PACA_EXNMI+EX_R12(r13)
829 std r10,PACA_EXNMI+EX_R13(r13)
831 EXCEPTION_PROLOG_2_REAL system_reset_common, EXC_STD, 0
833 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
834 * being used, so a nested NMI exception would corrupt it.
837 EXC_REAL_END(system_reset, 0x100, 0x100)
838 EXC_VIRT_NONE(0x4100, 0x100)
839 TRAMP_KVM(PACA_EXNMI, 0x100)
841 #ifdef CONFIG_PPC_P7_NAP
842 EXC_COMMON_BEGIN(system_reset_idle_common)
844 * This must be a direct branch (without linker branch stub) because
845 * we can not use TOC at this point as r2 may not be restored yet.
847 b idle_return_gpr_loss
850 EXC_COMMON_BEGIN(system_reset_common)
852 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
853 * to recover, but nested NMI will notice in_nmi and not recover
854 * because of the use of the NMI stack. in_nmi reentrancy is tested in
855 * system_reset_exception.
857 lhz r10,PACA_IN_NMI(r13)
859 sth r10,PACA_IN_NMI(r13)
864 ld r1,PACA_NMI_EMERG_SP(r13)
865 subi r1,r1,INT_FRAME_SIZE
866 EXCEPTION_COMMON_STACK(PACA_EXNMI, 0x100)
869 * Set IRQS_ALL_DISABLED unconditionally so arch_irqs_disabled does
870 * the right thing. We do not want to reconcile because that goes
871 * through irq tracing which we don't want in NMI.
873 * Save PACAIRQHAPPENED because some code will do a hard disable
874 * (e.g., xmon). So we want to restore this back to where it was
875 * when we return. DAR is unused in the stack, so save it there.
877 li r10,IRQS_ALL_DISABLED
878 stb r10,PACAIRQSOFTMASK(r13)
879 lbz r10,PACAIRQHAPPENED(r13)
882 addi r3,r1,STACK_FRAME_OVERHEAD
883 bl system_reset_exception
885 /* Clear MSR_RI before setting SRR0 and SRR1. */
890 * MSR_RI is clear, now we can decrement paca->in_nmi.
892 lhz r10,PACA_IN_NMI(r13)
894 sth r10,PACA_IN_NMI(r13)
897 * Restore soft mask settings.
900 stb r10,PACAIRQHAPPENED(r13)
902 stb r10,PACAIRQSOFTMASK(r13)
905 * Keep below code in synch with MACHINE_CHECK_HANDLER_WINDUP.
906 * Should share common bits...
909 /* Move original SRR0 and SRR1 into the respective regs */
927 /* restore original r1. */
929 RFI_TO_USER_OR_KERNEL
931 #ifdef CONFIG_PPC_PSERIES
933 * Vectors for the FWNMI option. Share common code.
935 TRAMP_REAL_BEGIN(system_reset_fwnmi)
936 SET_SCRATCH0(r13) /* save r13 */
937 /* See comment at system_reset exception, don't turn on RI */
938 EXCEPTION_PROLOG_0 PACA_EXNMI
939 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXNMI, 0, 0x100, 0
940 EXCEPTION_PROLOG_2_REAL system_reset_common, EXC_STD, 0
942 #endif /* CONFIG_PPC_PSERIES */
945 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
946 /* This is moved out of line as it can be patched by FW, but
947 * some code path might still want to branch into the original
950 SET_SCRATCH0(r13) /* save r13 */
951 EXCEPTION_PROLOG_0 PACA_EXMC
953 b machine_check_common_early
955 b machine_check_pSeries_0
956 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
957 EXC_REAL_END(machine_check, 0x200, 0x100)
958 EXC_VIRT_NONE(0x4200, 0x100)
959 TRAMP_REAL_BEGIN(machine_check_common_early)
960 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 0, 0x200, 0
965 * Original R9 to R13 is saved on PACA_EXMC
967 * Switch to mc_emergency stack and handle re-entrancy (we limit
968 * the nested MCE upto level 4 to avoid stack overflow).
969 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
971 * We use paca->in_mce to check whether this is the first entry or
972 * nested machine check. We increment paca->in_mce to track nested
975 * If this is the first entry then set stack pointer to
976 * paca->mc_emergency_sp, otherwise r1 is already pointing to
977 * stack frame on mc_emergency stack.
979 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
980 * checkstop if we get another machine check exception before we do
981 * rfid with MSR_ME=1.
983 * This interrupt can wake directly from idle. If that is the case,
984 * the machine check is handled then the idle wakeup code is called
987 mr r11,r1 /* Save r1 */
988 lhz r10,PACA_IN_MCE(r13)
989 cmpwi r10,0 /* Are we in nested machine check */
990 bne 0f /* Yes, we are. */
991 /* First machine check entry */
992 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
993 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
994 addi r10,r10,1 /* increment paca->in_mce */
995 sth r10,PACA_IN_MCE(r13)
996 /* Limit nested MCE to level 4 to avoid stack overflow */
997 cmpwi r10,MAX_MCE_DEPTH
998 bgt 2f /* Check if we hit limit of 4 */
999 std r11,GPR1(r1) /* Save r1 on the stack. */
1000 std r11,0(r1) /* make stack chain pointer */
1001 mfspr r11,SPRN_SRR0 /* Save SRR0 */
1003 mfspr r11,SPRN_SRR1 /* Save SRR1 */
1005 mfspr r11,SPRN_DAR /* Save DAR */
1007 mfspr r11,SPRN_DSISR /* Save DSISR */
1009 std r9,_CCR(r1) /* Save CR in stackframe */
1010 /* We don't touch AMR here, we never go to virtual mode */
1011 /* Save r9 through r13 from EXMC save area to stack frame. */
1012 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
1013 mfmsr r11 /* get MSR value */
1015 ori r11,r11,MSR_ME /* turn on ME bit */
1016 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1017 ori r11,r11,MSR_RI /* turn on RI bit */
1018 LOAD_HANDLER(r12, machine_check_handle_early)
1019 1: mtspr SPRN_SRR0,r12
1022 b . /* prevent speculative execution */
1024 /* Stack overflow. Stay on emergency stack and panic.
1025 * Keep the ME bit off while panic-ing, so that if we hit
1026 * another machine check we checkstop.
1028 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
1029 ld r11,PACAKMSR(r13)
1030 LOAD_HANDLER(r12, unrecover_mce)
1032 andc r11,r11,r10 /* Turn off MSR_ME */
1034 b . /* prevent speculative execution */
1036 TRAMP_REAL_BEGIN(machine_check_pSeries)
1037 .globl machine_check_fwnmi
1038 machine_check_fwnmi:
1039 SET_SCRATCH0(r13) /* save r13 */
1040 EXCEPTION_PROLOG_0 PACA_EXMC
1042 b machine_check_common_early
1043 END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
1044 machine_check_pSeries_0:
1045 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 0
1047 * MSR_RI is not enabled, because PACA_EXMC is being used, so a
1048 * nested machine check corrupts it. machine_check_common enables
1051 EXCEPTION_PROLOG_2_REAL machine_check_common, EXC_STD, 0
1053 TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
1055 EXC_COMMON_BEGIN(machine_check_common)
1057 * Machine check is different because we use a different
1058 * save area: PACA_EXMC instead of PACA_EXGEN.
1061 std r10,PACA_EXMC+EX_DAR(r13)
1062 mfspr r10,SPRN_DSISR
1063 stw r10,PACA_EXMC+EX_DSISR(r13)
1064 EXCEPTION_COMMON(PACA_EXMC, 0x200)
1066 RECONCILE_IRQ_STATE(r10, r11)
1067 ld r3,PACA_EXMC+EX_DAR(r13)
1068 lwz r4,PACA_EXMC+EX_DSISR(r13)
1069 /* Enable MSR_RI when finished with PACA_EXMC */
1075 addi r3,r1,STACK_FRAME_OVERHEAD
1076 bl machine_check_exception
1079 #define MACHINE_CHECK_HANDLER_WINDUP \
1080 /* Clear MSR_RI before setting SRR0 and SRR1. */\
1082 mtmsrd r9,1; /* Clear MSR_RI */ \
1083 /* Move original SRR0 and SRR1 into the respective regs */ \
1085 mtspr SPRN_SRR1,r9; \
1087 mtspr SPRN_SRR0,r9; \
1095 REST_8GPRS(2, r1); \
1099 /* Decrement paca->in_mce. */ \
1100 lhz r12,PACA_IN_MCE(r13); \
1102 sth r12,PACA_IN_MCE(r13); \
1104 REST_2GPRS(12, r1); \
1105 /* restore original r1. */ \
1108 #ifdef CONFIG_PPC_P7_NAP
1110 * This is an idle wakeup. Low level machine check has already been
1111 * done. Queue the event then call the idle code to do the wake up.
1113 EXC_COMMON_BEGIN(machine_check_idle_common)
1114 bl machine_check_queue_event
1117 * We have not used any non-volatile GPRs here, and as a rule
1118 * most exception code including machine check does not.
1119 * Therefore PACA_NAPSTATELOST does not need to be set. Idle
1120 * wakeup will restore volatile registers.
1122 * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
1124 * Then decrement MCE nesting after finishing with the stack.
1129 lhz r11,PACA_IN_MCE(r13)
1131 sth r11,PACA_IN_MCE(r13)
1134 rlwinm r10,r3,47-31,30,31
1136 bltlr cr1 /* no state loss, return to idle caller */
1137 b idle_return_gpr_loss
1140 * Handle machine check early in real mode. We come here with
1141 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
1143 EXC_COMMON_BEGIN(machine_check_handle_early)
1144 std r0,GPR0(r1) /* Save r0 */
1145 EXCEPTION_PROLOG_COMMON_3(0x200)
1147 addi r3,r1,STACK_FRAME_OVERHEAD
1148 bl machine_check_early
1149 std r3,RESULT(r1) /* Save result */
1153 END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
1155 #ifdef CONFIG_PPC_P7_NAP
1157 * Check if thread was in power saving mode. We come here when any
1158 * of the following is true:
1159 * a. thread wasn't in power saving mode
1160 * b. thread was in power saving mode with no state loss,
1161 * supervisor state loss or hypervisor state loss.
1163 * Go back to nap/sleep/winkle mode again if (b) is true.
1166 rlwinm. r11,r12,47-31,30,31
1167 bne machine_check_idle_common
1168 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
1172 * Check if we are coming from hypervisor userspace. If yes then we
1173 * continue in host kernel in V mode to deliver the MC event.
1175 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */
1177 4: andi. r11,r12,MSR_PR /* See if coming from user. */
1178 bne 9f /* continue in V mode if we are. */
1181 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1184 * We are coming from kernel context. Check if we are coming from
1185 * guest. if yes, then we can continue. We will fall through
1186 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
1188 lbz r11,HSTATE_IN_GUEST(r13)
1189 cmpwi r11,0 /* Check if coming from guest */
1190 bne 9f /* continue if we are. */
1191 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1194 * At this point we are not sure about what context we come from.
1195 * Queue up the MCE event and return from the interrupt.
1196 * But before that, check if this is an un-recoverable exception.
1197 * If yes, then stay on emergency stack and panic.
1199 andi. r11,r12,MSR_RI
1201 1: mfspr r11,SPRN_SRR0
1202 LOAD_HANDLER(r10,unrecover_mce)
1204 ld r10,PACAKMSR(r13)
1206 * We are going down. But there are chances that we might get hit by
1207 * another MCE during panic path and we may run into unstable state
1208 * with no way out. Hence, turn ME bit off while going down, so that
1209 * when another MCE is hit during panic path, system will checkstop
1210 * and hypervisor will get restarted cleanly by SP.
1213 andc r10,r10,r3 /* Turn off MSR_ME */
1219 * Check if we have successfully handled/recovered from error, if not
1220 * then stay on emergency stack and panic.
1222 ld r3,RESULT(r1) /* Load result */
1223 cmpdi r3,0 /* see if we handled MCE successfully */
1225 beq 1b /* if !handled then panic */
1228 * Return from MC interrupt.
1229 * Queue up the MCE event so that we can log it later, while
1230 * returning from kernel or opal call.
1232 bl machine_check_queue_event
1233 MACHINE_CHECK_HANDLER_WINDUP
1234 RFI_TO_USER_OR_KERNEL
1237 * pSeries: Return from MC interrupt. Before that stay on emergency
1238 * stack and call machine_check_exception to log the MCE event.
1240 LOAD_HANDLER(r10,mce_return)
1242 ld r10,PACAKMSR(r13)
1246 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1248 /* Deliver the machine check to host kernel in V mode. */
1249 MACHINE_CHECK_HANDLER_WINDUP
1250 SET_SCRATCH0(r13) /* save r13 */
1251 EXCEPTION_PROLOG_0 PACA_EXMC
1252 b machine_check_pSeries_0
1254 EXC_COMMON_BEGIN(unrecover_mce)
1255 /* Invoke machine_check_exception to print MCE event and panic. */
1256 addi r3,r1,STACK_FRAME_OVERHEAD
1257 bl machine_check_exception
1259 * We will not reach here. Even if we did, there is no way out. Call
1260 * unrecoverable_exception and die.
1262 1: addi r3,r1,STACK_FRAME_OVERHEAD
1263 bl unrecoverable_exception
1266 EXC_COMMON_BEGIN(mce_return)
1267 /* Invoke machine_check_exception to print MCE event and return. */
1268 addi r3,r1,STACK_FRAME_OVERHEAD
1269 bl machine_check_exception
1270 MACHINE_CHECK_HANDLER_WINDUP
1274 EXC_REAL_BEGIN(data_access, 0x300, 0x80)
1275 SET_SCRATCH0(r13) /* save r13 */
1276 EXCEPTION_PROLOG_0 PACA_EXGEN
1277 b tramp_real_data_access
1278 EXC_REAL_END(data_access, 0x300, 0x80)
1280 TRAMP_REAL_BEGIN(tramp_real_data_access)
1281 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x300, 0
1283 * DAR/DSISR must be read before setting MSR[RI], because
1284 * a d-side MCE will clobber those registers so is not
1285 * recoverable if they are live.
1288 mfspr r11,SPRN_DSISR
1289 std r10,PACA_EXGEN+EX_DAR(r13)
1290 stw r11,PACA_EXGEN+EX_DSISR(r13)
1291 EXCEPTION_PROLOG_2_REAL data_access_common, EXC_STD, 1
1293 EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
1294 SET_SCRATCH0(r13) /* save r13 */
1295 EXCEPTION_PROLOG_0 PACA_EXGEN
1296 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300, 0
1298 mfspr r11,SPRN_DSISR
1299 std r10,PACA_EXGEN+EX_DAR(r13)
1300 stw r11,PACA_EXGEN+EX_DSISR(r13)
1301 EXCEPTION_PROLOG_2_VIRT data_access_common, EXC_STD
1302 EXC_VIRT_END(data_access, 0x4300, 0x80)
1304 TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
1306 EXC_COMMON_BEGIN(data_access_common)
1308 * Here r13 points to the paca, r9 contains the saved CR,
1309 * SRR0 and SRR1 are saved in r11 and r12,
1310 * r9 - r13 are saved in paca->exgen.
1311 * EX_DAR and EX_DSISR have saved DAR/DSISR
1313 EXCEPTION_COMMON(PACA_EXGEN, 0x300)
1314 RECONCILE_IRQ_STATE(r10, r11)
1316 ld r3,PACA_EXGEN+EX_DAR(r13)
1317 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1321 BEGIN_MMU_FTR_SECTION
1322 b do_hash_page /* Try to handle as hpte fault */
1323 MMU_FTR_SECTION_ELSE
1325 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1328 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
1329 SET_SCRATCH0(r13) /* save r13 */
1330 EXCEPTION_PROLOG_0 PACA_EXSLB
1331 b tramp_real_data_access_slb
1332 EXC_REAL_END(data_access_slb, 0x380, 0x80)
1334 TRAMP_REAL_BEGIN(tramp_real_data_access_slb)
1335 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 1, 0x380, 0
1337 std r10,PACA_EXSLB+EX_DAR(r13)
1338 EXCEPTION_PROLOG_2_REAL data_access_slb_common, EXC_STD, 1
1340 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
1341 SET_SCRATCH0(r13) /* save r13 */
1342 EXCEPTION_PROLOG_0 PACA_EXSLB
1343 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380, 0
1345 std r10,PACA_EXSLB+EX_DAR(r13)
1346 EXCEPTION_PROLOG_2_VIRT data_access_slb_common, EXC_STD
1347 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
1349 TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
1351 EXC_COMMON_BEGIN(data_access_slb_common)
1352 EXCEPTION_COMMON(PACA_EXSLB, 0x380)
1353 ld r4,PACA_EXSLB+EX_DAR(r13)
1355 addi r3,r1,STACK_FRAME_OVERHEAD
1356 BEGIN_MMU_FTR_SECTION
1357 /* HPT case, do SLB fault */
1361 b fast_exception_return
1363 MMU_FTR_SECTION_ELSE
1364 /* Radix case, access is outside page table range */
1366 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1369 RECONCILE_IRQ_STATE(r10, r11)
1372 addi r3,r1,STACK_FRAME_OVERHEAD
1377 EXC_REAL(instruction_access, 0x400, 0x80)
1378 EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400)
1379 TRAMP_KVM(PACA_EXGEN, 0x400)
1381 EXC_COMMON_BEGIN(instruction_access_common)
1382 EXCEPTION_COMMON(PACA_EXGEN, 0x400)
1383 RECONCILE_IRQ_STATE(r10, r11)
1386 andis. r4,r12,DSISR_SRR1_MATCH_64S@h
1390 BEGIN_MMU_FTR_SECTION
1391 b do_hash_page /* Try to handle as hpte fault */
1392 MMU_FTR_SECTION_ELSE
1394 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1397 __EXC_REAL(instruction_access_slb, 0x480, 0x80, PACA_EXSLB)
1398 __EXC_VIRT(instruction_access_slb, 0x4480, 0x80, 0x480, PACA_EXSLB)
1399 TRAMP_KVM(PACA_EXSLB, 0x480)
1401 EXC_COMMON_BEGIN(instruction_access_slb_common)
1402 EXCEPTION_COMMON(PACA_EXSLB, 0x480)
1404 addi r3,r1,STACK_FRAME_OVERHEAD
1405 BEGIN_MMU_FTR_SECTION
1406 /* HPT case, do SLB fault */
1410 b fast_exception_return
1412 MMU_FTR_SECTION_ELSE
1413 /* Radix case, access is outside page table range */
1415 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1418 RECONCILE_IRQ_STATE(r10, r11)
1421 addi r3,r1,STACK_FRAME_OVERHEAD
1426 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
1427 SET_SCRATCH0(r13) /* save r13 */
1428 EXCEPTION_PROLOG_0 PACA_EXGEN
1430 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, IRQS_DISABLED
1431 EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_HV, 1
1433 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, IRQS_DISABLED
1434 EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_STD, 1
1435 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
1436 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
1438 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
1439 SET_SCRATCH0(r13) /* save r13 */
1440 EXCEPTION_PROLOG_0 PACA_EXGEN
1442 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, IRQS_DISABLED
1443 EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_HV
1445 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, IRQS_DISABLED
1446 EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_STD
1447 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1448 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
1450 TRAMP_KVM(PACA_EXGEN, 0x500)
1451 TRAMP_KVM_HV(PACA_EXGEN, 0x500)
1452 EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
1455 EXC_REAL_BEGIN(alignment, 0x600, 0x100)
1456 SET_SCRATCH0(r13) /* save r13 */
1457 EXCEPTION_PROLOG_0 PACA_EXGEN
1458 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600, 0
1460 mfspr r11,SPRN_DSISR
1461 std r10,PACA_EXGEN+EX_DAR(r13)
1462 stw r11,PACA_EXGEN+EX_DSISR(r13)
1463 EXCEPTION_PROLOG_2_REAL alignment_common, EXC_STD, 1
1464 EXC_REAL_END(alignment, 0x600, 0x100)
1466 EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
1467 SET_SCRATCH0(r13) /* save r13 */
1468 EXCEPTION_PROLOG_0 PACA_EXGEN
1469 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600, 0
1471 mfspr r11,SPRN_DSISR
1472 std r10,PACA_EXGEN+EX_DAR(r13)
1473 stw r11,PACA_EXGEN+EX_DSISR(r13)
1474 EXCEPTION_PROLOG_2_VIRT alignment_common, EXC_STD
1475 EXC_VIRT_END(alignment, 0x4600, 0x100)
1477 TRAMP_KVM(PACA_EXGEN, 0x600)
1478 EXC_COMMON_BEGIN(alignment_common)
1479 EXCEPTION_COMMON(PACA_EXGEN, 0x600)
1480 ld r3,PACA_EXGEN+EX_DAR(r13)
1481 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1485 RECONCILE_IRQ_STATE(r10, r11)
1486 addi r3,r1,STACK_FRAME_OVERHEAD
1487 bl alignment_exception
1491 EXC_REAL(program_check, 0x700, 0x100)
1492 EXC_VIRT(program_check, 0x4700, 0x100, 0x700)
1493 TRAMP_KVM(PACA_EXGEN, 0x700)
1494 EXC_COMMON_BEGIN(program_check_common)
1496 * It's possible to receive a TM Bad Thing type program check with
1497 * userspace register values (in particular r1), but with SRR1 reporting
1498 * that we came from the kernel. Normally that would confuse the bad
1499 * stack logic, and we would report a bad kernel stack pointer. Instead
1500 * we switch to the emergency stack if we're taking a TM Bad Thing from
1503 li r10,MSR_PR /* Build a mask of MSR_PR .. */
1504 oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */
1505 and r10,r10,r12 /* Mask SRR1 with that. */
1506 srdi r10,r10,8 /* Shift it so we can compare */
1507 cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */
1508 bne 1f /* If != go to normal path. */
1510 /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */
1511 andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */
1512 /* 3 in EXCEPTION_PROLOG_COMMON */
1513 mr r10,r1 /* Save r1 */
1514 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
1515 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1516 b 3f /* Jump into the macro !! */
1517 1: EXCEPTION_COMMON(PACA_EXGEN, 0x700)
1519 RECONCILE_IRQ_STATE(r10, r11)
1520 addi r3,r1,STACK_FRAME_OVERHEAD
1521 bl program_check_exception
1525 EXC_REAL(fp_unavailable, 0x800, 0x100)
1526 EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800)
1527 TRAMP_KVM(PACA_EXGEN, 0x800)
1528 EXC_COMMON_BEGIN(fp_unavailable_common)
1529 EXCEPTION_COMMON(PACA_EXGEN, 0x800)
1530 bne 1f /* if from user, just load it up */
1532 RECONCILE_IRQ_STATE(r10, r11)
1533 addi r3,r1,STACK_FRAME_OVERHEAD
1534 bl kernel_fp_unavailable_exception
1537 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1539 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1540 * transaction), go do TM stuff
1542 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1544 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1547 b fast_exception_return
1548 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1549 2: /* User process was in a transaction */
1551 RECONCILE_IRQ_STATE(r10, r11)
1552 addi r3,r1,STACK_FRAME_OVERHEAD
1553 bl fp_unavailable_tm
1558 EXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80, IRQS_DISABLED)
1559 EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900, IRQS_DISABLED)
1560 TRAMP_KVM(PACA_EXGEN, 0x900)
1561 EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
1564 EXC_REAL_HV(hdecrementer, 0x980, 0x80)
1565 EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980)
1566 TRAMP_KVM_HV(PACA_EXGEN, 0x980)
1567 EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
1570 EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100, IRQS_DISABLED)
1571 EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00, IRQS_DISABLED)
1572 TRAMP_KVM(PACA_EXGEN, 0xa00)
1573 #ifdef CONFIG_PPC_DOORBELL
1574 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
1576 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
1580 EXC_REAL(trap_0b, 0xb00, 0x100)
1581 EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00)
1582 TRAMP_KVM(PACA_EXGEN, 0xb00)
1583 EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
1586 * system call / hypercall (0xc00, 0x4c00)
1588 * The system call exception is invoked with "sc 0" and does not alter HV bit.
1589 * There is support for kernel code to invoke system calls but there are no
1592 * The hypercall is invoked with "sc 1" and sets HV=1.
1594 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
1595 * 0x4c00 virtual mode.
1599 * syscall register convention is in Documentation/powerpc/syscall64-abi.txt
1601 * For hypercalls, the register convention is as follows:
1604 * r3 volatile parameter and return value for status
1605 * r4-r10 volatile input and output value
1606 * r11 volatile hypercall number and output value
1607 * r12 volatile input and output value
1608 * r13-r31 nonvolatile
1612 * CR0-1 CR5-7 volatile
1614 * Other registers nonvolatile
1616 * The intersection of volatile registers that don't contain possible
1617 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry
1618 * without saving, though xer is not a good idea to use, as hardware may
1619 * interpret some bits so it may be costly to change them.
1621 .macro SYSTEM_CALL virt
1622 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1624 * There is a little bit of juggling to get syscall and hcall
1625 * working well. Save r13 in ctr to avoid using SPRG scratch
1628 * Userspace syscalls have already saved the PPR, hcalls must save
1629 * it before setting HMT_MEDIUM.
1633 std r10,PACA_EXGEN+EX_R10(r13)
1635 KVMTEST EXC_STD 0xc00 /* uses r10, branch to do_kvm_0xc00_system_call */
1643 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
1647 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
1650 /* We reach here with PACA in r13, r13 in r9. */
1657 __LOAD_HANDLER(r10, system_call_common)
1659 ld r10,PACAKMSR(r13)
1662 b . /* prevent speculative execution */
1665 mtmsrd r10,1 /* Set RI (EE=0) */
1666 #ifdef CONFIG_RELOCATABLE
1667 __LOAD_HANDLER(r10, system_call_common)
1671 b system_call_common
1675 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
1676 /* Fast LE/BE switch system call */
1677 1: mfspr r12,SPRN_SRR1
1681 RFI_TO_USER /* return to userspace */
1682 b . /* prevent speculative execution */
1686 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
1688 EXC_REAL_END(system_call, 0xc00, 0x100)
1690 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
1692 EXC_VIRT_END(system_call, 0x4c00, 0x100)
1694 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1696 * This is a hcall, so register convention is as above, with these
1700 * orig r10 saved in PACA
1702 TRAMP_KVM_BEGIN(do_kvm_0xc00)
1704 * Save the PPR (on systems that support it) before changing to
1705 * HMT_MEDIUM. That allows the KVM code to save that value into the
1706 * guest state (it is the guest's PPR value).
1708 OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR)
1710 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR)
1713 std r9,PACA_EXGEN+EX_R9(r13)
1715 KVM_HANDLER PACA_EXGEN, EXC_STD, 0xc00, 0
1719 EXC_REAL(single_step, 0xd00, 0x100)
1720 EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00)
1721 TRAMP_KVM(PACA_EXGEN, 0xd00)
1722 EXC_COMMON(single_step_common, 0xd00, single_step_exception)
1724 EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20)
1725 EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00)
1726 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
1727 EXC_COMMON_BEGIN(h_data_storage_common)
1729 std r10,PACA_EXGEN+EX_DAR(r13)
1730 mfspr r10,SPRN_HDSISR
1731 stw r10,PACA_EXGEN+EX_DSISR(r13)
1732 EXCEPTION_COMMON(PACA_EXGEN, 0xe00)
1734 RECONCILE_IRQ_STATE(r10, r11)
1735 addi r3,r1,STACK_FRAME_OVERHEAD
1736 BEGIN_MMU_FTR_SECTION
1737 ld r4,PACA_EXGEN+EX_DAR(r13)
1738 lwz r5,PACA_EXGEN+EX_DSISR(r13)
1743 MMU_FTR_SECTION_ELSE
1744 bl unknown_exception
1745 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX)
1749 EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20)
1750 EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20)
1751 TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
1752 EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
1755 EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20)
1756 EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40)
1757 TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
1758 EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
1762 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early
1763 * first, and then eventaully from there to the trampoline to get into virtual
1766 __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early)
1767 __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED)
1768 EXC_VIRT_NONE(0x4e60, 0x20)
1769 TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
1770 TRAMP_REAL_BEGIN(hmi_exception_early)
1771 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0xe60, 0
1772 mr r10,r1 /* Save r1 */
1773 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
1774 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1775 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */
1776 mfspr r12,SPRN_HSRR1 /* Save HSRR1 */
1777 EXCEPTION_PROLOG_COMMON_1()
1778 /* We don't touch AMR here, we never go to virtual mode */
1779 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
1780 EXCEPTION_PROLOG_COMMON_3(0xe60)
1781 addi r3,r1,STACK_FRAME_OVERHEAD
1782 BRANCH_LINK_TO_FAR(DOTSYM(hmi_exception_realmode)) /* Function call ABI */
1785 /* Windup the stack. */
1786 /* Move original HSRR0 and HSRR1 into the respective regs */
1806 HRFI_TO_USER_OR_KERNEL
1813 * Go to virtual mode and pull the HMI event information from
1816 .globl hmi_exception_after_realmode
1817 hmi_exception_after_realmode:
1819 EXCEPTION_PROLOG_0 PACA_EXGEN
1820 b tramp_real_hmi_exception
1822 EXC_COMMON_BEGIN(hmi_exception_common)
1823 EXCEPTION_COMMON(PACA_EXGEN, 0xe60)
1826 RECONCILE_IRQ_STATE(r10, r11)
1828 addi r3,r1,STACK_FRAME_OVERHEAD
1829 bl handle_hmi_exception
1832 EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20, IRQS_DISABLED)
1833 EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80, IRQS_DISABLED)
1834 TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
1835 #ifdef CONFIG_PPC_DOORBELL
1836 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1838 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1842 EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20, IRQS_DISABLED)
1843 EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0, IRQS_DISABLED)
1844 TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
1845 EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1848 EXC_REAL_NONE(0xec0, 0x20)
1849 EXC_VIRT_NONE(0x4ec0, 0x20)
1850 EXC_REAL_NONE(0xee0, 0x20)
1851 EXC_VIRT_NONE(0x4ee0, 0x20)
1854 EXC_REAL_OOL_MASKABLE(performance_monitor, 0xf00, 0x20, IRQS_PMI_DISABLED)
1855 EXC_VIRT_OOL_MASKABLE(performance_monitor, 0x4f00, 0x20, 0xf00, IRQS_PMI_DISABLED)
1856 TRAMP_KVM(PACA_EXGEN, 0xf00)
1857 EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1860 EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20)
1861 EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20)
1862 TRAMP_KVM(PACA_EXGEN, 0xf20)
1863 EXC_COMMON_BEGIN(altivec_unavailable_common)
1864 EXCEPTION_COMMON(PACA_EXGEN, 0xf20)
1865 #ifdef CONFIG_ALTIVEC
1868 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1869 BEGIN_FTR_SECTION_NESTED(69)
1870 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1871 * transaction), go do TM stuff
1873 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1875 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1878 b fast_exception_return
1879 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1880 2: /* User process was in a transaction */
1882 RECONCILE_IRQ_STATE(r10, r11)
1883 addi r3,r1,STACK_FRAME_OVERHEAD
1884 bl altivec_unavailable_tm
1888 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1891 RECONCILE_IRQ_STATE(r10, r11)
1892 addi r3,r1,STACK_FRAME_OVERHEAD
1893 bl altivec_unavailable_exception
1897 EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20)
1898 EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40)
1899 TRAMP_KVM(PACA_EXGEN, 0xf40)
1900 EXC_COMMON_BEGIN(vsx_unavailable_common)
1901 EXCEPTION_COMMON(PACA_EXGEN, 0xf40)
1905 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1906 BEGIN_FTR_SECTION_NESTED(69)
1907 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1908 * transaction), go do TM stuff
1910 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1912 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1915 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1916 2: /* User process was in a transaction */
1918 RECONCILE_IRQ_STATE(r10, r11)
1919 addi r3,r1,STACK_FRAME_OVERHEAD
1920 bl vsx_unavailable_tm
1924 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1927 RECONCILE_IRQ_STATE(r10, r11)
1928 addi r3,r1,STACK_FRAME_OVERHEAD
1929 bl vsx_unavailable_exception
1933 EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20)
1934 EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60)
1935 TRAMP_KVM(PACA_EXGEN, 0xf60)
1936 EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1939 EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20)
1940 EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80)
1941 TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
1942 EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1945 EXC_REAL_NONE(0xfa0, 0x20)
1946 EXC_VIRT_NONE(0x4fa0, 0x20)
1947 EXC_REAL_NONE(0xfc0, 0x20)
1948 EXC_VIRT_NONE(0x4fc0, 0x20)
1949 EXC_REAL_NONE(0xfe0, 0x20)
1950 EXC_VIRT_NONE(0x4fe0, 0x20)
1952 EXC_REAL_NONE(0x1000, 0x100)
1953 EXC_VIRT_NONE(0x5000, 0x100)
1954 EXC_REAL_NONE(0x1100, 0x100)
1955 EXC_VIRT_NONE(0x5100, 0x100)
1957 #ifdef CONFIG_CBE_RAS
1958 EXC_REAL_HV(cbe_system_error, 0x1200, 0x100)
1959 EXC_VIRT_NONE(0x5200, 0x100)
1960 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
1961 EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1962 #else /* CONFIG_CBE_RAS */
1963 EXC_REAL_NONE(0x1200, 0x100)
1964 EXC_VIRT_NONE(0x5200, 0x100)
1968 EXC_REAL(instruction_breakpoint, 0x1300, 0x100)
1969 EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300)
1970 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
1971 EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1973 EXC_REAL_NONE(0x1400, 0x100)
1974 EXC_VIRT_NONE(0x5400, 0x100)
1976 EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
1977 mtspr SPRN_SPRG_HSCRATCH0,r13
1978 EXCEPTION_PROLOG_0 PACA_EXGEN
1979 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 0, 0x1500, 0
1981 #ifdef CONFIG_PPC_DENORMALISATION
1982 mfspr r10,SPRN_HSRR1
1983 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */
1987 KVMTEST EXC_HV 0x1500
1988 EXCEPTION_PROLOG_2_REAL denorm_common, EXC_HV, 1
1989 EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
1991 #ifdef CONFIG_PPC_DENORMALISATION
1992 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
1993 b exc_real_0x1500_denorm_exception_hv
1994 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
1996 EXC_VIRT_NONE(0x5500, 0x100)
1999 TRAMP_KVM_HV(PACA_EXGEN, 0x1500)
2001 #ifdef CONFIG_PPC_DENORMALISATION
2002 TRAMP_REAL_BEGIN(denorm_assist)
2005 * To denormalise we need to move a copy of the register to itself.
2006 * For POWER6 do that here for all FP regs.
2009 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
2010 xori r10,r10,(MSR_FE0|MSR_FE1)
2022 * To denormalise we need to move a copy of the register to itself.
2023 * For POWER7 do that here for the first 32 VSX registers only.
2026 oris r10,r10,MSR_VSX@h
2032 XVCPSGNDP(.Lreg,.Lreg,.Lreg)
2036 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
2040 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
2042 * To denormalise we need to move a copy of the register to itself.
2043 * For POWER8 we need to do that for all 64 VSX registers
2047 XVCPSGNDP(.Lreg,.Lreg,.Lreg)
2052 mfspr r11,SPRN_HSRR0
2054 mtspr SPRN_HSRR0,r11
2056 ld r9,PACA_EXGEN+EX_R9(r13)
2057 RESTORE_PPR_PACA(PACA_EXGEN, r10)
2059 ld r10,PACA_EXGEN+EX_CFAR(r13)
2061 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
2062 ld r10,PACA_EXGEN+EX_R10(r13)
2063 ld r11,PACA_EXGEN+EX_R11(r13)
2064 ld r12,PACA_EXGEN+EX_R12(r13)
2065 ld r13,PACA_EXGEN+EX_R13(r13)
2070 EXC_COMMON(denorm_common, 0x1500, unknown_exception)
2073 #ifdef CONFIG_CBE_RAS
2074 EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100)
2075 EXC_VIRT_NONE(0x5600, 0x100)
2076 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
2077 EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
2078 #else /* CONFIG_CBE_RAS */
2079 EXC_REAL_NONE(0x1600, 0x100)
2080 EXC_VIRT_NONE(0x5600, 0x100)
2084 EXC_REAL(altivec_assist, 0x1700, 0x100)
2085 EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700)
2086 TRAMP_KVM(PACA_EXGEN, 0x1700)
2087 #ifdef CONFIG_ALTIVEC
2088 EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
2090 EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
2094 #ifdef CONFIG_CBE_RAS
2095 EXC_REAL_HV(cbe_thermal, 0x1800, 0x100)
2096 EXC_VIRT_NONE(0x5800, 0x100)
2097 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
2098 EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
2099 #else /* CONFIG_CBE_RAS */
2100 EXC_REAL_NONE(0x1800, 0x100)
2101 EXC_VIRT_NONE(0x5800, 0x100)
2104 #ifdef CONFIG_PPC_WATCHDOG
2106 #define MASKED_DEC_HANDLER_LABEL 3f
2108 #define MASKED_DEC_HANDLER(_H) \
2110 std r12,PACA_EXGEN+EX_R12(r13); \
2111 GET_SCRATCH0(r10); \
2112 std r10,PACA_EXGEN+EX_R13(r13); \
2113 EXCEPTION_PROLOG_2_REAL soft_nmi_common, _H, 1
2116 * Branch to soft_nmi_interrupt using the emergency stack. The emergency
2117 * stack is one that is usable by maskable interrupts so long as MSR_EE
2118 * remains off. It is used for recovery when something has corrupted the
2119 * normal kernel stack, for example. The "soft NMI" must not use the process
2120 * stack because we want irq disabled sections to avoid touching the stack
2121 * at all (other than PMU interrupts), so use the emergency stack for this,
2122 * and run it entirely with interrupts hard disabled.
2124 EXC_COMMON_BEGIN(soft_nmi_common)
2126 ld r1,PACAEMERGSP(r13)
2127 subi r1,r1,INT_FRAME_SIZE
2128 EXCEPTION_COMMON_STACK(PACA_EXGEN, 0x900)
2130 RECONCILE_IRQ_STATE(r10, r11)
2131 addi r3,r1,STACK_FRAME_OVERHEAD
2132 bl soft_nmi_interrupt
2135 #else /* CONFIG_PPC_WATCHDOG */
2136 #define MASKED_DEC_HANDLER_LABEL 2f /* normal return */
2137 #define MASKED_DEC_HANDLER(_H)
2138 #endif /* CONFIG_PPC_WATCHDOG */
2141 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
2142 * - If it was a decrementer interrupt, we bump the dec to max and and return.
2143 * - If it was a doorbell we return immediately since doorbells are edge
2144 * triggered and won't automatically refire.
2145 * - If it was a HMI we return immediately since we handled it in realmode
2146 * and it won't refire.
2147 * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return.
2148 * This is called with r10 containing the value to OR to the paca field.
2150 .macro MASKED_INTERRUPT hsrr
2156 std r11,PACA_EXGEN+EX_R11(r13)
2157 lbz r11,PACAIRQHAPPENED(r13)
2159 stb r11,PACAIRQHAPPENED(r13)
2160 cmpwi r10,PACA_IRQ_DEC
2165 b MASKED_DEC_HANDLER_LABEL
2166 1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK
2169 mfspr r10,SPRN_HSRR1
2170 xori r10,r10,MSR_EE /* clear MSR_EE */
2171 mtspr SPRN_HSRR1,r10
2174 xori r10,r10,MSR_EE /* clear MSR_EE */
2177 ori r11,r11,PACA_IRQ_HARD_DIS
2178 stb r11,PACAIRQHAPPENED(r13)
2182 ld r9,PACA_EXGEN+EX_R9(r13)
2183 ld r10,PACA_EXGEN+EX_R10(r13)
2184 ld r11,PACA_EXGEN+EX_R11(r13)
2185 /* returns to kernel where r13 must be set up, so don't restore it */
2192 MASKED_DEC_HANDLER(\hsrr\())
2195 TRAMP_REAL_BEGIN(stf_barrier_fallback)
2196 std r9,PACA_EXRFI+EX_R9(r13)
2197 std r10,PACA_EXRFI+EX_R10(r13)
2199 ld r9,PACA_EXRFI+EX_R9(r13)
2200 ld r10,PACA_EXRFI+EX_R10(r13)
2208 TRAMP_REAL_BEGIN(rfi_flush_fallback)
2211 std r1,PACA_EXRFI+EX_R12(r13)
2212 ld r1,PACAKSAVE(r13)
2213 std r9,PACA_EXRFI+EX_R9(r13)
2214 std r10,PACA_EXRFI+EX_R10(r13)
2215 std r11,PACA_EXRFI+EX_R11(r13)
2217 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
2218 ld r11,PACA_L1D_FLUSH_SIZE(r13)
2219 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
2221 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
2223 /* order ld/st prior to dcbt stop all streams with flushing */
2227 * The load adresses are at staggered offsets within cachelines,
2228 * which suits some pipelines better (on others it should not
2232 ld r11,(0x80 + 8)*0(r10)
2233 ld r11,(0x80 + 8)*1(r10)
2234 ld r11,(0x80 + 8)*2(r10)
2235 ld r11,(0x80 + 8)*3(r10)
2236 ld r11,(0x80 + 8)*4(r10)
2237 ld r11,(0x80 + 8)*5(r10)
2238 ld r11,(0x80 + 8)*6(r10)
2239 ld r11,(0x80 + 8)*7(r10)
2244 ld r9,PACA_EXRFI+EX_R9(r13)
2245 ld r10,PACA_EXRFI+EX_R10(r13)
2246 ld r11,PACA_EXRFI+EX_R11(r13)
2247 ld r1,PACA_EXRFI+EX_R12(r13)
2251 TRAMP_REAL_BEGIN(hrfi_flush_fallback)
2254 std r1,PACA_EXRFI+EX_R12(r13)
2255 ld r1,PACAKSAVE(r13)
2256 std r9,PACA_EXRFI+EX_R9(r13)
2257 std r10,PACA_EXRFI+EX_R10(r13)
2258 std r11,PACA_EXRFI+EX_R11(r13)
2260 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
2261 ld r11,PACA_L1D_FLUSH_SIZE(r13)
2262 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
2264 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
2266 /* order ld/st prior to dcbt stop all streams with flushing */
2270 * The load adresses are at staggered offsets within cachelines,
2271 * which suits some pipelines better (on others it should not
2275 ld r11,(0x80 + 8)*0(r10)
2276 ld r11,(0x80 + 8)*1(r10)
2277 ld r11,(0x80 + 8)*2(r10)
2278 ld r11,(0x80 + 8)*3(r10)
2279 ld r11,(0x80 + 8)*4(r10)
2280 ld r11,(0x80 + 8)*5(r10)
2281 ld r11,(0x80 + 8)*6(r10)
2282 ld r11,(0x80 + 8)*7(r10)
2287 ld r9,PACA_EXRFI+EX_R9(r13)
2288 ld r10,PACA_EXRFI+EX_R10(r13)
2289 ld r11,PACA_EXRFI+EX_R11(r13)
2290 ld r1,PACA_EXRFI+EX_R12(r13)
2295 * Real mode exceptions actually use this too, but alternate
2296 * instruction code patches (which end up in the common .text area)
2297 * cannot reach these if they are put there.
2299 USE_FIXED_SECTION(virt_trampolines)
2300 MASKED_INTERRUPT EXC_STD
2301 MASKED_INTERRUPT EXC_HV
2303 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
2304 TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
2306 * Here all GPRs are unchanged from when the interrupt happened
2307 * except for r13, which is saved in SPRG_SCRATCH0.
2309 mfspr r13, SPRN_SRR0
2311 mtspr SPRN_SRR0, r13
2316 TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
2318 * Here all GPRs are unchanged from when the interrupt happened
2319 * except for r13, which is saved in SPRG_SCRATCH0.
2321 mfspr r13, SPRN_HSRR0
2323 mtspr SPRN_HSRR0, r13
2330 * Ensure that any handlers that get invoked from the exception prologs
2331 * above are below the first 64KB (0x10000) of the kernel image because
2332 * the prologs assemble the addresses of these handlers using the
2333 * LOAD_HANDLER macro, which uses an ori instruction.
2336 /*** Common interrupt handlers ***/
2340 * Relocation-on interrupts: A subset of the interrupts can be delivered
2341 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
2342 * it. Addresses are the same as the original interrupt addresses, but
2343 * offset by 0xc000000000004000.
2344 * It's impossible to receive interrupts below 0x300 via this mechanism.
2345 * KVM: None of these traps are from the guest ; anything that escalated
2346 * to HV=1 from HV=0 is delivered via real mode handlers.
2350 * This uses the standard macro, since the original 0x300 vector
2351 * only has extra guff for STAB-based processors -- which never
2355 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
2356 b __ppc64_runlatch_on
2358 USE_FIXED_SECTION(virt_trampolines)
2360 * The __end_interrupts marker must be past the out-of-line (OOL)
2361 * handlers, so that they are copied to real address 0x100 when running
2362 * a relocatable kernel. This ensures they can be reached from the short
2363 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
2364 * directly, without using LOAD_HANDLER().
2367 .globl __end_interrupts
2369 DEFINE_FIXED_SYMBOL(__end_interrupts)
2371 #ifdef CONFIG_PPC_970_NAP
2372 EXC_COMMON_BEGIN(power4_fixup_nap)
2374 std r9,TI_LOCAL_FLAGS(r11)
2375 ld r10,_LINK(r1) /* make idle task do the */
2376 std r10,_NIP(r1) /* equivalent of a blr */
2380 CLOSE_FIXED_SECTION(real_vectors);
2381 CLOSE_FIXED_SECTION(real_trampolines);
2382 CLOSE_FIXED_SECTION(virt_vectors);
2383 CLOSE_FIXED_SECTION(virt_trampolines);
2390 .balign IFETCH_ALIGN_BYTES
2392 #ifdef CONFIG_PPC_BOOK3S_64
2393 lis r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h
2394 ori r0,r0,DSISR_BAD_FAULT_64S@l
2395 and. r0,r4,r0 /* weird error? */
2396 bne- handle_page_fault /* if not, try to insert a HPTE */
2397 ld r11, PACA_THREAD_INFO(r13)
2398 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
2399 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
2400 bne 77f /* then don't call hash_page now */
2403 * r3 contains the faulting address
2405 * r5 contains the trap number
2408 * at return r3 = 0 for success, 1 for page fault, negative for error
2412 bl __hash_page /* build HPTE if possible */
2413 cmpdi r3,0 /* see if __hash_page succeeded */
2416 beq fast_exc_return_irq /* Return from exception on success */
2421 /* Reload DSISR into r4 for the DABR check below */
2423 #endif /* CONFIG_PPC_BOOK3S_64 */
2425 /* Here we have a page fault that hash_page can't handle. */
2427 11: andis. r0,r4,DSISR_DABRMATCH@h
2428 bne- handle_dabr_fault
2431 addi r3,r1,STACK_FRAME_OVERHEAD
2434 beq+ ret_from_except_lite
2437 addi r3,r1,STACK_FRAME_OVERHEAD
2442 /* We have a data breakpoint exception - handle it */
2447 addi r3,r1,STACK_FRAME_OVERHEAD
2450 * do_break() may have changed the NV GPRS while handling a breakpoint.
2451 * If so, we need to restore them with their updated values. Don't use
2452 * ret_from_except_lite here.
2457 #ifdef CONFIG_PPC_BOOK3S_64
2458 /* We have a page fault that hash_page could handle but HV refused
2463 addi r3,r1,STACK_FRAME_OVERHEAD
2470 * We come here as a result of a DSI at a point where we don't want
2471 * to call hash_page, such as when we are accessing memory (possibly
2472 * user memory) inside a PMU interrupt that occurred while interrupts
2473 * were soft-disabled. We want to invoke the exception handler for
2474 * the access, or panic if there isn't a handler.
2478 addi r3,r1,STACK_FRAME_OVERHEAD
2484 * Here we have detected that the kernel stack pointer is bad.
2485 * R9 contains the saved CR, r13 points to the paca,
2486 * r10 contains the (bad) kernel stack pointer,
2487 * r11 and r12 contain the saved SRR0 and SRR1.
2488 * We switch to using an emergency stack, save the registers there,
2489 * and call kernel_bad_stack(), which panics.
2492 ld r1,PACAEMERGSP(r13)
2493 subi r1,r1,64+INT_FRAME_SIZE
2499 mfspr r12,SPRN_DSISR
2525 std r10,ORIG_GPR3(r1)
2526 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
2529 lhz r12,PACA_TRAP_SAVE(r13)
2531 addi r11,r1,INT_FRAME_SIZE
2536 ld r11,exception_marker@toc(r2)
2538 std r11,STACK_FRAME_OVERHEAD-16(r1)
2539 1: addi r3,r1,STACK_FRAME_OVERHEAD
2542 _ASM_NOKPROBE_SYMBOL(bad_stack);
2545 * When doorbell is triggered from system reset wakeup, the message is
2546 * not cleared, so it would fire again when EE is enabled.
2548 * When coming from local_irq_enable, there may be the same problem if
2549 * we were hard disabled.
2551 * Execute msgclr to clear pending exceptions before handling it.
2553 h_doorbell_common_msgclr:
2554 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
2558 doorbell_super_common_msgclr:
2559 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
2561 b doorbell_super_common
2564 * Called from arch_local_irq_enable when an interrupt needs
2565 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
2566 * which kind of interrupt. MSR:EE is already off. We generate a
2567 * stackframe like if a real interrupt had happened.
2569 * Note: While MSR:EE is off, we need to make sure that _MSR
2570 * in the generated frame has EE set to 1 or the exception
2571 * handler will not properly re-enable them.
2573 * Note that we don't specify LR as the NIP (return address) for
2574 * the interrupt because that would unbalance the return branch
2577 _GLOBAL(__replay_interrupt)
2578 /* We are going to jump to the exception common code which
2579 * will retrieve various register values from the PACA which
2580 * we don't give a damn about, so we don't bother storing them.
2583 LOAD_REG_ADDR(r11, replay_interrupt_return)
2587 beq decrementer_common
2590 beq h_virt_irq_common
2592 beq hardware_interrupt_common
2593 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300)
2595 beq performance_monitor_common
2598 beq h_doorbell_common_msgclr
2600 beq hmi_exception_common
2603 beq doorbell_super_common_msgclr
2604 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
2605 replay_interrupt_return:
2608 _ASM_NOKPROBE_SYMBOL(__replay_interrupt)
projects / linux-2.6-block.git / blob