1 /* SPDX-License-Identifier: GPL-2.0 */
3 * This file contains the 64-bit "server" PowerPC variant
4 * of the low level exception handling including exception
5 * vectors, exception return, part of the slb and stab
6 * handling and other fixed offset specific things.
8 * This file is meant to be #included from head_64.S due to
9 * position dependent assembly.
11 * Most of this originates from head_64.S and thus has the same
16 #include <asm/hw_irq.h>
17 #include <asm/exception-64s.h>
18 #include <asm/ptrace.h>
19 #include <asm/cpuidle.h>
20 #include <asm/head-64.h>
21 #include <asm/feature-fixups.h>
25 * We're short on space and time in the exception prolog, so we can't
26 * use the normal LOAD_REG_IMMEDIATE macro to load the address of label.
27 * Instead we get the base of the kernel from paca->kernelbase and or in the low
28 * part of label. This requires that the label be within 64KB of kernelbase, and
29 * that kernelbase be 64K aligned.
31 #define LOAD_HANDLER(reg, label) \
32 ld reg,PACAKBASE(r13); /* get high part of &label */ \
33 ori reg,reg,FIXED_SYMBOL_ABS_ADDR(label)
35 #define __LOAD_HANDLER(reg, label) \
36 ld reg,PACAKBASE(r13); \
37 ori reg,reg,(ABS_ADDR(label))@l
40 * Branches from unrelocated code (e.g., interrupts) to labels outside
41 * head-y require >64K offsets.
43 #define __LOAD_FAR_HANDLER(reg, label) \
44 ld reg,PACAKBASE(r13); \
45 ori reg,reg,(ABS_ADDR(label))@l; \
46 addis reg,reg,(ABS_ADDR(label))@h
48 /* Exception register prefixes */
52 #if defined(CONFIG_RELOCATABLE)
54 * If we support interrupts with relocation on AND we're a relocatable kernel,
55 * we need to use CTR to get to the 2nd level handler. So, save/restore it
58 #define SAVE_CTR(reg, area) mfctr reg ; std reg,area+EX_CTR(r13)
59 #define GET_CTR(reg, area) ld reg,area+EX_CTR(r13)
60 #define RESTORE_CTR(reg, area) ld reg,area+EX_CTR(r13) ; mtctr reg
62 /* ...else CTR is unused and in register. */
63 #define SAVE_CTR(reg, area)
64 #define GET_CTR(reg, area) mfctr reg
65 #define RESTORE_CTR(reg, area)
69 * PPR save/restore macros used in exceptions-64s.S
70 * Used for P7 or later processors
72 #define SAVE_PPR(area, ra) \
73 BEGIN_FTR_SECTION_NESTED(940) \
74 ld ra,area+EX_PPR(r13); /* Read PPR from paca */ \
76 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,940)
78 #define RESTORE_PPR_PACA(area, ra) \
79 BEGIN_FTR_SECTION_NESTED(941) \
80 ld ra,area+EX_PPR(r13); \
82 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,941)
85 * Get an SPR into a register if the CPU has the given feature
87 #define OPT_GET_SPR(ra, spr, ftr) \
88 BEGIN_FTR_SECTION_NESTED(943) \
90 END_FTR_SECTION_NESTED(ftr,ftr,943)
93 * Set an SPR from a register if the CPU has the given feature
95 #define OPT_SET_SPR(ra, spr, ftr) \
96 BEGIN_FTR_SECTION_NESTED(943) \
98 END_FTR_SECTION_NESTED(ftr,ftr,943)
101 * Save a register to the PACA if the CPU has the given feature
103 #define OPT_SAVE_REG_TO_PACA(offset, ra, ftr) \
104 BEGIN_FTR_SECTION_NESTED(943) \
105 std ra,offset(r13); \
106 END_FTR_SECTION_NESTED(ftr,ftr,943)
108 .macro EXCEPTION_PROLOG_0 area
110 std r9,\area\()+EX_R9(r13) /* save r9 */
111 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR)
113 std r10,\area\()+EX_R10(r13) /* save r10 - r12 */
114 OPT_GET_SPR(r10, SPRN_CFAR, CPU_FTR_CFAR)
117 .macro EXCEPTION_PROLOG_1 hsrr, area, kvm, vec, bitmask
118 OPT_SAVE_REG_TO_PACA(\area\()+EX_PPR, r9, CPU_FTR_HAS_PPR)
119 OPT_SAVE_REG_TO_PACA(\area\()+EX_CFAR, r10, CPU_FTR_CFAR)
121 SAVE_CTR(r10, \area\())
127 lbz r10,PACAIRQSOFTMASK(r13)
128 andi. r10,r10,\bitmask
129 /* Associate vector numbers with bits in paca->irq_happened */
130 .if \vec == 0x500 || \vec == 0xea0
132 .elseif \vec == 0x900
134 .elseif \vec == 0xa00 || \vec == 0xe80
135 li r10,PACA_IRQ_DBELL
136 .elseif \vec == 0xe60
138 .elseif \vec == 0xf00
141 .abort "Bad maskable vector"
145 bne masked_Hinterrupt
151 std r11,\area\()+EX_R11(r13)
152 std r12,\area\()+EX_R12(r13)
154 std r10,\area\()+EX_R13(r13)
157 .macro EXCEPTION_PROLOG_2_REAL label, hsrr, set_ri
158 ld r10,PACAKMSR(r13) /* get MSR value for kernel */
160 xori r10,r10,MSR_RI /* Clear MSR_RI */
163 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
165 mfspr r11,SPRN_SRR0 /* save SRR0 */
167 LOAD_HANDLER(r12, \label\())
170 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
175 mfspr r12,SPRN_SRR1 /* and SRR1 */
179 b . /* prevent speculative execution */
182 .macro EXCEPTION_PROLOG_2_VIRT label, hsrr
183 #ifdef CONFIG_RELOCATABLE
185 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
187 mfspr r11,SPRN_SRR0 /* save SRR0 */
189 LOAD_HANDLER(r12, \label\())
192 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
194 mfspr r12,SPRN_SRR1 /* and HSRR1 */
197 mtmsrd r10,1 /* Set RI (EE=0) */
201 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
202 mfspr r12,SPRN_HSRR1 /* and HSRR1 */
204 mfspr r11,SPRN_SRR0 /* save SRR0 */
205 mfspr r12,SPRN_SRR1 /* and SRR1 */
208 mtmsrd r10,1 /* Set RI (EE=0) */
214 * Branch to label using its 0xC000 address. This results in instruction
215 * address suitable for MSR[IR]=0 or 1, which allows relocation to be turned
216 * on using mtmsr rather than rfid.
218 * This could set the 0xc bits for !RELOCATABLE as an immediate, rather than
219 * load KBASE for a slight optimisation.
221 #define BRANCH_TO_C000(reg, label) \
222 __LOAD_HANDLER(reg, label); \
226 #ifdef CONFIG_RELOCATABLE
227 #define BRANCH_LINK_TO_FAR(label) \
228 __LOAD_FAR_HANDLER(r12, label); \
233 #define BRANCH_LINK_TO_FAR(label) \
237 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
238 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
240 * If hv is possible, interrupts come into to the hv version
241 * of the kvmppc_interrupt code, which then jumps to the PR handler,
242 * kvmppc_interrupt_pr, if the guest is a PR guest.
244 #define kvmppc_interrupt kvmppc_interrupt_hv
246 #define kvmppc_interrupt kvmppc_interrupt_pr
249 .macro KVMTEST hsrr, n
250 lbz r10,HSTATE_IN_GUEST(r13)
259 .macro KVM_HANDLER area, hsrr, n, skip
261 cmpwi r10,KVM_GUEST_MODE_SKIP
264 BEGIN_FTR_SECTION_NESTED(947)
265 ld r10,\area+EX_CFAR(r13)
266 std r10,HSTATE_CFAR(r13)
267 END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947)
270 BEGIN_FTR_SECTION_NESTED(948)
271 ld r10,\area+EX_PPR(r13)
272 std r10,HSTATE_PPR(r13)
273 END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948)
274 ld r10,\area+EX_R10(r13)
275 std r12,HSTATE_SCRATCH0(r13)
277 /* HSRR variants have the 0x2 bit added to their trap number */
279 ori r12,r12,(\n + 0x2)
284 #ifdef CONFIG_RELOCATABLE
286 * KVM requires __LOAD_FAR_HANDLER beause kvmppc_interrupt lives
287 * outside the head section. CONFIG_RELOCATABLE KVM expects CTR
288 * to be saved in HSTATE_SCRATCH1.
291 std r9,HSTATE_SCRATCH1(r13)
292 __LOAD_FAR_HANDLER(r9, kvmppc_interrupt)
294 ld r9,\area+EX_R9(r13)
297 ld r9,\area+EX_R9(r13)
304 ld r9,\area+EX_R9(r13)
305 ld r10,\area+EX_R10(r13)
307 b kvmppc_skip_Hinterrupt
309 b kvmppc_skip_interrupt
315 .macro KVMTEST hsrr, n
317 .macro KVM_HANDLER area, hsrr, n, skip
321 #define EXCEPTION_PROLOG_COMMON_1() \
322 std r9,_CCR(r1); /* save CR in stackframe */ \
323 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
324 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
325 std r10,0(r1); /* make stack chain pointer */ \
326 std r0,GPR0(r1); /* save r0 in stackframe */ \
327 std r10,GPR1(r1); /* save r1 in stackframe */ \
331 * The common exception prolog is used for all except a few exceptions
332 * such as a segment miss on a kernel address. We have to be prepared
333 * to take another exception from the point where we first touch the
334 * kernel stack onwards.
336 * On entry r13 points to the paca, r9-r13 are saved in the paca,
337 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
338 * SRR1, and relocation is on.
340 #define EXCEPTION_PROLOG_COMMON(n, area) \
341 andi. r10,r12,MSR_PR; /* See if coming from user */ \
342 mr r10,r1; /* Save r1 */ \
343 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
345 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
346 1: cmpdi cr1,r1,-INT_FRAME_SIZE; /* check if r1 is in userspace */ \
347 blt+ cr1,3f; /* abort if it is */ \
348 li r1,(n); /* will be reloaded later */ \
349 sth r1,PACA_TRAP_SAVE(r13); \
350 std r3,area+EX_R3(r13); \
351 addi r3,r13,area; /* r3 -> where regs are saved*/ \
352 RESTORE_CTR(r1, area); \
354 3: EXCEPTION_PROLOG_COMMON_1(); \
355 kuap_save_amr_and_lock r9, r10, cr1, cr0; \
356 beq 4f; /* if from kernel mode */ \
357 ACCOUNT_CPU_USER_ENTRY(r13, r9, r10); \
358 SAVE_PPR(area, r9); \
359 4: EXCEPTION_PROLOG_COMMON_2(area) \
360 EXCEPTION_PROLOG_COMMON_3(n) \
363 /* Save original regs values from save area to stack frame. */
364 #define EXCEPTION_PROLOG_COMMON_2(area) \
365 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
366 ld r10,area+EX_R10(r13); \
369 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
370 ld r10,area+EX_R12(r13); \
371 ld r11,area+EX_R13(r13); \
375 BEGIN_FTR_SECTION_NESTED(66); \
376 ld r10,area+EX_CFAR(r13); \
377 std r10,ORIG_GPR3(r1); \
378 END_FTR_SECTION_NESTED(CPU_FTR_CFAR, CPU_FTR_CFAR, 66); \
379 GET_CTR(r10, area); \
382 #define EXCEPTION_PROLOG_COMMON_3(n) \
383 std r2,GPR2(r1); /* save r2 in stackframe */ \
384 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
385 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
386 mflr r9; /* Get LR, later save to stack */ \
387 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
389 lbz r10,PACAIRQSOFTMASK(r13); \
390 mfspr r11,SPRN_XER; /* save XER in stackframe */ \
394 std r9,_TRAP(r1); /* set trap number */ \
396 ld r11,exception_marker@toc(r2); \
397 std r10,RESULT(r1); /* clear regs->result */ \
398 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
400 #define RUNLATCH_ON \
402 ld r3, PACA_THREAD_INFO(r13); \
403 ld r4,TI_LOCAL_FLAGS(r3); \
404 andi. r0,r4,_TLF_RUNLATCH; \
405 beql ppc64_runlatch_on_trampoline; \
406 END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
408 #define EXCEPTION_COMMON(area, trap) \
409 EXCEPTION_PROLOG_COMMON(trap, area); \
412 * Exception where stack is already set in r1, r1 is saved in r10
414 #define EXCEPTION_COMMON_STACK(area, trap) \
415 EXCEPTION_PROLOG_COMMON_1(); \
416 kuap_save_amr_and_lock r9, r10, cr1; \
417 EXCEPTION_PROLOG_COMMON_2(area); \
418 EXCEPTION_PROLOG_COMMON_3(trap)
421 * When the idle code in power4_idle puts the CPU into NAP mode,
422 * it has to do so in a loop, and relies on the external interrupt
423 * and decrementer interrupt entry code to get it out of the loop.
424 * It sets the _TLF_NAPPING bit in current_thread_info()->local_flags
425 * to signal that it is in the loop and needs help to get out.
427 #ifdef CONFIG_PPC_970_NAP
430 ld r11, PACA_THREAD_INFO(r13); \
431 ld r9,TI_LOCAL_FLAGS(r11); \
432 andi. r10,r9,_TLF_NAPPING; \
433 bnel power4_fixup_nap; \
434 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
440 * Following are the BOOK3S exception handler helper macros.
441 * Handlers come in a number of types, and each type has a number of varieties.
443 * EXC_REAL_* - real, unrelocated exception vectors
444 * EXC_VIRT_* - virt (AIL), unrelocated exception vectors
445 * TRAMP_REAL_* - real, unrelocated helpers (virt can call these)
446 * TRAMP_VIRT_* - virt, unreloc helpers (in practice, real can use)
447 * TRAMP_KVM - KVM handlers that get put into real, unrelocated
448 * EXC_COMMON - virt, relocated common handlers
450 * The EXC handlers are given a name, and branch to name_common, or the
451 * appropriate KVM or masking function. Vector handler verieties are as
454 * EXC_{REAL|VIRT}_BEGIN/END - used to open-code the exception
456 * EXC_{REAL|VIRT} - standard exception
458 * EXC_{REAL|VIRT}_suffix
460 * - _MASKABLE - maskable exception
461 * - _OOL - out of line with trampoline to common handler
462 * - _HV - HV exception
464 * There can be combinations, e.g., EXC_VIRT_OOL_MASKABLE_HV
466 * The one unusual case is __EXC_REAL_OOL_HV_DIRECT, which is
467 * an OOL vector that branches to a specified handler rather than the usual
468 * trampoline that goes to common. It, and other underscore macros, should
471 * KVM handlers come in the following verieties:
477 * COMMON handlers come in the following verieties:
478 * EXC_COMMON_BEGIN/END - used to open-code the handler
482 * TRAMP_REAL and TRAMP_VIRT can be used with BEGIN/END. KVM
483 * and OOL handlers are implemented as types of TRAMP and TRAMP_VIRT handlers.
486 #define __EXC_REAL(name, start, size, area) \
487 EXC_REAL_BEGIN(name, start, size); \
488 SET_SCRATCH0(r13); /* save r13 */ \
489 EXCEPTION_PROLOG_0 area ; \
490 EXCEPTION_PROLOG_1 EXC_STD, area, 1, start, 0 ; \
491 EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \
492 EXC_REAL_END(name, start, size)
494 #define EXC_REAL(name, start, size) \
495 __EXC_REAL(name, start, size, PACA_EXGEN)
497 #define __EXC_VIRT(name, start, size, realvec, area) \
498 EXC_VIRT_BEGIN(name, start, size); \
499 SET_SCRATCH0(r13); /* save r13 */ \
500 EXCEPTION_PROLOG_0 area ; \
501 EXCEPTION_PROLOG_1 EXC_STD, area, 0, realvec, 0; \
502 EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \
503 EXC_VIRT_END(name, start, size)
505 #define EXC_VIRT(name, start, size, realvec) \
506 __EXC_VIRT(name, start, size, realvec, PACA_EXGEN)
508 #define EXC_REAL_MASKABLE(name, start, size, bitmask) \
509 EXC_REAL_BEGIN(name, start, size); \
510 SET_SCRATCH0(r13); /* save r13 */ \
511 EXCEPTION_PROLOG_0 PACA_EXGEN ; \
512 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, start, bitmask ; \
513 EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1 ; \
514 EXC_REAL_END(name, start, size)
516 #define EXC_VIRT_MASKABLE(name, start, size, realvec, bitmask) \
517 EXC_VIRT_BEGIN(name, start, size); \
518 SET_SCRATCH0(r13); /* save r13 */ \
519 EXCEPTION_PROLOG_0 PACA_EXGEN ; \
520 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, bitmask ; \
521 EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD ; \
522 EXC_VIRT_END(name, start, size)
524 #define EXC_REAL_HV(name, start, size) \
525 EXC_REAL_BEGIN(name, start, size); \
526 SET_SCRATCH0(r13); /* save r13 */ \
527 EXCEPTION_PROLOG_0 PACA_EXGEN; \
528 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, start, 0 ; \
529 EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1 ; \
530 EXC_REAL_END(name, start, size)
532 #define EXC_VIRT_HV(name, start, size, realvec) \
533 EXC_VIRT_BEGIN(name, start, size); \
534 SET_SCRATCH0(r13); /* save r13 */ \
535 EXCEPTION_PROLOG_0 PACA_EXGEN; \
536 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0 ; \
537 EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV ; \
538 EXC_VIRT_END(name, start, size)
540 #define __EXC_REAL_OOL(name, start, size) \
541 EXC_REAL_BEGIN(name, start, size); \
543 EXCEPTION_PROLOG_0 PACA_EXGEN ; \
544 b tramp_real_##name ; \
545 EXC_REAL_END(name, start, size)
547 #define __TRAMP_REAL_OOL(name, vec) \
548 TRAMP_REAL_BEGIN(tramp_real_##name); \
549 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, 0 ; \
550 EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1
552 #define EXC_REAL_OOL(name, start, size) \
553 __EXC_REAL_OOL(name, start, size); \
554 __TRAMP_REAL_OOL(name, start)
556 #define __EXC_REAL_OOL_MASKABLE(name, start, size) \
557 __EXC_REAL_OOL(name, start, size)
559 #define __TRAMP_REAL_OOL_MASKABLE(name, vec, bitmask) \
560 TRAMP_REAL_BEGIN(tramp_real_##name); \
561 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, vec, bitmask ; \
562 EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1
564 #define EXC_REAL_OOL_MASKABLE(name, start, size, bitmask) \
565 __EXC_REAL_OOL_MASKABLE(name, start, size); \
566 __TRAMP_REAL_OOL_MASKABLE(name, start, bitmask)
568 #define __EXC_REAL_OOL_HV_DIRECT(name, start, size, handler) \
569 EXC_REAL_BEGIN(name, start, size); \
571 EXCEPTION_PROLOG_0 PACA_EXGEN ; \
573 EXC_REAL_END(name, start, size)
575 #define __EXC_REAL_OOL_HV(name, start, size) \
576 __EXC_REAL_OOL(name, start, size)
578 #define __TRAMP_REAL_OOL_HV(name, vec) \
579 TRAMP_REAL_BEGIN(tramp_real_##name); \
580 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, 0 ; \
581 EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1
583 #define EXC_REAL_OOL_HV(name, start, size) \
584 __EXC_REAL_OOL_HV(name, start, size); \
585 __TRAMP_REAL_OOL_HV(name, start)
587 #define __EXC_REAL_OOL_MASKABLE_HV(name, start, size) \
588 __EXC_REAL_OOL(name, start, size)
590 #define __TRAMP_REAL_OOL_MASKABLE_HV(name, vec, bitmask) \
591 TRAMP_REAL_BEGIN(tramp_real_##name); \
592 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, vec, bitmask ; \
593 EXCEPTION_PROLOG_2_REAL name##_common, EXC_HV, 1
595 #define EXC_REAL_OOL_MASKABLE_HV(name, start, size, bitmask) \
596 __EXC_REAL_OOL_MASKABLE_HV(name, start, size); \
597 __TRAMP_REAL_OOL_MASKABLE_HV(name, start, bitmask)
599 #define __EXC_VIRT_OOL(name, start, size) \
600 EXC_VIRT_BEGIN(name, start, size); \
602 EXCEPTION_PROLOG_0 PACA_EXGEN ; \
603 b tramp_virt_##name; \
604 EXC_VIRT_END(name, start, size)
606 #define __TRAMP_VIRT_OOL(name, realvec) \
607 TRAMP_VIRT_BEGIN(tramp_virt_##name); \
608 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, vec, 0 ; \
609 EXCEPTION_PROLOG_2_VIRT name##_common, EXC_STD
611 #define EXC_VIRT_OOL(name, start, size, realvec) \
612 __EXC_VIRT_OOL(name, start, size); \
613 __TRAMP_VIRT_OOL(name, realvec)
615 #define __EXC_VIRT_OOL_MASKABLE(name, start, size) \
616 __EXC_VIRT_OOL(name, start, size)
618 #define __TRAMP_VIRT_OOL_MASKABLE(name, realvec, bitmask) \
619 TRAMP_VIRT_BEGIN(tramp_virt_##name); \
620 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, realvec, bitmask ; \
621 EXCEPTION_PROLOG_2_REAL name##_common, EXC_STD, 1
623 #define EXC_VIRT_OOL_MASKABLE(name, start, size, realvec, bitmask) \
624 __EXC_VIRT_OOL_MASKABLE(name, start, size); \
625 __TRAMP_VIRT_OOL_MASKABLE(name, realvec, bitmask)
627 #define __EXC_VIRT_OOL_HV(name, start, size) \
628 __EXC_VIRT_OOL(name, start, size)
630 #define __TRAMP_VIRT_OOL_HV(name, realvec) \
631 TRAMP_VIRT_BEGIN(tramp_virt_##name); \
632 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, 0 ; \
633 EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV
635 #define EXC_VIRT_OOL_HV(name, start, size, realvec) \
636 __EXC_VIRT_OOL_HV(name, start, size); \
637 __TRAMP_VIRT_OOL_HV(name, realvec)
639 #define __EXC_VIRT_OOL_MASKABLE_HV(name, start, size) \
640 __EXC_VIRT_OOL(name, start, size)
642 #define __TRAMP_VIRT_OOL_MASKABLE_HV(name, realvec, bitmask) \
643 TRAMP_VIRT_BEGIN(tramp_virt_##name); \
644 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, realvec, bitmask ; \
645 EXCEPTION_PROLOG_2_VIRT name##_common, EXC_HV
647 #define EXC_VIRT_OOL_MASKABLE_HV(name, start, size, realvec, bitmask) \
648 __EXC_VIRT_OOL_MASKABLE_HV(name, start, size); \
649 __TRAMP_VIRT_OOL_MASKABLE_HV(name, realvec, bitmask)
651 #define TRAMP_KVM(area, n) \
652 TRAMP_KVM_BEGIN(do_kvm_##n); \
653 KVM_HANDLER area, EXC_STD, n, 0
655 #define TRAMP_KVM_SKIP(area, n) \
656 TRAMP_KVM_BEGIN(do_kvm_##n); \
657 KVM_HANDLER area, EXC_STD, n, 1
659 #define TRAMP_KVM_HV(area, n) \
660 TRAMP_KVM_BEGIN(do_kvm_H##n); \
661 KVM_HANDLER area, EXC_HV, n, 0
663 #define TRAMP_KVM_HV_SKIP(area, n) \
664 TRAMP_KVM_BEGIN(do_kvm_H##n); \
665 KVM_HANDLER area, EXC_HV, n, 1
667 #define EXC_COMMON(name, realvec, hdlr) \
668 EXC_COMMON_BEGIN(name); \
669 EXCEPTION_COMMON(PACA_EXGEN, realvec); \
671 RECONCILE_IRQ_STATE(r10, r11); \
672 addi r3,r1,STACK_FRAME_OVERHEAD; \
677 * Like EXC_COMMON, but for exceptions that can occur in the idle task and
678 * therefore need the special idle handling (finish nap and runlatch)
680 #define EXC_COMMON_ASYNC(name, realvec, hdlr) \
681 EXC_COMMON_BEGIN(name); \
682 EXCEPTION_COMMON(PACA_EXGEN, realvec); \
684 RECONCILE_IRQ_STATE(r10, r11); \
686 addi r3,r1,STACK_FRAME_OVERHEAD; \
688 b ret_from_except_lite
692 * There are a few constraints to be concerned with.
693 * - Real mode exceptions code/data must be located at their physical location.
694 * - Virtual mode exceptions must be mapped at their 0xc000... location.
695 * - Fixed location code must not call directly beyond the __end_interrupts
696 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
698 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
700 * - Conditional branch targets must be within +/-32K of caller.
702 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
703 * therefore don't have to run in physically located code or rfid to
704 * virtual mode kernel code. However on relocatable kernels they do have
705 * to branch to KERNELBASE offset because the rest of the kernel (outside
706 * the exception vectors) may be located elsewhere.
708 * Virtual exceptions correspond with physical, except their entry points
709 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
710 * offset applied. Virtual exceptions are enabled with the Alternate
711 * Interrupt Location (AIL) bit set in the LPCR. However this does not
712 * guarantee they will be delivered virtually. Some conditions (see the ISA)
713 * cause exceptions to be delivered in real mode.
715 * It's impossible to receive interrupts below 0x300 via AIL.
717 * KVM: None of the virtual exceptions are from the guest. Anything that
718 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
721 * We layout physical memory as follows:
722 * 0x0000 - 0x00ff : Secondary processor spin code
723 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
724 * 0x1900 - 0x3fff : Real mode trampolines
725 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
726 * 0x5900 - 0x6fff : Relon mode trampolines
727 * 0x7000 - 0x7fff : FWNMI data area
728 * 0x8000 - .... : Common interrupt handlers, remaining early
729 * setup code, rest of kernel.
731 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
732 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
735 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
736 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000)
737 OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900)
738 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
740 #ifdef CONFIG_PPC_POWERNV
741 .globl start_real_trampolines
742 .globl end_real_trampolines
743 .globl start_virt_trampolines
744 .globl end_virt_trampolines
747 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
749 * Data area reserved for FWNMI option.
750 * This address (0x7000) is fixed by the RPA.
751 * pseries and powernv need to keep the whole page from
752 * 0x7000 to 0x8000 free for use by the firmware
754 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
755 OPEN_TEXT_SECTION(0x8000)
757 OPEN_TEXT_SECTION(0x7000)
760 USE_FIXED_SECTION(real_vectors)
763 * This is the start of the interrupt handlers for pSeries
764 * This code runs with relocation off.
765 * Code from here to __end_interrupts gets copied down to real
766 * address 0x100 when we are running a relocatable kernel.
767 * Therefore any relative branches in this section must only
768 * branch to labels in this section.
770 .globl __start_interrupts
773 /* No virt vectors corresponding with 0x0..0x100 */
774 EXC_VIRT_NONE(0x4000, 0x100)
777 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
779 EXCEPTION_PROLOG_0 PACA_EXNMI
781 /* This is EXCEPTION_PROLOG_1 with the idle feature section added */
782 OPT_SAVE_REG_TO_PACA(PACA_EXNMI+EX_PPR, r9, CPU_FTR_HAS_PPR)
783 OPT_SAVE_REG_TO_PACA(PACA_EXNMI+EX_CFAR, r10, CPU_FTR_CFAR)
785 SAVE_CTR(r10, PACA_EXNMI)
788 #ifdef CONFIG_PPC_P7_NAP
790 * If running native on arch 2.06 or later, check if we are waking up
791 * from nap/sleep/winkle, and branch to idle handler. This tests SRR1
792 * bits 46:47. A non-0 value indicates that we are coming from a power
793 * saving state. The idle wakeup handler initially runs in real mode,
794 * but we branch to the 0xc000... address so we can turn on relocation
799 rlwinm. r10,r10,47-31,30,31
803 bltlr cr1 /* no state loss, return to idle caller */
804 BRANCH_TO_C000(r10, system_reset_idle_common)
806 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
809 KVMTEST EXC_STD 0x100
810 std r11,PACA_EXNMI+EX_R11(r13)
811 std r12,PACA_EXNMI+EX_R12(r13)
813 std r10,PACA_EXNMI+EX_R13(r13)
815 EXCEPTION_PROLOG_2_REAL system_reset_common, EXC_STD, 0
817 * MSR_RI is not enabled, because PACA_EXNMI and nmi stack is
818 * being used, so a nested NMI exception would corrupt it.
821 EXC_REAL_END(system_reset, 0x100, 0x100)
822 EXC_VIRT_NONE(0x4100, 0x100)
823 TRAMP_KVM(PACA_EXNMI, 0x100)
825 #ifdef CONFIG_PPC_P7_NAP
826 EXC_COMMON_BEGIN(system_reset_idle_common)
828 * This must be a direct branch (without linker branch stub) because
829 * we can not use TOC at this point as r2 may not be restored yet.
831 b idle_return_gpr_loss
834 EXC_COMMON_BEGIN(system_reset_common)
836 * Increment paca->in_nmi then enable MSR_RI. SLB or MCE will be able
837 * to recover, but nested NMI will notice in_nmi and not recover
838 * because of the use of the NMI stack. in_nmi reentrancy is tested in
839 * system_reset_exception.
841 lhz r10,PACA_IN_NMI(r13)
843 sth r10,PACA_IN_NMI(r13)
848 ld r1,PACA_NMI_EMERG_SP(r13)
849 subi r1,r1,INT_FRAME_SIZE
850 EXCEPTION_COMMON_STACK(PACA_EXNMI, 0x100)
853 * Set IRQS_ALL_DISABLED unconditionally so arch_irqs_disabled does
854 * the right thing. We do not want to reconcile because that goes
855 * through irq tracing which we don't want in NMI.
857 * Save PACAIRQHAPPENED because some code will do a hard disable
858 * (e.g., xmon). So we want to restore this back to where it was
859 * when we return. DAR is unused in the stack, so save it there.
861 li r10,IRQS_ALL_DISABLED
862 stb r10,PACAIRQSOFTMASK(r13)
863 lbz r10,PACAIRQHAPPENED(r13)
866 addi r3,r1,STACK_FRAME_OVERHEAD
867 bl system_reset_exception
869 /* This (and MCE) can be simplified with mtmsrd L=1 */
870 /* Clear MSR_RI before setting SRR0 and SRR1. */
877 * MSR_RI is clear, now we can decrement paca->in_nmi.
879 lhz r10,PACA_IN_NMI(r13)
881 sth r10,PACA_IN_NMI(r13)
884 * Restore soft mask settings.
887 stb r10,PACAIRQHAPPENED(r13)
889 stb r10,PACAIRQSOFTMASK(r13)
892 * Keep below code in synch with MACHINE_CHECK_HANDLER_WINDUP.
893 * Should share common bits...
896 /* Move original SRR0 and SRR1 into the respective regs */
914 /* restore original r1. */
916 RFI_TO_USER_OR_KERNEL
918 #ifdef CONFIG_PPC_PSERIES
920 * Vectors for the FWNMI option. Share common code.
922 TRAMP_REAL_BEGIN(system_reset_fwnmi)
923 SET_SCRATCH0(r13) /* save r13 */
924 /* See comment at system_reset exception, don't turn on RI */
925 EXCEPTION_PROLOG_0 PACA_EXNMI
926 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXNMI, 0, 0x100, 0
927 EXCEPTION_PROLOG_2_REAL system_reset_common, EXC_STD, 0
929 #endif /* CONFIG_PPC_PSERIES */
932 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
933 /* This is moved out of line as it can be patched by FW, but
934 * some code path might still want to branch into the original
937 SET_SCRATCH0(r13) /* save r13 */
938 EXCEPTION_PROLOG_0 PACA_EXMC
940 b machine_check_common_early
942 b machine_check_pSeries_0
943 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
944 EXC_REAL_END(machine_check, 0x200, 0x100)
945 EXC_VIRT_NONE(0x4200, 0x100)
946 TRAMP_REAL_BEGIN(machine_check_common_early)
947 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 0, 0x200, 0
952 * Original R9 to R13 is saved on PACA_EXMC
954 * Switch to mc_emergency stack and handle re-entrancy (we limit
955 * the nested MCE upto level 4 to avoid stack overflow).
956 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
958 * We use paca->in_mce to check whether this is the first entry or
959 * nested machine check. We increment paca->in_mce to track nested
962 * If this is the first entry then set stack pointer to
963 * paca->mc_emergency_sp, otherwise r1 is already pointing to
964 * stack frame on mc_emergency stack.
966 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
967 * checkstop if we get another machine check exception before we do
968 * rfid with MSR_ME=1.
970 * This interrupt can wake directly from idle. If that is the case,
971 * the machine check is handled then the idle wakeup code is called
974 mr r11,r1 /* Save r1 */
975 lhz r10,PACA_IN_MCE(r13)
976 cmpwi r10,0 /* Are we in nested machine check */
977 bne 0f /* Yes, we are. */
978 /* First machine check entry */
979 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
980 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
981 addi r10,r10,1 /* increment paca->in_mce */
982 sth r10,PACA_IN_MCE(r13)
983 /* Limit nested MCE to level 4 to avoid stack overflow */
984 cmpwi r10,MAX_MCE_DEPTH
985 bgt 2f /* Check if we hit limit of 4 */
986 std r11,GPR1(r1) /* Save r1 on the stack. */
987 std r11,0(r1) /* make stack chain pointer */
988 mfspr r11,SPRN_SRR0 /* Save SRR0 */
990 mfspr r11,SPRN_SRR1 /* Save SRR1 */
992 mfspr r11,SPRN_DAR /* Save DAR */
994 mfspr r11,SPRN_DSISR /* Save DSISR */
996 std r9,_CCR(r1) /* Save CR in stackframe */
997 /* We don't touch AMR here, we never go to virtual mode */
998 /* Save r9 through r13 from EXMC save area to stack frame. */
999 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
1000 mfmsr r11 /* get MSR value */
1002 ori r11,r11,MSR_ME /* turn on ME bit */
1003 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1004 ori r11,r11,MSR_RI /* turn on RI bit */
1005 LOAD_HANDLER(r12, machine_check_handle_early)
1006 1: mtspr SPRN_SRR0,r12
1009 b . /* prevent speculative execution */
1011 /* Stack overflow. Stay on emergency stack and panic.
1012 * Keep the ME bit off while panic-ing, so that if we hit
1013 * another machine check we checkstop.
1015 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
1016 ld r11,PACAKMSR(r13)
1017 LOAD_HANDLER(r12, unrecover_mce)
1019 andc r11,r11,r10 /* Turn off MSR_ME */
1021 b . /* prevent speculative execution */
1023 TRAMP_REAL_BEGIN(machine_check_pSeries)
1024 .globl machine_check_fwnmi
1025 machine_check_fwnmi:
1026 SET_SCRATCH0(r13) /* save r13 */
1027 EXCEPTION_PROLOG_0 PACA_EXMC
1029 b machine_check_common_early
1030 END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
1031 machine_check_pSeries_0:
1032 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXMC, 1, 0x200, 0
1034 * MSR_RI is not enabled, because PACA_EXMC is being used, so a
1035 * nested machine check corrupts it. machine_check_common enables
1038 EXCEPTION_PROLOG_2_REAL machine_check_common, EXC_STD, 0
1040 TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
1042 EXC_COMMON_BEGIN(machine_check_common)
1044 * Machine check is different because we use a different
1045 * save area: PACA_EXMC instead of PACA_EXGEN.
1048 std r10,PACA_EXMC+EX_DAR(r13)
1049 mfspr r10,SPRN_DSISR
1050 stw r10,PACA_EXMC+EX_DSISR(r13)
1051 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
1053 RECONCILE_IRQ_STATE(r10, r11)
1054 ld r3,PACA_EXMC+EX_DAR(r13)
1055 lwz r4,PACA_EXMC+EX_DSISR(r13)
1056 /* Enable MSR_RI when finished with PACA_EXMC */
1062 addi r3,r1,STACK_FRAME_OVERHEAD
1063 bl machine_check_exception
1066 #define MACHINE_CHECK_HANDLER_WINDUP \
1067 /* Clear MSR_RI before setting SRR0 and SRR1. */\
1069 mfmsr r9; /* get MSR value */ \
1071 mtmsrd r9,1; /* Clear MSR_RI */ \
1072 /* Move original SRR0 and SRR1 into the respective regs */ \
1074 mtspr SPRN_SRR1,r9; \
1076 mtspr SPRN_SRR0,r3; \
1084 REST_8GPRS(2, r1); \
1088 /* Decrement paca->in_mce. */ \
1089 lhz r12,PACA_IN_MCE(r13); \
1091 sth r12,PACA_IN_MCE(r13); \
1093 REST_2GPRS(12, r1); \
1094 /* restore original r1. */ \
1097 #ifdef CONFIG_PPC_P7_NAP
1099 * This is an idle wakeup. Low level machine check has already been
1100 * done. Queue the event then call the idle code to do the wake up.
1102 EXC_COMMON_BEGIN(machine_check_idle_common)
1103 bl machine_check_queue_event
1106 * We have not used any non-volatile GPRs here, and as a rule
1107 * most exception code including machine check does not.
1108 * Therefore PACA_NAPSTATELOST does not need to be set. Idle
1109 * wakeup will restore volatile registers.
1111 * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
1113 * Then decrement MCE nesting after finishing with the stack.
1118 lhz r11,PACA_IN_MCE(r13)
1120 sth r11,PACA_IN_MCE(r13)
1123 rlwinm r10,r3,47-31,30,31
1125 bltlr cr1 /* no state loss, return to idle caller */
1126 b idle_return_gpr_loss
1129 * Handle machine check early in real mode. We come here with
1130 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
1132 EXC_COMMON_BEGIN(machine_check_handle_early)
1133 std r0,GPR0(r1) /* Save r0 */
1134 EXCEPTION_PROLOG_COMMON_3(0x200)
1136 addi r3,r1,STACK_FRAME_OVERHEAD
1137 bl machine_check_early
1138 std r3,RESULT(r1) /* Save result */
1142 END_FTR_SECTION_IFCLR(CPU_FTR_HVMODE)
1144 #ifdef CONFIG_PPC_P7_NAP
1146 * Check if thread was in power saving mode. We come here when any
1147 * of the following is true:
1148 * a. thread wasn't in power saving mode
1149 * b. thread was in power saving mode with no state loss,
1150 * supervisor state loss or hypervisor state loss.
1152 * Go back to nap/sleep/winkle mode again if (b) is true.
1155 rlwinm. r11,r12,47-31,30,31
1156 bne machine_check_idle_common
1157 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
1161 * Check if we are coming from hypervisor userspace. If yes then we
1162 * continue in host kernel in V mode to deliver the MC event.
1164 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */
1166 4: andi. r11,r12,MSR_PR /* See if coming from user. */
1167 bne 9f /* continue in V mode if we are. */
1170 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1173 * We are coming from kernel context. Check if we are coming from
1174 * guest. if yes, then we can continue. We will fall through
1175 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
1177 lbz r11,HSTATE_IN_GUEST(r13)
1178 cmpwi r11,0 /* Check if coming from guest */
1179 bne 9f /* continue if we are. */
1180 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1183 * At this point we are not sure about what context we come from.
1184 * Queue up the MCE event and return from the interrupt.
1185 * But before that, check if this is an un-recoverable exception.
1186 * If yes, then stay on emergency stack and panic.
1188 andi. r11,r12,MSR_RI
1190 1: mfspr r11,SPRN_SRR0
1191 LOAD_HANDLER(r10,unrecover_mce)
1193 ld r10,PACAKMSR(r13)
1195 * We are going down. But there are chances that we might get hit by
1196 * another MCE during panic path and we may run into unstable state
1197 * with no way out. Hence, turn ME bit off while going down, so that
1198 * when another MCE is hit during panic path, system will checkstop
1199 * and hypervisor will get restarted cleanly by SP.
1202 andc r10,r10,r3 /* Turn off MSR_ME */
1208 * Check if we have successfully handled/recovered from error, if not
1209 * then stay on emergency stack and panic.
1211 ld r3,RESULT(r1) /* Load result */
1212 cmpdi r3,0 /* see if we handled MCE successfully */
1214 beq 1b /* if !handled then panic */
1217 * Return from MC interrupt.
1218 * Queue up the MCE event so that we can log it later, while
1219 * returning from kernel or opal call.
1221 bl machine_check_queue_event
1222 MACHINE_CHECK_HANDLER_WINDUP
1223 RFI_TO_USER_OR_KERNEL
1226 * pSeries: Return from MC interrupt. Before that stay on emergency
1227 * stack and call machine_check_exception to log the MCE event.
1229 LOAD_HANDLER(r10,mce_return)
1231 ld r10,PACAKMSR(r13)
1235 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1237 /* Deliver the machine check to host kernel in V mode. */
1238 MACHINE_CHECK_HANDLER_WINDUP
1239 SET_SCRATCH0(r13) /* save r13 */
1240 EXCEPTION_PROLOG_0 PACA_EXMC
1241 b machine_check_pSeries_0
1243 EXC_COMMON_BEGIN(unrecover_mce)
1244 /* Invoke machine_check_exception to print MCE event and panic. */
1245 addi r3,r1,STACK_FRAME_OVERHEAD
1246 bl machine_check_exception
1248 * We will not reach here. Even if we did, there is no way out. Call
1249 * unrecoverable_exception and die.
1251 1: addi r3,r1,STACK_FRAME_OVERHEAD
1252 bl unrecoverable_exception
1255 EXC_COMMON_BEGIN(mce_return)
1256 /* Invoke machine_check_exception to print MCE event and return. */
1257 addi r3,r1,STACK_FRAME_OVERHEAD
1258 bl machine_check_exception
1259 MACHINE_CHECK_HANDLER_WINDUP
1263 EXC_REAL_BEGIN(data_access, 0x300, 0x80)
1264 SET_SCRATCH0(r13) /* save r13 */
1265 EXCEPTION_PROLOG_0 PACA_EXGEN
1266 b tramp_real_data_access
1267 EXC_REAL_END(data_access, 0x300, 0x80)
1269 TRAMP_REAL_BEGIN(tramp_real_data_access)
1270 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x300, 0
1272 * DAR/DSISR must be read before setting MSR[RI], because
1273 * a d-side MCE will clobber those registers so is not
1274 * recoverable if they are live.
1277 mfspr r11,SPRN_DSISR
1278 std r10,PACA_EXGEN+EX_DAR(r13)
1279 stw r11,PACA_EXGEN+EX_DSISR(r13)
1280 EXCEPTION_PROLOG_2_REAL data_access_common, EXC_STD, 1
1282 EXC_VIRT_BEGIN(data_access, 0x4300, 0x80)
1283 SET_SCRATCH0(r13) /* save r13 */
1284 EXCEPTION_PROLOG_0 PACA_EXGEN
1285 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x300, 0
1287 mfspr r11,SPRN_DSISR
1288 std r10,PACA_EXGEN+EX_DAR(r13)
1289 stw r11,PACA_EXGEN+EX_DSISR(r13)
1290 EXCEPTION_PROLOG_2_VIRT data_access_common, EXC_STD
1291 EXC_VIRT_END(data_access, 0x4300, 0x80)
1293 TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
1295 EXC_COMMON_BEGIN(data_access_common)
1297 * Here r13 points to the paca, r9 contains the saved CR,
1298 * SRR0 and SRR1 are saved in r11 and r12,
1299 * r9 - r13 are saved in paca->exgen.
1300 * EX_DAR and EX_DSISR have saved DAR/DSISR
1302 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
1303 RECONCILE_IRQ_STATE(r10, r11)
1305 ld r3,PACA_EXGEN+EX_DAR(r13)
1306 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1310 BEGIN_MMU_FTR_SECTION
1311 b do_hash_page /* Try to handle as hpte fault */
1312 MMU_FTR_SECTION_ELSE
1314 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1317 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
1318 SET_SCRATCH0(r13) /* save r13 */
1319 EXCEPTION_PROLOG_0 PACA_EXSLB
1320 b tramp_real_data_access_slb
1321 EXC_REAL_END(data_access_slb, 0x380, 0x80)
1323 TRAMP_REAL_BEGIN(tramp_real_data_access_slb)
1324 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 1, 0x380, 0
1326 std r10,PACA_EXSLB+EX_DAR(r13)
1327 EXCEPTION_PROLOG_2_REAL data_access_slb_common, EXC_STD, 1
1329 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
1330 SET_SCRATCH0(r13) /* save r13 */
1331 EXCEPTION_PROLOG_0 PACA_EXSLB
1332 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXSLB, 0, 0x380, 0
1334 std r10,PACA_EXSLB+EX_DAR(r13)
1335 EXCEPTION_PROLOG_2_VIRT data_access_slb_common, EXC_STD
1336 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
1338 TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
1340 EXC_COMMON_BEGIN(data_access_slb_common)
1341 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
1342 ld r4,PACA_EXSLB+EX_DAR(r13)
1344 addi r3,r1,STACK_FRAME_OVERHEAD
1345 BEGIN_MMU_FTR_SECTION
1346 /* HPT case, do SLB fault */
1350 b fast_exception_return
1352 MMU_FTR_SECTION_ELSE
1353 /* Radix case, access is outside page table range */
1355 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1358 RECONCILE_IRQ_STATE(r10, r11)
1361 addi r3,r1,STACK_FRAME_OVERHEAD
1366 EXC_REAL(instruction_access, 0x400, 0x80)
1367 EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400)
1368 TRAMP_KVM(PACA_EXGEN, 0x400)
1370 EXC_COMMON_BEGIN(instruction_access_common)
1371 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
1372 RECONCILE_IRQ_STATE(r10, r11)
1375 andis. r4,r12,DSISR_SRR1_MATCH_64S@h
1379 BEGIN_MMU_FTR_SECTION
1380 b do_hash_page /* Try to handle as hpte fault */
1381 MMU_FTR_SECTION_ELSE
1383 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1386 __EXC_REAL(instruction_access_slb, 0x480, 0x80, PACA_EXSLB)
1387 __EXC_VIRT(instruction_access_slb, 0x4480, 0x80, 0x480, PACA_EXSLB)
1388 TRAMP_KVM(PACA_EXSLB, 0x480)
1390 EXC_COMMON_BEGIN(instruction_access_slb_common)
1391 EXCEPTION_PROLOG_COMMON(0x480, PACA_EXSLB)
1393 addi r3,r1,STACK_FRAME_OVERHEAD
1394 BEGIN_MMU_FTR_SECTION
1395 /* HPT case, do SLB fault */
1399 b fast_exception_return
1401 MMU_FTR_SECTION_ELSE
1402 /* Radix case, access is outside page table range */
1404 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1407 RECONCILE_IRQ_STATE(r10, r11)
1410 addi r3,r1,STACK_FRAME_OVERHEAD
1415 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
1416 SET_SCRATCH0(r13) /* save r13 */
1417 EXCEPTION_PROLOG_0 PACA_EXGEN
1419 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, IRQS_DISABLED
1420 EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_HV, 1
1422 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, IRQS_DISABLED
1423 EXCEPTION_PROLOG_2_REAL hardware_interrupt_common, EXC_STD, 1
1424 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
1425 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
1427 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
1428 SET_SCRATCH0(r13) /* save r13 */
1429 EXCEPTION_PROLOG_0 PACA_EXGEN
1431 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0x500, IRQS_DISABLED
1432 EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_HV
1434 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x500, IRQS_DISABLED
1435 EXCEPTION_PROLOG_2_VIRT hardware_interrupt_common, EXC_STD
1436 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
1437 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
1439 TRAMP_KVM(PACA_EXGEN, 0x500)
1440 TRAMP_KVM_HV(PACA_EXGEN, 0x500)
1441 EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
1444 EXC_REAL_BEGIN(alignment, 0x600, 0x100)
1445 SET_SCRATCH0(r13) /* save r13 */
1446 EXCEPTION_PROLOG_0 PACA_EXGEN
1447 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 1, 0x600, 0
1449 mfspr r11,SPRN_DSISR
1450 std r10,PACA_EXGEN+EX_DAR(r13)
1451 stw r11,PACA_EXGEN+EX_DSISR(r13)
1452 EXCEPTION_PROLOG_2_REAL alignment_common, EXC_STD, 1
1453 EXC_REAL_END(alignment, 0x600, 0x100)
1455 EXC_VIRT_BEGIN(alignment, 0x4600, 0x100)
1456 SET_SCRATCH0(r13) /* save r13 */
1457 EXCEPTION_PROLOG_0 PACA_EXGEN
1458 EXCEPTION_PROLOG_1 EXC_STD, PACA_EXGEN, 0, 0x600, 0
1460 mfspr r11,SPRN_DSISR
1461 std r10,PACA_EXGEN+EX_DAR(r13)
1462 stw r11,PACA_EXGEN+EX_DSISR(r13)
1463 EXCEPTION_PROLOG_2_VIRT alignment_common, EXC_STD
1464 EXC_VIRT_END(alignment, 0x4600, 0x100)
1466 TRAMP_KVM(PACA_EXGEN, 0x600)
1467 EXC_COMMON_BEGIN(alignment_common)
1468 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
1469 ld r3,PACA_EXGEN+EX_DAR(r13)
1470 lwz r4,PACA_EXGEN+EX_DSISR(r13)
1474 RECONCILE_IRQ_STATE(r10, r11)
1475 addi r3,r1,STACK_FRAME_OVERHEAD
1476 bl alignment_exception
1480 EXC_REAL(program_check, 0x700, 0x100)
1481 EXC_VIRT(program_check, 0x4700, 0x100, 0x700)
1482 TRAMP_KVM(PACA_EXGEN, 0x700)
1483 EXC_COMMON_BEGIN(program_check_common)
1485 * It's possible to receive a TM Bad Thing type program check with
1486 * userspace register values (in particular r1), but with SRR1 reporting
1487 * that we came from the kernel. Normally that would confuse the bad
1488 * stack logic, and we would report a bad kernel stack pointer. Instead
1489 * we switch to the emergency stack if we're taking a TM Bad Thing from
1492 li r10,MSR_PR /* Build a mask of MSR_PR .. */
1493 oris r10,r10,0x200000@h /* .. and SRR1_PROGTM */
1494 and r10,r10,r12 /* Mask SRR1 with that. */
1495 srdi r10,r10,8 /* Shift it so we can compare */
1496 cmpldi r10,(0x200000 >> 8) /* .. with an immediate. */
1497 bne 1f /* If != go to normal path. */
1499 /* SRR1 had PR=0 and SRR1_PROGTM=1, so use the emergency stack */
1500 andi. r10,r12,MSR_PR; /* Set CR0 correctly for label */
1501 /* 3 in EXCEPTION_PROLOG_COMMON */
1502 mr r10,r1 /* Save r1 */
1503 ld r1,PACAEMERGSP(r13) /* Use emergency stack */
1504 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1505 b 3f /* Jump into the macro !! */
1506 1: EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
1508 RECONCILE_IRQ_STATE(r10, r11)
1509 addi r3,r1,STACK_FRAME_OVERHEAD
1510 bl program_check_exception
1514 EXC_REAL(fp_unavailable, 0x800, 0x100)
1515 EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800)
1516 TRAMP_KVM(PACA_EXGEN, 0x800)
1517 EXC_COMMON_BEGIN(fp_unavailable_common)
1518 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
1519 bne 1f /* if from user, just load it up */
1521 RECONCILE_IRQ_STATE(r10, r11)
1522 addi r3,r1,STACK_FRAME_OVERHEAD
1523 bl kernel_fp_unavailable_exception
1526 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1528 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1529 * transaction), go do TM stuff
1531 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1533 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1536 b fast_exception_return
1537 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1538 2: /* User process was in a transaction */
1540 RECONCILE_IRQ_STATE(r10, r11)
1541 addi r3,r1,STACK_FRAME_OVERHEAD
1542 bl fp_unavailable_tm
1547 EXC_REAL_OOL_MASKABLE(decrementer, 0x900, 0x80, IRQS_DISABLED)
1548 EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900, IRQS_DISABLED)
1549 TRAMP_KVM(PACA_EXGEN, 0x900)
1550 EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
1553 EXC_REAL_HV(hdecrementer, 0x980, 0x80)
1554 EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980)
1555 TRAMP_KVM_HV(PACA_EXGEN, 0x980)
1556 EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
1559 EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100, IRQS_DISABLED)
1560 EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00, IRQS_DISABLED)
1561 TRAMP_KVM(PACA_EXGEN, 0xa00)
1562 #ifdef CONFIG_PPC_DOORBELL
1563 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
1565 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
1569 EXC_REAL(trap_0b, 0xb00, 0x100)
1570 EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00)
1571 TRAMP_KVM(PACA_EXGEN, 0xb00)
1572 EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
1575 * system call / hypercall (0xc00, 0x4c00)
1577 * The system call exception is invoked with "sc 0" and does not alter HV bit.
1578 * There is support for kernel code to invoke system calls but there are no
1581 * The hypercall is invoked with "sc 1" and sets HV=1.
1583 * In HPT, sc 1 always goes to 0xc00 real mode. In RADIX, sc 1 can go to
1584 * 0x4c00 virtual mode.
1588 * syscall register convention is in Documentation/powerpc/syscall64-abi.txt
1590 * For hypercalls, the register convention is as follows:
1593 * r3 volatile parameter and return value for status
1594 * r4-r10 volatile input and output value
1595 * r11 volatile hypercall number and output value
1596 * r12 volatile input and output value
1597 * r13-r31 nonvolatile
1601 * CR0-1 CR5-7 volatile
1603 * Other registers nonvolatile
1605 * The intersection of volatile registers that don't contain possible
1606 * inputs is: cr0, xer, ctr. We may use these as scratch regs upon entry
1607 * without saving, though xer is not a good idea to use, as hardware may
1608 * interpret some bits so it may be costly to change them.
1610 .macro SYSTEM_CALL virt
1611 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1613 * There is a little bit of juggling to get syscall and hcall
1614 * working well. Save r13 in ctr to avoid using SPRG scratch
1617 * Userspace syscalls have already saved the PPR, hcalls must save
1618 * it before setting HMT_MEDIUM.
1622 std r10,PACA_EXGEN+EX_R10(r13)
1624 KVMTEST EXC_STD 0xc00 /* uses r10, branch to do_kvm_0xc00_system_call */
1634 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
1638 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
1640 /* We reach here with PACA in r13, r13 in r9, and HMT_MEDIUM. */
1645 __LOAD_HANDLER(r10, system_call_common)
1647 ld r10,PACAKMSR(r13)
1650 b . /* prevent speculative execution */
1652 #ifdef CONFIG_RELOCATABLE
1654 * We can't branch directly so we do it via the CTR which
1655 * is volatile across system calls.
1657 __LOAD_HANDLER(r10, system_call_common)
1665 /* We can branch directly */
1669 mtmsrd r10,1 /* Set RI (EE=0) */
1670 b system_call_common
1674 #ifdef CONFIG_PPC_FAST_ENDIAN_SWITCH
1675 /* Fast LE/BE switch system call */
1676 1: mfspr r12,SPRN_SRR1
1680 RFI_TO_USER /* return to userspace */
1681 b . /* prevent speculative execution */
1685 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
1687 EXC_REAL_END(system_call, 0xc00, 0x100)
1689 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
1691 EXC_VIRT_END(system_call, 0x4c00, 0x100)
1693 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1695 * This is a hcall, so register convention is as above, with these
1699 * orig r10 saved in PACA
1701 TRAMP_KVM_BEGIN(do_kvm_0xc00)
1703 * Save the PPR (on systems that support it) before changing to
1704 * HMT_MEDIUM. That allows the KVM code to save that value into the
1705 * guest state (it is the guest's PPR value).
1707 OPT_GET_SPR(r10, SPRN_PPR, CPU_FTR_HAS_PPR)
1709 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r10, CPU_FTR_HAS_PPR)
1712 std r9,PACA_EXGEN+EX_R9(r13)
1714 KVM_HANDLER PACA_EXGEN, EXC_STD, 0xc00, 0
1718 EXC_REAL(single_step, 0xd00, 0x100)
1719 EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00)
1720 TRAMP_KVM(PACA_EXGEN, 0xd00)
1721 EXC_COMMON(single_step_common, 0xd00, single_step_exception)
1723 EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20)
1724 EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00)
1725 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
1726 EXC_COMMON_BEGIN(h_data_storage_common)
1728 std r10,PACA_EXGEN+EX_DAR(r13)
1729 mfspr r10,SPRN_HDSISR
1730 stw r10,PACA_EXGEN+EX_DSISR(r13)
1731 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
1733 RECONCILE_IRQ_STATE(r10, r11)
1734 addi r3,r1,STACK_FRAME_OVERHEAD
1735 BEGIN_MMU_FTR_SECTION
1736 ld r4,PACA_EXGEN+EX_DAR(r13)
1737 lwz r5,PACA_EXGEN+EX_DSISR(r13)
1742 MMU_FTR_SECTION_ELSE
1743 bl unknown_exception
1744 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX)
1748 EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20)
1749 EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20)
1750 TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
1751 EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
1754 EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20)
1755 EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40)
1756 TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
1757 EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
1761 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early
1762 * first, and then eventaully from there to the trampoline to get into virtual
1765 __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early)
1766 __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60, IRQS_DISABLED)
1767 EXC_VIRT_NONE(0x4e60, 0x20)
1768 TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
1769 TRAMP_REAL_BEGIN(hmi_exception_early)
1770 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 1, 0xe60, 0
1771 mr r10,r1 /* Save r1 */
1772 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
1773 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
1774 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */
1775 mfspr r12,SPRN_HSRR1 /* Save HSRR1 */
1776 EXCEPTION_PROLOG_COMMON_1()
1777 /* We don't touch AMR here, we never go to virtual mode */
1778 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
1779 EXCEPTION_PROLOG_COMMON_3(0xe60)
1780 addi r3,r1,STACK_FRAME_OVERHEAD
1781 BRANCH_LINK_TO_FAR(DOTSYM(hmi_exception_realmode)) /* Function call ABI */
1784 /* Windup the stack. */
1785 /* Move original HSRR0 and HSRR1 into the respective regs */
1805 HRFI_TO_USER_OR_KERNEL
1812 * Go to virtual mode and pull the HMI event information from
1815 .globl hmi_exception_after_realmode
1816 hmi_exception_after_realmode:
1818 EXCEPTION_PROLOG_0 PACA_EXGEN
1819 b tramp_real_hmi_exception
1821 EXC_COMMON_BEGIN(hmi_exception_common)
1822 EXCEPTION_COMMON(PACA_EXGEN, 0xe60)
1825 RECONCILE_IRQ_STATE(r10, r11)
1827 addi r3,r1,STACK_FRAME_OVERHEAD
1828 bl handle_hmi_exception
1831 EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20, IRQS_DISABLED)
1832 EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80, IRQS_DISABLED)
1833 TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
1834 #ifdef CONFIG_PPC_DOORBELL
1835 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
1837 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
1841 EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20, IRQS_DISABLED)
1842 EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0, IRQS_DISABLED)
1843 TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
1844 EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
1847 EXC_REAL_NONE(0xec0, 0x20)
1848 EXC_VIRT_NONE(0x4ec0, 0x20)
1849 EXC_REAL_NONE(0xee0, 0x20)
1850 EXC_VIRT_NONE(0x4ee0, 0x20)
1853 EXC_REAL_OOL_MASKABLE(performance_monitor, 0xf00, 0x20, IRQS_PMI_DISABLED)
1854 EXC_VIRT_OOL_MASKABLE(performance_monitor, 0x4f00, 0x20, 0xf00, IRQS_PMI_DISABLED)
1855 TRAMP_KVM(PACA_EXGEN, 0xf00)
1856 EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1859 EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20)
1860 EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20)
1861 TRAMP_KVM(PACA_EXGEN, 0xf20)
1862 EXC_COMMON_BEGIN(altivec_unavailable_common)
1863 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1864 #ifdef CONFIG_ALTIVEC
1867 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1868 BEGIN_FTR_SECTION_NESTED(69)
1869 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1870 * transaction), go do TM stuff
1872 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1874 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1877 b fast_exception_return
1878 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1879 2: /* User process was in a transaction */
1881 RECONCILE_IRQ_STATE(r10, r11)
1882 addi r3,r1,STACK_FRAME_OVERHEAD
1883 bl altivec_unavailable_tm
1887 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1890 RECONCILE_IRQ_STATE(r10, r11)
1891 addi r3,r1,STACK_FRAME_OVERHEAD
1892 bl altivec_unavailable_exception
1896 EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20)
1897 EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40)
1898 TRAMP_KVM(PACA_EXGEN, 0xf40)
1899 EXC_COMMON_BEGIN(vsx_unavailable_common)
1900 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
1904 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1905 BEGIN_FTR_SECTION_NESTED(69)
1906 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1907 * transaction), go do TM stuff
1909 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1911 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1914 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1915 2: /* User process was in a transaction */
1917 RECONCILE_IRQ_STATE(r10, r11)
1918 addi r3,r1,STACK_FRAME_OVERHEAD
1919 bl vsx_unavailable_tm
1923 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1926 RECONCILE_IRQ_STATE(r10, r11)
1927 addi r3,r1,STACK_FRAME_OVERHEAD
1928 bl vsx_unavailable_exception
1932 EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20)
1933 EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60)
1934 TRAMP_KVM(PACA_EXGEN, 0xf60)
1935 EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1938 EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20)
1939 EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80)
1940 TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
1941 EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1944 EXC_REAL_NONE(0xfa0, 0x20)
1945 EXC_VIRT_NONE(0x4fa0, 0x20)
1946 EXC_REAL_NONE(0xfc0, 0x20)
1947 EXC_VIRT_NONE(0x4fc0, 0x20)
1948 EXC_REAL_NONE(0xfe0, 0x20)
1949 EXC_VIRT_NONE(0x4fe0, 0x20)
1951 EXC_REAL_NONE(0x1000, 0x100)
1952 EXC_VIRT_NONE(0x5000, 0x100)
1953 EXC_REAL_NONE(0x1100, 0x100)
1954 EXC_VIRT_NONE(0x5100, 0x100)
1956 #ifdef CONFIG_CBE_RAS
1957 EXC_REAL_HV(cbe_system_error, 0x1200, 0x100)
1958 EXC_VIRT_NONE(0x5200, 0x100)
1959 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
1960 EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1961 #else /* CONFIG_CBE_RAS */
1962 EXC_REAL_NONE(0x1200, 0x100)
1963 EXC_VIRT_NONE(0x5200, 0x100)
1967 EXC_REAL(instruction_breakpoint, 0x1300, 0x100)
1968 EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300)
1969 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
1970 EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1972 EXC_REAL_NONE(0x1400, 0x100)
1973 EXC_VIRT_NONE(0x5400, 0x100)
1975 EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
1976 mtspr SPRN_SPRG_HSCRATCH0,r13
1977 EXCEPTION_PROLOG_0 PACA_EXGEN
1978 EXCEPTION_PROLOG_1 EXC_HV, PACA_EXGEN, 0, 0x1500, 0
1980 #ifdef CONFIG_PPC_DENORMALISATION
1981 mfspr r10,SPRN_HSRR1
1982 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */
1986 KVMTEST EXC_HV 0x1500
1987 EXCEPTION_PROLOG_2_REAL denorm_common, EXC_HV, 1
1988 EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
1990 #ifdef CONFIG_PPC_DENORMALISATION
1991 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
1992 b exc_real_0x1500_denorm_exception_hv
1993 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
1995 EXC_VIRT_NONE(0x5500, 0x100)
1998 TRAMP_KVM_HV(PACA_EXGEN, 0x1500)
2000 #ifdef CONFIG_PPC_DENORMALISATION
2001 TRAMP_REAL_BEGIN(denorm_assist)
2004 * To denormalise we need to move a copy of the register to itself.
2005 * For POWER6 do that here for all FP regs.
2008 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
2009 xori r10,r10,(MSR_FE0|MSR_FE1)
2021 * To denormalise we need to move a copy of the register to itself.
2022 * For POWER7 do that here for the first 32 VSX registers only.
2025 oris r10,r10,MSR_VSX@h
2031 XVCPSGNDP(.Lreg,.Lreg,.Lreg)
2035 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
2039 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
2041 * To denormalise we need to move a copy of the register to itself.
2042 * For POWER8 we need to do that for all 64 VSX registers
2046 XVCPSGNDP(.Lreg,.Lreg,.Lreg)
2051 mfspr r11,SPRN_HSRR0
2053 mtspr SPRN_HSRR0,r11
2055 ld r9,PACA_EXGEN+EX_R9(r13)
2056 RESTORE_PPR_PACA(PACA_EXGEN, r10)
2058 ld r10,PACA_EXGEN+EX_CFAR(r13)
2060 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
2061 ld r10,PACA_EXGEN+EX_R10(r13)
2062 ld r11,PACA_EXGEN+EX_R11(r13)
2063 ld r12,PACA_EXGEN+EX_R12(r13)
2064 ld r13,PACA_EXGEN+EX_R13(r13)
2069 EXC_COMMON(denorm_common, 0x1500, unknown_exception)
2072 #ifdef CONFIG_CBE_RAS
2073 EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100)
2074 EXC_VIRT_NONE(0x5600, 0x100)
2075 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
2076 EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
2077 #else /* CONFIG_CBE_RAS */
2078 EXC_REAL_NONE(0x1600, 0x100)
2079 EXC_VIRT_NONE(0x5600, 0x100)
2083 EXC_REAL(altivec_assist, 0x1700, 0x100)
2084 EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700)
2085 TRAMP_KVM(PACA_EXGEN, 0x1700)
2086 #ifdef CONFIG_ALTIVEC
2087 EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
2089 EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
2093 #ifdef CONFIG_CBE_RAS
2094 EXC_REAL_HV(cbe_thermal, 0x1800, 0x100)
2095 EXC_VIRT_NONE(0x5800, 0x100)
2096 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
2097 EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
2098 #else /* CONFIG_CBE_RAS */
2099 EXC_REAL_NONE(0x1800, 0x100)
2100 EXC_VIRT_NONE(0x5800, 0x100)
2103 #ifdef CONFIG_PPC_WATCHDOG
2105 #define MASKED_DEC_HANDLER_LABEL 3f
2107 #define MASKED_DEC_HANDLER(_H) \
2109 std r12,PACA_EXGEN+EX_R12(r13); \
2110 GET_SCRATCH0(r10); \
2111 std r10,PACA_EXGEN+EX_R13(r13); \
2112 EXCEPTION_PROLOG_2_REAL soft_nmi_common, _H, 1
2115 * Branch to soft_nmi_interrupt using the emergency stack. The emergency
2116 * stack is one that is usable by maskable interrupts so long as MSR_EE
2117 * remains off. It is used for recovery when something has corrupted the
2118 * normal kernel stack, for example. The "soft NMI" must not use the process
2119 * stack because we want irq disabled sections to avoid touching the stack
2120 * at all (other than PMU interrupts), so use the emergency stack for this,
2121 * and run it entirely with interrupts hard disabled.
2123 EXC_COMMON_BEGIN(soft_nmi_common)
2125 ld r1,PACAEMERGSP(r13)
2126 subi r1,r1,INT_FRAME_SIZE
2127 EXCEPTION_COMMON_STACK(PACA_EXGEN, 0x900)
2129 RECONCILE_IRQ_STATE(r10, r11)
2130 addi r3,r1,STACK_FRAME_OVERHEAD
2131 bl soft_nmi_interrupt
2134 #else /* CONFIG_PPC_WATCHDOG */
2135 #define MASKED_DEC_HANDLER_LABEL 2f /* normal return */
2136 #define MASKED_DEC_HANDLER(_H)
2137 #endif /* CONFIG_PPC_WATCHDOG */
2140 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
2141 * - If it was a decrementer interrupt, we bump the dec to max and and return.
2142 * - If it was a doorbell we return immediately since doorbells are edge
2143 * triggered and won't automatically refire.
2144 * - If it was a HMI we return immediately since we handled it in realmode
2145 * and it won't refire.
2146 * - Else it is one of PACA_IRQ_MUST_HARD_MASK, so hard disable and return.
2147 * This is called with r10 containing the value to OR to the paca field.
2149 .macro MASKED_INTERRUPT hsrr
2155 std r11,PACA_EXGEN+EX_R11(r13)
2156 lbz r11,PACAIRQHAPPENED(r13)
2158 stb r11,PACAIRQHAPPENED(r13)
2159 cmpwi r10,PACA_IRQ_DEC
2164 b MASKED_DEC_HANDLER_LABEL
2165 1: andi. r10,r10,PACA_IRQ_MUST_HARD_MASK
2168 mfspr r10,SPRN_HSRR1
2169 xori r10,r10,MSR_EE /* clear MSR_EE */
2170 mtspr SPRN_HSRR1,r10
2173 xori r10,r10,MSR_EE /* clear MSR_EE */
2176 ori r11,r11,PACA_IRQ_HARD_DIS
2177 stb r11,PACAIRQHAPPENED(r13)
2181 ld r9,PACA_EXGEN+EX_R9(r13)
2182 ld r10,PACA_EXGEN+EX_R10(r13)
2183 ld r11,PACA_EXGEN+EX_R11(r13)
2184 /* returns to kernel where r13 must be set up, so don't restore it */
2191 MASKED_DEC_HANDLER(\hsrr\())
2194 TRAMP_REAL_BEGIN(stf_barrier_fallback)
2195 std r9,PACA_EXRFI+EX_R9(r13)
2196 std r10,PACA_EXRFI+EX_R10(r13)
2198 ld r9,PACA_EXRFI+EX_R9(r13)
2199 ld r10,PACA_EXRFI+EX_R10(r13)
2207 TRAMP_REAL_BEGIN(rfi_flush_fallback)
2210 std r1,PACA_EXRFI+EX_R12(r13)
2211 ld r1,PACAKSAVE(r13)
2212 std r9,PACA_EXRFI+EX_R9(r13)
2213 std r10,PACA_EXRFI+EX_R10(r13)
2214 std r11,PACA_EXRFI+EX_R11(r13)
2216 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
2217 ld r11,PACA_L1D_FLUSH_SIZE(r13)
2218 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
2220 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
2222 /* order ld/st prior to dcbt stop all streams with flushing */
2226 * The load adresses are at staggered offsets within cachelines,
2227 * which suits some pipelines better (on others it should not
2231 ld r11,(0x80 + 8)*0(r10)
2232 ld r11,(0x80 + 8)*1(r10)
2233 ld r11,(0x80 + 8)*2(r10)
2234 ld r11,(0x80 + 8)*3(r10)
2235 ld r11,(0x80 + 8)*4(r10)
2236 ld r11,(0x80 + 8)*5(r10)
2237 ld r11,(0x80 + 8)*6(r10)
2238 ld r11,(0x80 + 8)*7(r10)
2243 ld r9,PACA_EXRFI+EX_R9(r13)
2244 ld r10,PACA_EXRFI+EX_R10(r13)
2245 ld r11,PACA_EXRFI+EX_R11(r13)
2246 ld r1,PACA_EXRFI+EX_R12(r13)
2250 TRAMP_REAL_BEGIN(hrfi_flush_fallback)
2253 std r1,PACA_EXRFI+EX_R12(r13)
2254 ld r1,PACAKSAVE(r13)
2255 std r9,PACA_EXRFI+EX_R9(r13)
2256 std r10,PACA_EXRFI+EX_R10(r13)
2257 std r11,PACA_EXRFI+EX_R11(r13)
2259 ld r10,PACA_RFI_FLUSH_FALLBACK_AREA(r13)
2260 ld r11,PACA_L1D_FLUSH_SIZE(r13)
2261 srdi r11,r11,(7 + 3) /* 128 byte lines, unrolled 8x */
2263 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r11) /* Stop prefetch streams */
2265 /* order ld/st prior to dcbt stop all streams with flushing */
2269 * The load adresses are at staggered offsets within cachelines,
2270 * which suits some pipelines better (on others it should not
2274 ld r11,(0x80 + 8)*0(r10)
2275 ld r11,(0x80 + 8)*1(r10)
2276 ld r11,(0x80 + 8)*2(r10)
2277 ld r11,(0x80 + 8)*3(r10)
2278 ld r11,(0x80 + 8)*4(r10)
2279 ld r11,(0x80 + 8)*5(r10)
2280 ld r11,(0x80 + 8)*6(r10)
2281 ld r11,(0x80 + 8)*7(r10)
2286 ld r9,PACA_EXRFI+EX_R9(r13)
2287 ld r10,PACA_EXRFI+EX_R10(r13)
2288 ld r11,PACA_EXRFI+EX_R11(r13)
2289 ld r1,PACA_EXRFI+EX_R12(r13)
2294 * Real mode exceptions actually use this too, but alternate
2295 * instruction code patches (which end up in the common .text area)
2296 * cannot reach these if they are put there.
2298 USE_FIXED_SECTION(virt_trampolines)
2299 MASKED_INTERRUPT EXC_STD
2300 MASKED_INTERRUPT EXC_HV
2302 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
2303 TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
2305 * Here all GPRs are unchanged from when the interrupt happened
2306 * except for r13, which is saved in SPRG_SCRATCH0.
2308 mfspr r13, SPRN_SRR0
2310 mtspr SPRN_SRR0, r13
2315 TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
2317 * Here all GPRs are unchanged from when the interrupt happened
2318 * except for r13, which is saved in SPRG_SCRATCH0.
2320 mfspr r13, SPRN_HSRR0
2322 mtspr SPRN_HSRR0, r13
2329 * Ensure that any handlers that get invoked from the exception prologs
2330 * above are below the first 64KB (0x10000) of the kernel image because
2331 * the prologs assemble the addresses of these handlers using the
2332 * LOAD_HANDLER macro, which uses an ori instruction.
2335 /*** Common interrupt handlers ***/
2339 * Relocation-on interrupts: A subset of the interrupts can be delivered
2340 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
2341 * it. Addresses are the same as the original interrupt addresses, but
2342 * offset by 0xc000000000004000.
2343 * It's impossible to receive interrupts below 0x300 via this mechanism.
2344 * KVM: None of these traps are from the guest ; anything that escalated
2345 * to HV=1 from HV=0 is delivered via real mode handlers.
2349 * This uses the standard macro, since the original 0x300 vector
2350 * only has extra guff for STAB-based processors -- which never
2354 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
2355 b __ppc64_runlatch_on
2357 USE_FIXED_SECTION(virt_trampolines)
2359 * The __end_interrupts marker must be past the out-of-line (OOL)
2360 * handlers, so that they are copied to real address 0x100 when running
2361 * a relocatable kernel. This ensures they can be reached from the short
2362 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
2363 * directly, without using LOAD_HANDLER().
2366 .globl __end_interrupts
2368 DEFINE_FIXED_SYMBOL(__end_interrupts)
2370 #ifdef CONFIG_PPC_970_NAP
2371 EXC_COMMON_BEGIN(power4_fixup_nap)
2373 std r9,TI_LOCAL_FLAGS(r11)
2374 ld r10,_LINK(r1) /* make idle task do the */
2375 std r10,_NIP(r1) /* equivalent of a blr */
2379 CLOSE_FIXED_SECTION(real_vectors);
2380 CLOSE_FIXED_SECTION(real_trampolines);
2381 CLOSE_FIXED_SECTION(virt_vectors);
2382 CLOSE_FIXED_SECTION(virt_trampolines);
2389 .balign IFETCH_ALIGN_BYTES
2391 #ifdef CONFIG_PPC_BOOK3S_64
2392 lis r0,(DSISR_BAD_FAULT_64S | DSISR_DABRMATCH | DSISR_KEYFAULT)@h
2393 ori r0,r0,DSISR_BAD_FAULT_64S@l
2394 and. r0,r4,r0 /* weird error? */
2395 bne- handle_page_fault /* if not, try to insert a HPTE */
2396 ld r11, PACA_THREAD_INFO(r13)
2397 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
2398 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
2399 bne 77f /* then don't call hash_page now */
2402 * r3 contains the faulting address
2404 * r5 contains the trap number
2407 * at return r3 = 0 for success, 1 for page fault, negative for error
2411 bl __hash_page /* build HPTE if possible */
2412 cmpdi r3,0 /* see if __hash_page succeeded */
2415 beq fast_exc_return_irq /* Return from exception on success */
2420 /* Reload DSISR into r4 for the DABR check below */
2422 #endif /* CONFIG_PPC_BOOK3S_64 */
2424 /* Here we have a page fault that hash_page can't handle. */
2426 11: andis. r0,r4,DSISR_DABRMATCH@h
2427 bne- handle_dabr_fault
2430 addi r3,r1,STACK_FRAME_OVERHEAD
2433 beq+ ret_from_except_lite
2436 addi r3,r1,STACK_FRAME_OVERHEAD
2441 /* We have a data breakpoint exception - handle it */
2446 addi r3,r1,STACK_FRAME_OVERHEAD
2449 * do_break() may have changed the NV GPRS while handling a breakpoint.
2450 * If so, we need to restore them with their updated values. Don't use
2451 * ret_from_except_lite here.
2456 #ifdef CONFIG_PPC_BOOK3S_64
2457 /* We have a page fault that hash_page could handle but HV refused
2462 addi r3,r1,STACK_FRAME_OVERHEAD
2469 * We come here as a result of a DSI at a point where we don't want
2470 * to call hash_page, such as when we are accessing memory (possibly
2471 * user memory) inside a PMU interrupt that occurred while interrupts
2472 * were soft-disabled. We want to invoke the exception handler for
2473 * the access, or panic if there isn't a handler.
2477 addi r3,r1,STACK_FRAME_OVERHEAD
2483 * Here we have detected that the kernel stack pointer is bad.
2484 * R9 contains the saved CR, r13 points to the paca,
2485 * r10 contains the (bad) kernel stack pointer,
2486 * r11 and r12 contain the saved SRR0 and SRR1.
2487 * We switch to using an emergency stack, save the registers there,
2488 * and call kernel_bad_stack(), which panics.
2491 ld r1,PACAEMERGSP(r13)
2492 subi r1,r1,64+INT_FRAME_SIZE
2498 mfspr r12,SPRN_DSISR
2524 std r10,ORIG_GPR3(r1)
2525 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
2528 lhz r12,PACA_TRAP_SAVE(r13)
2530 addi r11,r1,INT_FRAME_SIZE
2535 ld r11,exception_marker@toc(r2)
2537 std r11,STACK_FRAME_OVERHEAD-16(r1)
2538 1: addi r3,r1,STACK_FRAME_OVERHEAD
2541 _ASM_NOKPROBE_SYMBOL(bad_stack);
2544 * When doorbell is triggered from system reset wakeup, the message is
2545 * not cleared, so it would fire again when EE is enabled.
2547 * When coming from local_irq_enable, there may be the same problem if
2548 * we were hard disabled.
2550 * Execute msgclr to clear pending exceptions before handling it.
2552 h_doorbell_common_msgclr:
2553 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
2557 doorbell_super_common_msgclr:
2558 LOAD_REG_IMMEDIATE(r3, PPC_DBELL_MSGTYPE << (63-36))
2560 b doorbell_super_common
2563 * Called from arch_local_irq_enable when an interrupt needs
2564 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
2565 * which kind of interrupt. MSR:EE is already off. We generate a
2566 * stackframe like if a real interrupt had happened.
2568 * Note: While MSR:EE is off, we need to make sure that _MSR
2569 * in the generated frame has EE set to 1 or the exception
2570 * handler will not properly re-enable them.
2572 * Note that we don't specify LR as the NIP (return address) for
2573 * the interrupt because that would unbalance the return branch
2576 _GLOBAL(__replay_interrupt)
2577 /* We are going to jump to the exception common code which
2578 * will retrieve various register values from the PACA which
2579 * we don't give a damn about, so we don't bother storing them.
2582 LOAD_REG_ADDR(r11, replay_interrupt_return)
2586 beq decrementer_common
2589 beq h_virt_irq_common
2591 beq hardware_interrupt_common
2592 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_300)
2594 beq performance_monitor_common
2597 beq h_doorbell_common_msgclr
2599 beq hmi_exception_common
2602 beq doorbell_super_common_msgclr
2603 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
2604 replay_interrupt_return:
2607 _ASM_NOKPROBE_SYMBOL(__replay_interrupt)
projects / linux-2.6-block.git / blob